void DMA1_Stream4_IRQHandler(void) {
if(DMA_GetFlagStatus(DMA1_Stream4, DMA_FLAG_TCIF4) == SET) {
interruptDmaI2c_Tx();
DMA_ClearFlag(DMA1_Stream4, DMA_FLAG_TCIF4);
}
return;
}
void DMA1_Stream5_IRQHandler(void) {
if(DMA_GetFlagStatus(DMA1_Stream5, DMA_FLAG_TCIF5) == SET) {
interruptDmaSpi();
DMA_ClearFlag(DMA1_Stream5, DMA_FLAG_TCIF5);
}
return;
}
/* This function sends data bytes out to a string of WS2812s
* The first argument is a pointer to the first RGB triplet to be sent
* The seconds argument is the number of LEDs in the chain
*
* This will result in the RGB triplet passed by argument 1 being sent to
* the LED that is the furthest away from the controller (the point where
* data is injected into the chain)
*/
void WS2812_send2(const uint8_t (*color)[3], const uint16_t _len)
{
int i, j;
uint8_t led;
uint16_t memaddr;
uint16_t buffersize;
uint16_t len = _len;
// Byte order mapping. 0 is red, 1 is green, 2 is blue
const uint8_t pix_map[3] = {0, 2, 1};
buffersize = (len*24); // number of bytes needed is #LEDs * 24 bytes + 42 trailing bytes
memaddr = 0; // reset buffer memory index
led = 0; // reset led index
// fill transmit buffer with correct compare values to achieve
// correct pulse widths according to color values
while (len)
{
for (i = 0; i < 3; i++)
{
for (j = 0; j < 8; j++) // GREEN data
{
if ( (color[led][pix_map[i]]<<j) & 0x80 ) // data sent MSB first, j = 0 is MSB j = 7 is LSB
{
LED_BYTE_Buffer[memaddr] = TIM_COMPARE_LOGIC_1; // compare value for logical 1
}
else
{
LED_BYTE_Buffer[memaddr] = TIM_COMPARE_LOGIC_0; // compare value for logical 0
}
memaddr++;
}
}
led++;
len--;
}
LED_BYTE_Buffer[memaddr++] = 0;
LED_BYTE_Buffer[memaddr++] = 0;
DMA_SetCurrDataCounter(DMA_STREAM, buffersize + 2); // load number of bytes to be transferred
// PAP: Clear the timer's counter and set the compare value to 0. This
// sets the output low on start and gives us a full cycle to set up DMA.
TIM_SetCounter(PWM_TIMER, 0);
TIM_SetCompare1(PWM_TIMER, 0);
TIM_Cmd(PWM_TIMER, ENABLE); // enable Timer 3
// PAP: Start DMA transfer after starting the timer. This prevents the
// DMA/PWM from dropping the first bit.
DMA_Cmd(DMA_STREAM, ENABLE); // enable DMA channel 6
while(!DMA_GetFlagStatus(DMA_STREAM, DMA_TCIF)); // wait until transfer complete
TIM_Cmd(PWM_TIMER, DISABLE); // disable Timer 3
DMA_Cmd(DMA_STREAM, DISABLE); // disable DMA channel 6
DMA_ClearFlag(DMA_STREAM, DMA_TCIF); // clear DMA1 Channel 6 transfer complete flag
}
/**
* @brief This function handles second motor DMAx TC interrupt request.
* Required only for R1 with rep rate > 1
* @param None
* @retval None
*/
void DMAx_R1_M2_IRQHandler(void)
{
if (DMA_GetFlagStatus(DMAx_R1_M2_Stream,DMAx_R1_M2_Flag) == SET)
{
DMA_ClearFlag(DMAx_R1_M2_Stream,DMAx_R1_M2_Flag);
Exec_IRQ_Handler(MC_IRQ_PWMNCURRFDBK_2,2);
}
}
void ws2811DMAHandler(DMA_Channel_TypeDef *channel)
{
if (DMA_GetFlagStatus(WS2811_DMA_TC_FLAG)) {
ws2811LedDataTransferInProgress = 0;
DMA_Cmd(channel, DISABLE);
DMA_ClearFlag(WS2811_DMA_TC_FLAG);
}
}
//DMA---USART1传输
void DMA1_USART1_SEND(u32 SendBuff,u16 len)
{
MYDMA_Config(DMA1_Channel4,(u32)&USART1->DR,(u32)SendBuff,len);//DMA1通道4,外设为串口1,存储器为SendBuff,长度len.
USART_DMACmd(USART1, USART_DMAReq_Tx, ENABLE);
MYDMA_Enable(DMA1_Channel4);
while(DMA_GetFlagStatus(DMA1_FLAG_TC4) != SET);
DMA_ClearFlag(DMA1_FLAG_TC4); //清除发送完成标志
}
void DMA1_Channel3_IRQHandler(void)
{
if (DMA_GetFlagStatus(DMA1_FLAG_TC3)) {
ws2811LedDataTransferInProgress = 0;
DMA_Cmd(DMA1_Channel3, DISABLE); // disable DMA channel 6
DMA_ClearFlag(DMA1_FLAG_TC3); // clear DMA1 Channel 6 transfer complete flag
}
}
// Waits for DMA transfer to complete
static void oled_wait_dma(void) {
while(!DMA_GetFlagStatus(DMA2_Stream3, DMA_FLAG_TCIF3)) {
if(!DMA2_Stream3->NDTR) break;
}
DMA_ClearITPendingBit(DMA2_Stream3, DMA_IT_TCIF3);
DMA_Cmd(DMA2_Stream3, DISABLE);
SPI_I2S_DMACmd(OLED_SPI, SPI_I2S_DMAReq_Tx, DISABLE);
}
void transponderDMAHandler(DMA_Channel_TypeDef *channel)
{
if (DMA_GetFlagStatus(TRANSPONDER_DMA_TC_FLAG)) {
transponderIrDataTransferInProgress = 0;
DMA_Cmd(channel, DISABLE);
DMA_ClearFlag(TRANSPONDER_DMA_TC_FLAG);
}
}
void USART_DMA_send(USART_TypeDef* USARTx, DMA_Channel_TypeDef* DMAy_Channelx, char *buf, uint8_t len){
//
DMA_InitTypeDef DMA_InitStructure;
// DMA на запись
DMA_DeInit(DMAy_Channelx); //DMA1_Channel4
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t) &(USARTx->DR);
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) buf;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_BufferSize = len;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_Low;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init(DMA1_Channel4, &DMA_InitStructure);
// старт цикла отправки
USART_ClearFlag(USARTx, USART_FLAG_TC | USART_FLAG_TXE);
USART_DMACmd(USARTx, USART_DMAReq_Tx, ENABLE);
DMA_Cmd(DMAy_Channelx, ENABLE);
// wait until transmission complite from dma
if (DMAy_Channelx == DMA1_Channel1) {
while (DMA_GetFlagStatus(DMA1_FLAG_TC1) == RESET) {
}
}
if (DMAy_Channelx == DMA1_Channel2) {
while (DMA_GetFlagStatus(DMA1_FLAG_TC2) == RESET) {
}
}
if (DMAy_Channelx == DMA1_Channel3) {
while (DMA_GetFlagStatus(DMA1_FLAG_TC3) == RESET) {
}
}
if (DMAy_Channelx == DMA1_Channel4) {
while (DMA_GetFlagStatus(DMA1_FLAG_TC4) == RESET) {
}
}
DMA_Cmd(DMAy_Channelx, DISABLE);
USART_DMACmd(USARTx, USART_DMAReq_Tx, DISABLE);
}
uint8_t i2cMgr_t::CheckManyWriting() {
// Check if DMA transfer ended
if (DMA_GetFlagStatus(I2C_DMA_FLAG_TC_TX) == SET)
if (I2C_GetFlagStatus(I2C1, I2C_FLAG_BUSY) == RESET)
return I2C_OK;
if (Delay.Elapsed(&Timer, I2C_TIMEOUT_MS)) return I2C_ERR_TIMEOUT;
return I2C_WAITING;
}
// READ (done)
int dmaRcvBytes(SPI_TypeDef *SPIx, void *rbuf, unsigned count, int half) {
DMA_InitTypeDef DMA_InitStructure;
uint16_t dummy[] = {0xffff};
DMA_DeInit(DMA1_Channel4);
DMA_DeInit(DMA1_Channel5);
// Common to both channels
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&(SPIx->DR));
DMA_InitStructure.DMA_PeripheralDataSize = (half) ? DMA_PeripheralDataSize_HalfWord : DMA_PeripheralDataSize_Byte;
DMA_InitStructure.DMA_MemoryDataSize = (half) ? DMA_MemoryDataSize_HalfWord : DMA_MemoryDataSize_Byte;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_BufferSize = count;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
// Rx Channel
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t)rbuf;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralSRC;
DMA_Init(DMA1_Channel4, &DMA_InitStructure);
// Tx channel
DMA_InitStructure.DMA_MemoryBaseAddr = (uint32_t) dummy;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Disable;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_Init(DMA1_Channel5, &DMA_InitStructure);
// Enable channels
DMA_Cmd(DMA1_Channel4, ENABLE);
DMA_Cmd(DMA1_Channel5, ENABLE);
// Enable SPI TX/RX request
SPI_I2S_DMACmd(SPIx, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, ENABLE);
// Wait for completion
while (DMA_GetFlagStatus(DMA1_FLAG_TC4) == RESET);
// Disable channels
DMA_Cmd(DMA1_Channel4, DISABLE);
DMA_Cmd(DMA1_Channel5, DISABLE);
SPI_I2S_DMACmd(SPIx, SPI_I2S_DMAReq_Rx | SPI_I2S_DMAReq_Tx, DISABLE);
return count;
}
/*=====================================================================================================*/
void I2C_RX_DMA_IRQ(void)
{
if (DMA_GetFlagStatus(DMAx_RX_STREAM, DMAx_RX_FLAG_TCIF) != RESET) {
I2C_GenerateSTOP(I2Cx, ENABLE);
DMA_Cmd(DMAx_RX_STREAM, DISABLE);
DMA_ClearFlag(DMAx_RX_STREAM, DMAx_RX_FLAG_TCIF);
*I2C_ReadPtr = 0;
}
}
void DMA1_Stream5_IRQHandler (void)
{
if (DMA_GetITStatus(DMA1_Stream5, DMA_IT_TCIF5)
&& DMA_GetFlagStatus(DMA1_Stream5, DMA_FLAG_TCIF5)) {
DMA_ClearITPendingBit(DMA1_Stream5, DMA_IT_TCIF5);
DMA_ClearFlag(DMA1_Stream5, DMA_FLAG_TCIF5);
}
NVIC_ClearPendingIRQ(DMA1_Stream5_IRQn);
}
/**
* Функция обработки прерываний RX
*/
void halSPI1_Interrupt_RX_Handler(void)
{
if (DMA_GetFlagStatus(channel, SPI1_MASTER_Rx_DMA_FLAG_TC) == SET)
{
SPI_error = SPI_TRANSFER_COMPLETE;
DMA_ClearFlag (channel, SPI1_MASTER_Rx_DMA_FLAG_TC);
DMA_ClearITPendingBit(channel, SPI1_MASTER_Rx_DMA_FLAG_TC);
halSPI1_SS_off();
}
if (DMA_GetFlagStatus(channel, SPI1_MASTER_Rx_DMA_FLAG_TE) == SET)
{
SPI_error = SPI_TRANSFER_ERROR_FAIL;
DMA_ClearFlag (channel, SPI1_MASTER_Rx_DMA_FLAG_TE);
DMA_ClearITPendingBit(channel, SPI1_MASTER_Rx_DMA_FLAG_TE);
halSPI1_SS_off();
}
}
uint8_t * OV7670_capture_image()
{
DCMI_InitTypeDef DCMI_InitStructure;
DMA_InitTypeDef DMA_InitStructure;
/* DMA2 Stream1 Configuration */
DMA_DeInit(DMA2_Stream1);
DMA_InitStructure.DMA_Channel = DMA_Channel_1;
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)(&DCMI->DR);
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t) image_buffer;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralToMemory;
DMA_InitStructure.DMA_BufferSize = (IMG_SIZE/sizeof(uint32_t));
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Enable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_HalfFull;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
/* DMA2 IRQ channel Configuration */
DMA_Init(DMA2_Stream1, &DMA_InitStructure);
DMA_Cmd(DMA2_Stream1, ENABLE);
DCMI_Cmd(ENABLE);
DCMI_CaptureCmd(ENABLE);
int temp;
// Wait until DCMI DMA Rx transfer is complete
while (DMA_GetFlagStatus(DMA2_Stream1, DMA_FLAG_TCIF1) == RESET)
{
temp = DMA_GetCurrDataCounter(DMA2_Stream1);
temp = DCMI->CR;
temp = DCMI->RISR;
}
/* Clear all DMA Streams flags */
DMA_ClearFlag(DMA2_Stream1, DMA_FLAG_HTIF1 | DMA_FLAG_TCIF1);
/* Disable the DMA Rx Stream */
DMA_Cmd(DMA2_Stream1, DISABLE);
//Do not disable DCMI peripheral untill DMA disable command gets through
while(DMA_GetCmdStatus(DMA2_Stream1) == ENABLE)
{}
DCMI_Cmd(DISABLE);
return (uint8_t*) image_buffer;
}
/**
* @brief Interrupt for half and full buffer transfer
*
* This interrupt handler swaps between the two halfs of the double buffer to make
* sure the ahrs uses the most recent data. Only swaps data when AHRS is idle, but
* really this is a pretense of a sanity check since the DMA engine is consantly
* running in the background. Keep an eye on the ekf_too_slow variable to make sure
* it's keeping up.
*/
void PIOS_INTERNAL_ADC_DMA_Handler()
{
if(!PIOS_INTERNAL_ADC_validate(static_adc_dev))
return;
if (DMA_GetFlagStatus(static_adc_dev->cfg->full_flag /*DMA1_IT_TC1*/)) { // whole double buffer filled
static_adc_dev->valid_data_buffer = &static_adc_dev->raw_data_buffer[static_adc_dev->dma_half_buffer_size];
DMA_ClearFlag(static_adc_dev->cfg->full_flag);
PIOS_INTERNAL_ADC_downsample_data((uint32_t)static_adc_dev);
}
else if (DMA_GetFlagStatus(static_adc_dev->cfg->half_flag /*DMA1_IT_HT1*/)) {
static_adc_dev->valid_data_buffer = &static_adc_dev->raw_data_buffer[0];
DMA_ClearFlag(static_adc_dev->cfg->half_flag);
PIOS_INTERNAL_ADC_downsample_data((uint32_t)static_adc_dev);
}
else {
// This should not happen, probably due to transfer errors
DMA_ClearFlag(static_adc_dev->cfg->dma.irq.flags /*DMA1_FLAG_GL1*/);
}
}
void DMA1_Channel1_IRQHandler(void){
if (DMA_GetFlagStatus(DMA1_FLAG_TC1) == SET) {
DMA_ClearFlag(DMA1_FLAG_TC1);
if(adcfinish==false){
//every 0.5s
everydiffdo(long long,__adctime,timerTick05ms/1000){
memcpy(adcbufbak,adcbuf+2,sizeof(adcbufbak));
adcfinish = true;
}
}
void DMA1_Stream0_IRQHandler (void)
{
if (DMA_GetITStatus(DMA1_Stream0, DMA_IT_TCIF0)
&& DMA_GetFlagStatus(DMA1_Stream0, DMA_FLAG_TCIF0)) {
LEDs_greenToggle();
DMA_ClearITPendingBit(DMA1_Stream0, DMA_IT_TCIF0);
DMA_ClearFlag(DMA1_Stream0, DMA_FLAG_TCIF0);
}
NVIC_ClearPendingIRQ(DMA1_Stream0_IRQn);
}
/*USARTx使用DMA方式发送数据*/
void sys_usartSendData(uint8_t *Data, uint32_t SendSize)
{
while(DMA_GetCurrDataCounter(DMA1_Channel4));
while(!DMA_GetFlagStatus(DMA1_FLAG_TC4));
DMA_ClearFlag(DMA1_FLAG_TC4);
DMA1_Channel4->CCR &= 0xffffffe;
DMA1_Channel4->CMAR = (uint32_t)Data;
DMA1_Channel4->CNDTR = SendSize;
DMA1_Channel4->CCR |= 0x00000001;
}
uint8_t nRF24L01_WriteRegister(uint8_t cmd, uint8_t* pdata, uint8_t len)
{
uint8_t i, status;
uint8_t txbuf[33] = {0xFF};
for(i = 0; i < len; i++)
txbuf[i+1] = *(pdata+i);
txbuf[0] = cmd;
SPI_I2S_DMACmd(NRF24L01_SPI, SPI_I2S_DMAReq_Tx, ENABLE);
SPI_I2S_DMACmd(NRF24L01_SPI, SPI_I2S_DMAReq_Rx, ENABLE);
GPIO_ResetBits(NRF24L01_SPI_GPIO, NRF24L01_GPIO_CSN);
nRF24L01_Delay(5);
nRF24L01_TxDMAInit((uint8_t*)&txbuf, len+1);
nRF24L01_RxDMAInit(&status, 1);
DMA_Cmd(SPIx_TX_DMA_STREAM, ENABLE);
DMA_Cmd(SPIx_RX_DMA_STREAM, ENABLE);
while (DMA_GetFlagStatus(SPIx_TX_DMA_STREAM,SPIx_TX_DMA_TCIF)==RESET);
while (DMA_GetFlagStatus(SPIx_RX_DMA_STREAM,SPIx_RX_DMA_TCIF)==RESET);
/* Clear DMA Transfer Complete Flags */
DMA_ClearFlag(SPIx_TX_DMA_STREAM, SPIx_TX_DMA_TCIF);
DMA_ClearFlag(SPIx_RX_DMA_STREAM, SPIx_RX_DMA_TCIF);
DMA_Cmd(SPIx_RX_DMA_STREAM, DISABLE);
DMA_Cmd(SPIx_TX_DMA_STREAM, DISABLE);
SPI_I2S_DMACmd(NRF24L01_SPI, SPI_I2S_DMAReq_Tx, DISABLE);
SPI_I2S_DMACmd(NRF24L01_SPI, SPI_I2S_DMAReq_Rx, DISABLE);
nRF24L01_Delay(5);
GPIO_SetBits(NRF24L01_SPI_GPIO, NRF24L01_GPIO_CSN);
return status;
}
/*************************************************************************
* Function Name: SPI2_DmaHandler
* Parameters: none
* Return: none
*
* Description: Interrupt handler of the SPI2 DMA.
*
*************************************************************************/
void SPI2_RxDmaHandler(void)
{
if (DMA_GetFlagStatus(DMA_FLAG_TE4) == SET)
{
DMA_ClearITPendingBit(DMA_IT_GL5);
DMA_Cmd(DMA_Channel5,DISABLE);
DMA_Cmd(DMA_Channel4,DISABLE);
}
DMA_ClearITPendingBit(DMA_IT_GL4);
TransferStatus = FALSE;
}
/********************************************************************************************************
**函数信息 ：DMAcheckStatus(uint32_t DMA_FLAG)
**功能描述 : 查询DMA的标志位
**输入参数 ：uint32_t DMA_FLAG，DMA的状态标志位
**输出参数 ：无
********************************************************************************************************/
void DMAcheckStatus(uint32_t DMA_FLAG)
{
while(1)
{
if(DMA_GetFlagStatus(DMA_FLAG))
{
DMA_ClearFlag(DMA_FLAG);
break;
}
}
}
/**
* @brief HASH MD5 Digest computation (using DMA for data transfer)
* @note DMA2 stream7 channel2 is used to transfer data from memory
* (MessageToHash[] array) to HASH Peripheral (the INPUT data register).
* @param None
* @retval None
*/
static void HASH_MD5_DMA(void)
{
HASH_InitTypeDef HASH_InitStructure;
DMA_InitTypeDef DMA_InitStructure;
/* HASH Configuration */
HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
HASH_Init(&HASH_InitStructure);
/*DMA Configuration*/
DMA_DeInit(DMA2_Stream7);
DMA_InitStructure.DMA_Channel = DMA_Channel_2;
DMA_InitStructure.DMA_PeripheralBaseAddr = HASH_DIN_REG_ADDR;
DMA_InitStructure.DMA_Memory0BaseAddr = (uint32_t)MessageToHash;
DMA_InitStructure.DMA_DIR = DMA_DIR_MemoryToPeripheral;
DMA_InitStructure.DMA_BufferSize = SIZE_MSG_TO_HASH_IN_WORDS;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable;
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_Word;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_Word;
DMA_InitStructure.DMA_Mode = DMA_Mode_Normal;
DMA_InitStructure.DMA_Priority = DMA_Priority_High;
DMA_InitStructure.DMA_FIFOMode = DMA_FIFOMode_Disable;
DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
DMA_InitStructure.DMA_MemoryBurst = DMA_MemoryBurst_Single;
DMA_InitStructure.DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
/* Configure the DMA Stream */
DMA_Init(DMA2_Stream7, &DMA_InitStructure);
/* Enable HASH DMA */
HASH_DMACmd(ENABLE);
/* Enable DMA2 Transfer */
DMA_Cmd(DMA2_Stream7, ENABLE);
/* Note : When the DMA is enabled, it provides the information to the hash
processor when it is transferring the last data word. Then the
padding and digest computation are performed automatically as if
DCAL had been written to 1.*/
/* wait until DMA Transfer completed */
while (DMA_GetFlagStatus(DMA2_Stream7, DMA_FLAG_TCIF7) == RESET);
/* wait until the Busy flag is RESET */
while (HASH_GetFlagStatus(HASH_FLAG_BUSY) != RESET);
/* Get the MD5 Digest */
HASH_GetDigest(&MsgDigest);
}
/* I2C1_DMA_TX_IRQHandler */
void DMA1_Stream6_IRQHandler()
{
NVIC_ClearPendingIRQ(DMA1_Stream6_IRQn);
if(DMA_GetFlagStatus(I2C1_DMA_STREAM_TX, I2C1_DMA_TX_FLAG_TCIF) != RESET)
{
I2C_GenerateSTOP(I2C1, ENABLE);
DMA_Cmd(I2C1_DMA_STREAM_TX, DISABLE);
DMA_ClearFlag(I2C1_DMA_STREAM_TX, I2C1_DMA_TX_FLAG_TCIF);
I2C1_DMA_TX_Semaphore = 1;
}
}
void CheckVoltage()
{
/* Check the voltage*/
ADC_SoftwareStartConvCmd(ADC1, ENABLE);
/*wait for the TC14 to be 1*/
while(DMA_GetFlagStatus(DMA1_FLAG_TC1)==0);
DMA_ClearFlag(DMA1_FLAG_TC1);
/*The value is in ADC1ConvertedValue*/
ADC1ConvertedValue = ADC1ConvertedValue;
}
void DMA1_Channel4_IRQHandler(void)
{
//判断是否为DMA发送完成中断
if(DMA_GetFlagStatus(DMA1_FLAG_TC4)==SET)
{
//LED关闭
LEDG_INVERSE();
DMA_Cmd(DMA1_Channel4,DISABLE); //关闭DMA通道
DMA_ClearFlag(DMA1_FLAG_TC4|DMA1_FLAG_GL4); //清除DMA标志位
send_flag = 0;
}
}
// Blocking SPI transfer
static void spi_transfer() {
// Enable NSS output for master mode
SPI_SSOutputCmd(SPI1, ENABLE);
// Enable DMA1 Channel1 Transfer Complete interrupt
//DMA_ITConfig(SPI1_TX_DMA_CHANNEL, DMA_IT_TC, ENABLE);
// Enable the DMA channels
SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Rx, ENABLE);
SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx, ENABLE);
DMA_Cmd(SPI1_RX_DMA_CHANNEL, ENABLE);
DMA_Cmd(SPI1_TX_DMA_CHANNEL, ENABLE);
// Wait for everything to finish
//TODO: Implement timeout so we don't get stuck
//uint32_t TimeOut = USER_TIMEOUT;
while ((DMA_GetFlagStatus(SPI1_RX_DMA_FLAG_TC) == RESET));
while ((DMA_GetFlagStatus(SPI1_TX_DMA_FLAG_TC) == RESET));
/* The BSY flag can be monitored to ensure that the SPI communication is complete.
This is required to avoid corrupting the last transmission before disabling
the SPI or entering the Stop mode. The software must first wait until TXE=1
and then until BSY=0.*/
while ((SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_TXE) == RESET));
while ((SPI_I2S_GetFlagStatus(SPI1, SPI_I2S_FLAG_BSY) == SET));
// End the SPI transaction and DMA
// Clear DMA1 global flags
DMA_ClearFlag(SPI1_TX_DMA_FLAG_GL);
DMA_ClearFlag(SPI1_RX_DMA_FLAG_GL);
// Disable the DMA channels
DMA_Cmd(SPI1_RX_DMA_CHANNEL, DISABLE);
DMA_Cmd(SPI1_TX_DMA_CHANNEL, DISABLE);
// Disable the SPI Rx and Tx DMA requests
SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Rx, DISABLE);
SPI_I2S_DMACmd(SPI1, SPI_I2S_DMAReq_Tx, DISABLE);
}
/**
* @brief To set and config blutooth then send data to the register.
* @param rate, baudrate has setted on AT mode; addr, the memory base address; leng, the length of data you want to send.
* @retval None.
*/
void BT_Usart2_Config(uint32_t rate, uint32_t addr, uint8_t leng)
{
USART_InitTypeDef USART_InitStructure;
GPIO_InitTypeDef GPIO_InitStructure;
DMA_InitTypeDef DMA_InitStructure;
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE);
GPIO_InitStructure.GPIO_Pin = (GPIO_Pin_2/*TX, PA2*/ | GPIO_Pin_3/*RX, PA3*/);
GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
GPIO_Init(GPIOA, &GPIO_InitStructure);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_7);
GPIO_PinAFConfig(GPIOA, GPIO_PinSource3, GPIO_AF_7);
USART_InitStructure.USART_BaudRate = rate;
USART_InitStructure.USART_WordLength = USART_WordLength_8b;
USART_InitStructure.USART_StopBits = USART_StopBits_1;
USART_InitStructure.USART_Parity = USART_Parity_No;
USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
USART_InitStructure.USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
USART_DeInit(USART2);
USART_Init(USART2, &USART_InitStructure);
USART_Cmd(USART2, ENABLE);
RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1,ENABLE);
DMA_StructInit(&DMA_InitStructure);
DMA_DeInit(DMA1_Channel7);
DMA_InitStructure.DMA_PeripheralBaseAddr = (uint32_t)USART2 + 0x28; //////
DMA_InitStructure.DMA_MemoryBaseAddr = (u32)&addr;
DMA_InitStructure.DMA_DIR = DMA_DIR_PeripheralDST;
DMA_InitStructure.DMA_BufferSize = leng;
DMA_InitStructure.DMA_PeripheralInc = DMA_PeripheralInc_Disable; //address register is incremented or not
DMA_InitStructure.DMA_MemoryInc = DMA_MemoryInc_Enable;
DMA_InitStructure.DMA_PeripheralDataSize = DMA_PeripheralDataSize_HalfWord ;
DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord ;
DMA_InitStructure.DMA_Mode = DMA_Mode_Circular;
DMA_InitStructure.DMA_Priority = DMA_Priority_VeryHigh;
DMA_InitStructure.DMA_M2M = DMA_M2M_Disable;
DMA_Init(DMA1_Channel7,&DMA_InitStructure);
USART_ClearFlag(USART2,USART_FLAG_TC);
DMA_ClearFlag(DMA1_FLAG_TC7);
USART_DMACmd(USART2,USART_DMAReq_Tx,ENABLE);
DMA_Cmd(DMA1_Channel7,ENABLE);
sig_lam(2,1);
while (!DMA_GetFlagStatus(USART_FLAG_TC)){};
}
void PIOS_VIDEO_DMA_Handler(void)
{
if (DMA_GetFlagStatus(DMA1_Stream7,DMA_FLAG_TCIF7)) { // transfer completed load next line
DMA_ClearFlag(DMA1_Stream7,DMA_FLAG_TCIF7);
//PIOS_LED_Off(LED2);
/*if(gLineType == LINE_TYPE_GRAPHICS)
{
// Load new line
DMA_Cmd(dev_cfg->mask.dma.tx.channel, DISABLE);
DMA_Cmd(dev_cfg->level.dma.tx.channel, DISABLE);
DMA_MemoryTargetConfig(dev_cfg->level.dma.tx.channel,(uint32_t)&disp_buffer_level[line],DMA_Memory_0);
DMA_MemoryTargetConfig(dev_cfg->mask.dma.tx.channel,(uint32_t)&disp_buffer_mask[line],DMA_Memory_0);
//DMA_ClearFlag(dev_cfg->mask.dma.tx.channel,DMA_FLAG_TCIF5); // <-- TODO: HARDCODED
//DMA_ClearFlag(dev_cfg->level.dma.tx.channel,DMA_FLAG_TCIF5); // <-- TODO: HARDCODED
DMA_SetCurrDataCounter(dev_cfg->level.dma.tx.channel,BUFFER_LINE_LENGTH);
DMA_SetCurrDataCounter(dev_cfg->mask.dma.tx.channel,BUFFER_LINE_LENGTH);
}*/
//PIOS_LED_Toggle(LED2);
}
else if (DMA_GetFlagStatus(DMA1_Stream7,DMA_FLAG_HTIF7)) {
DMA_ClearFlag(DMA1_Stream7,DMA_FLAG_HTIF7);
}
else {
}
if (DMA_GetFlagStatus(DMA2_Stream5,DMA_FLAG_TCIF5)) { // whole double buffer filled
DMA_ClearFlag(DMA2_Stream5,DMA_FLAG_TCIF5);
//PIOS_LED_Toggle(LED3);
}
else if (DMA_GetFlagStatus(DMA2_Stream5,DMA_FLAG_HTIF5)) {
DMA_ClearFlag(DMA2_Stream5,DMA_FLAG_HTIF5);
}
else {
}
}
