bool PulsePositionInput::begin(uint8_t pin) { uint32_t channel; volatile void *reg; if (FTM0_MOD != 0xFFFF || FTM0_SC != (FTM_SC_CLKS(1) | FTM_SC_PS(0))) { FTM0_SC = 0; FTM0_CNT = 0; FTM0_MOD = 0xFFFF; FTM0_SC = FTM_SC_CLKS(1) | FTM_SC_PS(0); FTM0_MODE = 0; } switch (pin) { case 5: channel = 7; reg = &FTM0_C7SC; break; case 6: channel = 4; reg = &FTM0_C4SC; break; case 9: channel = 2; reg = &FTM0_C2SC; break; case 10: channel = 3; reg = &FTM0_C3SC; break; case 20: channel = 5; reg = &FTM0_C5SC; break; case 21: channel = 6; reg = &FTM0_C6SC; break; case 22: channel = 0; reg = &FTM0_C0SC; break; case 23: channel = 1; reg = &FTM0_C1SC; break; default: return false; } prev = 0; write_index = 255; available_flag = false; ftm = (struct ftm_channel_struct *)reg; ftm->csc = cscEdge; // input capture & interrupt on rising edge list[channel] = this; channelmask |= (1<<channel); *portConfigRegister(pin) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE; NVIC_SET_PRIORITY(IRQ_FTM0, 32); NVIC_ENABLE_IRQ(IRQ_FTM0); return true; }
/* ===================================================================*/ LDD_TDeviceData* TU2_Init(LDD_TUserData *UserDataPtr) { TU2_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID] == NULL) { /* Allocate device structure */ /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU2_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_FTM1__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC6: FTM1=1 */ SIM_SCGC6 |= SIM_SCGC6_FTM1_MASK; /* FTM1_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */ FTM1_MODE = (FTM_MODE_FAULTM(0x00) | FTM_MODE_WPDIS_MASK); /* Set up mode register */ /* FTM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */ FTM1_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00)); /* Clear status and control register */ /* FTM1_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */ FTM1_CNTIN = FTM_CNTIN_INIT(0x00); /* Clear counter initial register */ /* FTM1_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ FTM1_CNT = FTM_CNT_COUNT(0x00); /* Reset counter register */ /* FTM1_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,ICRST=0,DMA=0 */ FTM1_C0SC = 0x00U; /* Clear channel status and control register */ /* FTM1_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,ICRST=0,DMA=0 */ FTM1_C1SC = 0x00U; /* Clear channel status and control register */ /* FTM1_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0x8C9B */ FTM1_MOD = FTM_MOD_MOD(0x8C9B); /* Set up modulo register */ DeviceDataPrv->EnEvents = 0x0100U; /* Enable selected events */ /* NVIC_IPR4: PRI_18=1 */ NVIC_IPR4 = (uint32_t)((NVIC_IPR4 & (uint32_t)~(uint32_t)( NVIC_IP_PRI_18(0x02) )) | (uint32_t)( NVIC_IP_PRI_18(0x01) )); /* NVIC_ISER: SETENA31=0,SETENA30=0,SETENA29=0,SETENA28=0,SETENA27=0,SETENA26=0,SETENA25=0,SETENA24=0,SETENA23=0,SETENA22=0,SETENA21=0,SETENA20=0,SETENA19=0,SETENA18=1,SETENA17=0,SETENA16=0,SETENA15=0,SETENA14=0,SETENA13=0,SETENA12=0,SETENA11=0,SETENA10=0,SETENA9=0,SETENA8=0,SETENA7=0,SETENA6=0,SETENA5=0,SETENA4=0,SETENA3=0,SETENA2=0,SETENA1=0,SETENA0=0 */ NVIC_ISER = NVIC_ISER_SETENA18_MASK; /* NVIC_ICER: CLRENA31=0,CLRENA30=0,CLRENA29=0,CLRENA28=0,CLRENA27=0,CLRENA26=0,CLRENA25=0,CLRENA24=0,CLRENA23=0,CLRENA22=0,CLRENA21=0,CLRENA20=0,CLRENA19=0,CLRENA18=0,CLRENA17=0,CLRENA16=0,CLRENA15=0,CLRENA14=0,CLRENA13=0,CLRENA12=0,CLRENA11=0,CLRENA10=0,CLRENA9=0,CLRENA8=0,CLRENA7=0,CLRENA6=0,CLRENA5=0,CLRENA4=0,CLRENA3=0,CLRENA2=0,CLRENA1=0,CLRENA0=0 */ NVIC_ICER = 0x00U; /* FTM1_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=1,CPWMS=0,CLKS=1,PS=1 */ FTM1_SC = (FTM_SC_TOIE_MASK | FTM_SC_CLKS(0x01) | FTM_SC_PS(0x01)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU2_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
void lcd_backlight_hal_init(void) { // Setup Backlight SIM->SCGC6 |= SIM_SCGC6_FTM0; FTM0->CNT = 0; // Reset counter // PWM Period // 16-bit maximum FTM0->MOD = 0xFFFF; // Set FTM to PWM output - Edge Aligned, Low-true pulses #define CNSC_MODE FTM_SC_CPWMS | FTM_SC_PS(4) | FTM_SC_CLKS(0) CHANNEL_RED.CnSC = CNSC_MODE; CHANNEL_GREEN.CnSC = CNSC_MODE; CHANNEL_BLUE.CnSC = CNSC_MODE; // System clock, /w prescalar setting FTM0->SC = FTM_SC_CLKS(1) | FTM_SC_PS(PRESCALAR_DEFINE); CHANNEL_RED.CnV = 0; CHANNEL_GREEN.CnV = 0; CHANNEL_BLUE.CnV = 0; RGB_PORT_GPIO->PDDR |= (1 << RED_PIN); RGB_PORT_GPIO->PDDR |= (1 << GREEN_PIN); RGB_PORT_GPIO->PDDR |= (1 << BLUE_PIN); #define RGB_MODE PORTx_PCRn_SRE | PORTx_PCRn_DSE | PORTx_PCRn_MUX(4) RGB_PORT->PCR[RED_PIN] = RGB_MODE; RGB_PORT->PCR[GREEN_PIN] = RGB_MODE; RGB_PORT->PCR[BLUE_PIN] = RGB_MODE; }
void init_FTM0(void) { SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK|SIM_SCGC5_PORTC_MASK; PORTC_PCR1 = PORT_PCR_MUX(4); // S1 PORTC_PCR2 = PORT_PCR_MUX(4); // S2 PORTC_PCR3 = PORT_PCR_MUX(4); // S3 PORTC_PCR4 = PORT_PCR_MUX(4); // S4 PORTA_PCR1 = PORT_PCR_MUX(3); // S5 PORTA_PCR2 = PORT_PCR_MUX(3); // S6 SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; //SIM_SOPT2 &= ~(SIM_SOPT2_FTMSRC_MASK); SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; //SIM_SOPT2 |= SIM_SOPT2_FTMSRC(FTM_PLLFLL); FTM0_MOD = 350; FTM0_MODE |= FTM_MODE_WPDIS_MASK; FTM0_SC |= FTM_SC_PS(PS_4)|FTM_SC_CPWMS_MASK|FTM_SC_CLKS(FTM_CLK); FTM0_C0SC |= FTM_PWM_H; //S1 FTM0_C1SC |= FTM_PWM_L; //S2 FTM0_C2SC |= FTM_PWM_H; //S3 FTM0_C3SC |= FTM_PWM_L; //S4 FTM0_C6SC |= FTM_PWM_H; //S5 FTM0_C7SC |= FTM_PWM_L; //S6 //PORTA_PCR1 |= PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK; //GPIOA_PDDR |= (1 << 1); }
void pwmout_init(pwmout_t* obj, PinName pin) { // determine the channel PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); if (pwm == (PWMName)NC) error("PwmOut pin mapping failed"); unsigned int port = (unsigned int)pin >> PORT_SHIFT; unsigned int ftm_n = (pwm >> TPM_SHIFT); unsigned int ch_n = (pwm & 0xFF); SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); SIM->SCGC6 |= 1 << (SIM_SCGC6_FTM0_SHIFT + ftm_n); FTM_Type *ftm = (FTM_Type *)(FTM0_BASE + 0x1000 * ftm_n); ftm->MODE |= FTM_MODE_WPDIS_MASK; //write protection disabled ftm->CONF |= FTM_CONF_BDMMODE(3); ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(6); // (48)MHz / 64 = (0.75)MHz ftm->CONTROLS[ch_n].CnSC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* No Interrupts; High True pulses on Edge Aligned PWM */ ftm->PWMLOAD |= FTM_PWMLOAD_LDOK_MASK; //loading updated values enabled //ftm->SYNCONF |= FTM_SYNCONF_SWRSTCNT_MASK; ftm->MODE |= FTM_MODE_INIT_MASK; obj->CnV = &ftm->CONTROLS[ch_n].CnV; obj->MOD = &ftm->MOD; obj->CNT = &ftm->CNT; obj->SYNC = &ftm->SYNC; // default to 20ms: standard for servos, and fine for e.g. brightness control pwmout_period_ms(obj, 20); pwmout_write (obj, 0); // Wire pinout pinmap_pinout(pin, PinMap_PWM); }
void ftm0_isr(void) { if (FTM0_SC & 0x80) { FTM0_SC = FTM_SC_CLKS(1) | FTM_SC_PS(0); PulsePositionInput::overflow_count++; PulsePositionInput::overflow_inc = true; } uint8_t maskin = PulsePositionInput::channelmask; if ((maskin & 0x01) && (FTM0_C0SC & 0x80)) PulsePositionInput::list[0]->isr(); if ((maskin & 0x02) && (FTM0_C1SC & 0x80)) PulsePositionInput::list[1]->isr(); if ((maskin & 0x04) && (FTM0_C2SC & 0x80)) PulsePositionInput::list[2]->isr(); if ((maskin & 0x08) && (FTM0_C3SC & 0x80)) PulsePositionInput::list[3]->isr(); if ((maskin & 0x10) && (FTM0_C4SC & 0x80)) PulsePositionInput::list[4]->isr(); if ((maskin & 0x20) && (FTM0_C5SC & 0x80)) PulsePositionInput::list[5]->isr(); if ((maskin & 0x40) && (FTM0_C6SC & 0x80)) PulsePositionInput::list[6]->isr(); if ((maskin & 0x80) && (FTM0_C7SC & 0x80)) PulsePositionInput::list[7]->isr(); uint8_t maskout = PulsePositionOutput::channelmask; if ((maskout & 0x01) && (FTM0_C0SC & 0x80)) PulsePositionOutput::list[0]->isr(); if ((maskout & 0x02) && (FTM0_C1SC & 0x80)) PulsePositionOutput::list[1]->isr(); if ((maskout & 0x04) && (FTM0_C2SC & 0x80)) PulsePositionOutput::list[2]->isr(); if ((maskout & 0x08) && (FTM0_C3SC & 0x80)) PulsePositionOutput::list[3]->isr(); if ((maskout & 0x10) && (FTM0_C4SC & 0x80)) PulsePositionOutput::list[4]->isr(); if ((maskout & 0x20) && (FTM0_C5SC & 0x80)) PulsePositionOutput::list[5]->isr(); if ((maskout & 0x40) && (FTM0_C6SC & 0x80)) PulsePositionOutput::list[6]->isr(); if ((maskout & 0x80) && (FTM0_C7SC & 0x80)) PulsePositionOutput::list[7]->isr(); PulsePositionInput::overflow_inc = false; }
void flextimer_init(void){ //INits Flextimer // We configure A2 und A3 as flextimer outputs for FTM0_CH0 and FTM0_CH1 // Enable clock to TIMER FTM0 SIM->SCGC6 |= SIM_SCGC6_FTM0_MASK; // Enable clock to port pins used by FTM0, we use port C SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; // Select FTM0_CH0 and FTM0_CH1 pins SIM->SOPT8 |= (SIM_SOPT8_FTM0OCH0SRC_MASK|SIM_SOPT8_FTM0OCH1SRC_MASK); //Set pin to right output PORTC->PCR[1] = PORT_PCR_MUX(4); //FTM0_CH0 PORTC->PCR[2] = PORT_PCR_MUX(4); //FTM0_CH1 FTM0->MODE=FTM_MODE_FTMEN_MASK | FTM_MODE_WPDIS_MASK; // Set to freerunning mode FTM0->CNT=0; FTM0->CNTIN=0; FTM0->MOD=256; FTM0->SC=FTM_SC_CLKS(0b01); //We use the system clock FTM0->CONTROLS[0].CnSC=FTM_CnSC_MS(0b10)|FTM_CnSC_ELS(0b10); FTM0->CONTROLS[0].CnV=100; FTM0->CONTROLS[1].CnSC=FTM_CnSC_MS(0b10)|FTM_CnSC_ELS(0b10); FTM0->CONTROLS[0].CnV=200; }
int cam_init() { // // disable interrupt // disable_irq(64); // // FTM2 configuration // // enable the clock for FTM2 SIM_SCGC3 |= SIM_SCGC3_FTM2_MASK; // enable write-able mode for FTM2 FTM2_MODE |= FTM_MODE_WPDIS_MASK; // turn off Status and Control FTM2_SC = 0; // makes the initial counter value for FTM2 FTM2_CNTIN = 0; // writing any value to CNT loads the counter with CNTIN for FTM 2 FTM2_CNT = 0; // CHIE enables interrupts as an ISR (used by ADC function after // clock pulses) FTM2_C0SC = FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK | FTM_CnSC_CHIE_MASK; // when counter == mod, the counter resets, set MOD value FTM2_MOD = CAM_MOD_INIT; FTM2_C0V = 0; // set clock prescaler for FTM2 FTM2_SC |= FTM_SC_PS(2); // set main clock as BUS clock (50 MHz) for FTM2 FTM2_SC |= FTM_SC_CLKS(1); // // GPIO configuration for top level pins // // enable the clock for Port A SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK; // set Port A Pin 14 for GPIO functionality (A22) PORTA_PCR14 = (0|PORT_PCR_MUX(1)); // set Port A Pin 14 for output to drive the SI pulse GPIOA_PDDR |= GPIO_PDDR_PDD(GPIO_PIN(14)); // set Port A Pin 10 for GPIO functionality (B66) PORTA_PCR10 = (0|PORT_PCR_MUX(3)); // set Port A Pin 10 for output to drive the camera clock GPIOA_PDDR |= GPIO_PDDR_PDD(GPIO_PIN(10)); return CAM_RET_SUCCESS; }
void pwm_start(pwm_t dev) { switch (dev) { #if PWM_0_EN case PWM_0: PWM_0_DEV->SC |= FTM_SC_CLKS(1); break; #endif #if PWM_1_EN case PWM_1: PWM_1_DEV->SC |= FTM_SC_CLKS(1); break; #endif } }
bool PulsePositionOutput::begin(uint8_t txPin, uint8_t framePin) { uint32_t channel; volatile void *reg; if (FTM0_MOD != 0xFFFF || FTM0_SC != (FTM_SC_CLKS(1) | FTM_SC_PS(0))) { FTM0_SC = 0; FTM0_CNT = 0; FTM0_MOD = 0xFFFF; FTM0_SC = FTM_SC_CLKS(1) | FTM_SC_PS(0); FTM0_MODE = 0; } switch (txPin) { case 5: channel = 7; reg = &FTM0_C7SC; break; case 6: channel = 4; reg = &FTM0_C4SC; break; case 9: channel = 2; reg = &FTM0_C2SC; break; case 10: channel = 3; reg = &FTM0_C3SC; break; case 20: channel = 5; reg = &FTM0_C5SC; break; case 21: channel = 6; reg = &FTM0_C6SC; break; case 22: channel = 0; reg = &FTM0_C0SC; break; case 23: channel = 1; reg = &FTM0_C1SC; break; default: return false; } if (framePin < NUM_DIGITAL_PINS) { framePinReg = portOutputRegister(framePin); pinMode(framePin, OUTPUT); *framePinReg = 1; } else { framePinReg = NULL; } state = 0; current_channel = 0; total_channels = 0; ftm = (struct ftm_channel_struct *)reg; ftm->cv = 200; ftm->csc = cscSet; // set on compare match & interrupt list[channel] = this; channelmask |= (1<<channel); *portConfigRegister(txPin) = PORT_PCR_MUX(4) | PORT_PCR_DSE | PORT_PCR_SRE; NVIC_SET_PRIORITY(IRQ_FTM0, 32); NVIC_ENABLE_IRQ(IRQ_FTM0); return true; }
void FTM0_Init (void) { SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; //Gives clock to FTM0 FTM0_MOD = FTM0_MOD_VALUE; FTM0_SC = (FTM_SC_CLKS(1) | FTM_SC_TOIE_MASK | FTM_SC_PS(6)); //Runs FTM System Clock Prescaler = 64 NVICICPR1|=(1<<30); //Clear any pending interrupts on FTM0 NVICISER1|=(1<<30); //Enable interrupts from FTM0 module }
void FTM1_Init(void) { SIM_SCGC6 |= SIM_SCGC6_FTM1_MASK; //Gives clock to FTM1 FTM1_MOD = FTM1_MOD_VALUE; FTM1_SC = (FTM_SC_CLKS(1) | FTM_SC_TOIE_MASK | FTM_SC_PS(5)); //Runs FTM System Clock Prescaler = 32 NVICICPR1|=(UINT32)(1<<31); //Clear any pending interrupts on FTM1 NVICISER1|=(UINT32)(1<<31); //Enable interrupts from FTM1 module }
void HAL_FTM_Base_Start_IT(FTM_HandleTypeDef *hftm) { FTM_TypeDef *FTMx = hftm->Instance; assert_param(IS_FTM_INSTANCE(FTMx)); hftm->State = HAL_FTM_STATE_BUSY; FTMx->CNT = 0; FTMx->SC |= FTM_SC_CLKS(1) | FTM_SC_TOIE; hftm->State = HAL_FTM_STATE_READY; }
/* ===================================================================*/ LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ TU1_TDeviceData *DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* SIM_SCGC6: FTM0=1 */ SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; /* FTM0_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */ FTM0_MODE = (FTM_MODE_FAULTM(0x00) | FTM_MODE_WPDIS_MASK); /* Set up mode register */ /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */ FTM0_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00)); /* Clear status and control register */ /* FTM0_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */ FTM0_CNTIN = FTM_CNTIN_INIT(0x00); /* Clear counter initial register */ /* FTM0_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ FTM0_CNT = FTM_CNT_COUNT(0x00); /* Reset counter register */ /* FTM0_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C0SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C1SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C2SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C2SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C3SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C4SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C4SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C5SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C5SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C6SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C6SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C7SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C7SC = 0x00U; /* Clear channel status and control register */ /* FTM0_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0xFFFF */ FTM0_MOD = FTM_MOD_MOD(0xFFFF); /* Set up modulo register */ /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=1,PS=1 */ FTM0_SC = (FTM_SC_CLKS(0x01) | FTM_SC_PS(0x01)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
void ftm_enable(void) { // Initialize FTM2 for output compare FTM2_MODE |= FTM_MODE_FTMEN_MASK; // Enable FTM2, non-TPM-compatible registers. FTM2_CNT = 0x00000000; // Clear counter. FTM2_MOD = FTM_MOD_MOD(0xFFFF); // FTM0 Modulo set for counter overflow after 1 system clock cycles FTM2_C0SC = FTM_CnSC_MSA_MASK | FTM_CnSC_ELSA_MASK; // FTM2_CH0 set for Output Compare mode, toggle output on match FTM2_C0V = FTM_CnV_VAL(0xFFFF); // FTM2_CH0 output compare action on counter value of 0. FTM2_OUTINIT |= (FTM_OUTINIT_CH0OI_MASK); // Static output level high for FTM2_CH0 when OC toggle not desired. FTM2_SC = FTM_SC_CLKS(1) | FTM_SC_PS(6); // FTM0 in up-counter mode, TOF interrupt disabled, system clock source, div-by-128 prescaler. #if (defined(TWR_K40X256)) FTM2_SC |= FTM_SC_TOIE_MASK; // enable TOF interrupt if K40 tower board #endif }
/* * LPLD_FTM_IC_Init * FTM模块输入捕获模式初始化,内部调用 */ static uint8 LPLD_FTM_IC_Init(FTM_InitTypeDef ftm_init_structure) { uint8 i; uint8 ps = ftm_init_structure.FTM_ClkDiv; FTM_ISR_CALLBACK isr_func = ftm_init_structure.FTM_Isr; FTM_MemMapPtr ftmx = ftm_init_structure.FTM_Ftmx; //参数检查 //ASSERT( ps <= 7); //时钟分频系数 if (ps > 7) return 0; ftmx->CONF=FTM_CONF_BDMMODE(0x3); ftmx->SC = 0; ftmx->CNT = 0; ftmx->CNTIN = 0; ftmx->MOD = 0; ftmx->QDCTRL = (~FTM_QDCTRL_QUADEN_MASK); //关闭正交解码 ftmx->FILTER = 0x00; //关过虑器 // 配置FTM控制寄存器 // 将FTM Counter配置成Free Counter // 禁用中断, 加计数模式, 时钟源:System clock(Bus Clk), 分频系数:PS // 假设SysClk = 50MHz, SC_PS=3, FTM Clk = 50MHz/2^3 = 6.25MHz ftmx->SC |= FTM_SC_CLKS(1)|FTM_SC_PS(ps); //ftmx->SC |= FTM_SC_TOIE_MASK; //使能计数溢出中断 ftmx->SC &= (~FTM_SC_CPWMS_MASK); //FTM加计数 //设置中断函数入口地址并开启中断 if(isr_func!=NULL) { if(ftmx == FTM0) i=0; else if(ftmx == FTM1) i=1; else if(ftmx == FTM2) i=2; else if (ftmx == FTM3) i = 3; else return 0; FTM_ISR[i] = isr_func; } return 1; }
/*********************************************************************** * PURPOSE: Initialize FTM2 * * INPUTS: * RETURNS: ***********************************************************************/ void init_FTM2(){ // Enable clock SIM_SCGC6 |= SIM_SCGC6_FTM2_MASK; // Disable Write Protection FTM2_MODE |= FTM_MODE_WPDIS_MASK; // Set output to '1' on init FTM2_OUTINIT |= FTM_OUTINIT_CH0OI_MASK; // Initialize the CNT to 0 before writing to MOD FTM2_CNT = 0x00; // Set the Counter Initial Value to 0 FTM2_CNTIN = 0x00; // Set the period (~10us) //FTM2_MOD = FTM_MOD_MOD_MASK & ((DEFAULT_SYSTEM_CLOCK /100000) << FTM_MOD_MOD_SHIFT); FTM2_MOD = MOD_AMOUNT; // 50% duty //FTM2_C0V = FTM_CnV_VAL_MASK & (((DEFAULT_SYSTEM_CLOCK /100000) << 1) << FTM_CnV_VAL_SHIFT); FTM2_C0V = 50; // Set edge-aligned mode FTM2_C0SC |= FTM_CnSC_MSB_MASK; // Enable High-true pulses // ELSB = 1, ELSA = 0 FTM2_C0SC |= FTM_CnSC_ELSB_MASK; FTM2_C0SC &= ~FTM_CnSC_ELSA_MASK; //�Enable�hardware�trigger�from�FTM2 FTM2_EXTTRIG |= FTM_EXTTRIG_INITTRIGEN_MASK; // Don't enable interrupts yet (disable) FTM2_SC &= ~FTM_SC_TOIE_MASK; // No prescalar, system clock FTM2_SC = FTM_SC_CLKS(0x01) | FTM_SC_PS(0); // Set up interrupt NVIC_EnableIRQ(FTM2_IRQn); return; }
void FTM_init (FTM_MemMapPtr base) { // Habilito el pin PTC1 como salida del canal 0 PORTC_PCR1 = (PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x04)); PORTB_PCR18 = (PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03)); // Habilito la llave general de las interrupciones //NVICISER1 |= NVIC_ISER_SETENA(0x0400); // Habilito el clock gating SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; SIM_SCGC6 |= SIM_SCGC6_FTM2_MASK; // Deshabilito la proteccion de escritura FTM_MODE_REG(base) = FTM_MODE_WPDIS_MASK; // Apago los flag de interrupciones FTM_STATUS_REG(base) = (FTM0_STATUS & 0x00); // Deshabilito los clocks y borro la configuracion FTM_SC_REG(base) = 0x00; // Configuro el canal 0 como nada FTM_CnSC_REG(base,0) = 0x00; // Configuro la salida inicial en alto (los LEDs son activo-bajo) FTM_MODE_REG(base) = FTM_MODE_INIT_MASK; // Configuro el PWM a duty 25% y reinicio el contador FTM_CnV_REG(base,0) = 0x0000; FTM_MOD_REG(base) = 0x0000; FTM_CNTIN_REG(base) = 0x0000; FTM_CNT_REG(base) = 0x0000; FTM_PWMLOAD_REG(base) = (FTM_PWMLOAD_LDOK_MASK | FTM_PWMLOAD_CH0SEL_MASK); // Habilito las interrupciones y los clocks, y configuro el prescaler FTM_SC_REG(base) = (FTM_SC_TOIE_MASK | FTM_SC_CLKS(0x01) | FTM_SC_PS(0x0F)); // Habilito los contadores del modulo FTM_CONF_REG(base) = FTM_CONF_BDMMODE(0x03); }
//Timer control routines void baud_timer_init() { #ifdef ___MAPLE timer4.pause(); // Pause the timer while configuring it timer4.setMode(TIMER_CH1, TIMER_OUTPUT_COMPARE); // Set up interrupt on channel 1 timer4.setCount(0); // Reset count to zero timer4.setPrescaleFactor(72); // Timer counts at 72MHz/72 = 1MHz 1 count = 1uS timer4.setOverflow(0xFFFF); // reset occurs at 15.259Hz timer4.refresh(); // Refresh the timer's count, prescale, and overflow timer4.resume(); // Start the timer counting #endif #ifdef ___ARDUINO cli(); // stop interrupts during configuration TCCR1A = 0; // Clear TCCR1A register TCCR1B = 0; // Clear TCCR1B register TCNT1 = 0; // Initialize counter value OCR1A = 0xFFFF; // Set compare match register to maximum value TCCR1B |= (1 << WGM12); // CTC mode // We want 1uS ticks, for 16MHz CPU, we use prescaler of 16 // as 1MHz = 1uS period, but Arduino is lame and only has // 3 bit multiplier, we can have 8 (overflows too quickly) // or 64, which operates at 1/4 the desired resolution TCCR1B |= (1 << CS11); // Configure for 8 prescaler TIMSK1 |= (1 << OCIE1A); // enable compare interrupt sei(); // re-enable interrupts #endif #ifdef ___TEENSY FTM0_MODE |= FTM_MODE_WPDIS; FTM0_CNT = 0; FTM0_CNTIN = 0; FTM0_SC |= FTM_SC_PS(7); FTM0_SC |= FTM_SC_CLKS(1); FTM0_MOD = 0xFFFF; FTM0_MODE |= FTM_MODE_FTMEN; /* PIT_LDVAL1 = 0x500000; PIT_TCTRL1 = TIE; PIT_TCTRL1 |= TEN; PIT_TFLG1 |= 1; */ #endif }
/*********************************************************************** * PURPOSE: Initialize the FlexTimer for DC Motors * * INPUTS: * RETURNS: ***********************************************************************/ void InitDCMotors(void) { // 12.2.13 Enable the Clock to the FTM0 Module SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; // Enable clock on PORT A so it can output SIM_SCGC5 |= SIM_SCGC5_PORTA_MASK | SIM_SCGC5_PORTB_MASK | SIM_SCGC5_PORTC_MASK; // 11.4.1 Route the output of TPM channel 0 to the pins // Use drive strength enable flag to high drive strength //These port/pins may need to be updated for the K64 <Yes, they do. Here are two that work.> PORTC_PCR3 = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK; //Ch2 PORTC_PCR4 = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;//Ch3 // 39.3.10 Disable Write Protection FTM0_MODE |= FTM_MODE_WPDIS_MASK; // 39.3.4 FTM Counter Value // Initialize the CNT to 0 before writing to MOD FTM0_CNT = 0; // 39.3.8 Set the Counter Initial Value to 0 FTM0_CNTIN = 0; // 39.3.5 Set the Modulo resister FTM0_MOD = (SYSTEM_CLOCK/MOTOR_FREQUNECY); // 39.3.6 Set the Status and Control of both channels // Used to configure mode, edge and level selection // See Table 39-67, Edge-aligned PWM, High-true pulses (clear out on match) FTM0_C3SC |= FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK; FTM0_C3SC &= ~FTM_CnSC_ELSA_MASK; // See Table 39-67, Edge-aligned PWM, Low-true pulses (clear out on match) FTM0_C2SC |= FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK; FTM0_C2SC &= ~FTM_CnSC_ELSA_MASK; // 39.3.3 FTM Setup // Set prescale value to 1 // Chose system clock source // Timer Overflow Interrupt Enable FTM0_SC = FTM_SC_PS(0) | FTM_SC_CLKS(1) | FTM_SC_TOIE_MASK; }
void pwmout_init(pwmout_t* obj, PinName pin) { // determine the channel PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM); if (pwm == (PWMName)NC) error("PwmOut pin mapping failed"); uint32_t clkdiv = 0; float clkval = SystemCoreClock / 1000000.0f; while (clkval > 1) { clkdiv++; clkval /= 2.0; if (clkdiv == 7) break; } pwm_clock = clkval; unsigned int port = (unsigned int)pin >> PORT_SHIFT; unsigned int ftm_n = (pwm >> TPM_SHIFT); unsigned int ch_n = (pwm & 0xFF); SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port); SIM->SCGC6 |= 1 << (SIM_SCGC6_FTM0_SHIFT + ftm_n); FTM_Type *ftm = (FTM_Type *)(FTM0_BASE + 0x1000 * ftm_n); ftm->CONF |= FTM_CONF_BDMMODE(3); ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(clkdiv); // (clock)MHz / clkdiv ~= (0.75)MHz ftm->CONTROLS[ch_n].CnSC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* No Interrupts; High True pulses on Edge Aligned PWM */ obj->CnV = &ftm->CONTROLS[ch_n].CnV; obj->MOD = &ftm->MOD; obj->CNT = &ftm->CNT; // default to 20ms: standard for servos, and fine for e.g. brightness control pwmout_period_ms(obj, 20); pwmout_write(obj, 0); // Wire pinout pinmap_pinout(pin, PinMap_PWM); }
/** * @brief pwm2模块相关寄存器配置 * * @param channel pwm2所选的通道 */ static void pwm_mod2_set(ID channel) { /*使能ftm0模块时钟*/ SIM_SCGC3 |= SIM_SCGC3_FTM2_MASK; /*选择时钟源,分频系数,以及计数器计数方式*/ FTM_SC_REG(FTM2_BASE_PTR) = FTM_SC_CLKS(FTM2_PWM_CLK) | FTM_SC_PS(FTM2_PWM_PRESCALE) | ((FTM2_PWM_MODE & 0x10)<<1); /*设置计数器计数初值*/ FTM_CNTIN_REG(FTM2_BASE_PTR) = CNTIN_VALUE; /*初始化计数器*/ FTM_CNT_REG(FTM2_BASE_PTR) = FTM2_INIT_VALUE; /*设置计数器最大模值*/ FTM_MOD_REG(FTM2_BASE_PTR) = FTM2_PWM_CYCLE; /*设置FTM模块的工作方式*/ FTM_CnSC_REG(FTM2_BASE_PTR,channel) = ((FTM2_PWM_MODE & 0x0f)<<2); /*设置初始化占空比*/ FTM_CnV_REG(FTM2_BASE_PTR,channel) = PWM_INIT_VALUE; }
/* ===================================================================*/ LDD_TDeviceData* TU2_Init(LDD_TUserData *UserDataPtr) { TU2_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID] == NULL) { /* Allocate device structure */ /* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU2_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU2_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* SIM_SCGC3: FTM3=1 */ SIM_SCGC3 |= SIM_SCGC3_FTM3_MASK; /* SIM_SCGC5: PORTD=1 */ SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK; /* FTM3_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */ FTM3_MODE = (FTM_MODE_FAULTM(0x00) | FTM_MODE_WPDIS_MASK); /* Set up mode register */ /* FTM3_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */ FTM3_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00)); /* Clear status and control register */ /* FTM3_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */ FTM3_CNTIN = FTM_CNTIN_INIT(0x00); /* Clear counter initial register */ /* FTM3_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ FTM3_CNT = FTM_CNT_COUNT(0x00); /* Reset counter register */ /* FTM3_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM3_C0SC = 0x00U; /* Clear channel status and control register */ /* FTM3_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM3_C1SC = 0x00U; /* Clear channel status and control register */ /* FTM3_C2SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM3_C2SC = 0x00U; /* Clear channel status and control register */ /* FTM3_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM3_C3SC = 0x00U; /* Clear channel status and control register */ /* FTM3_C4SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM3_C4SC = 0x00U; /* Clear channel status and control register */ /* FTM3_C5SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM3_C5SC = 0x00U; /* Clear channel status and control register */ /* FTM3_C6SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM3_C6SC = 0x00U; /* Clear channel status and control register */ /* FTM3_C7SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM3_C7SC = 0x00U; /* Clear channel status and control register */ /* FTM3_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0x493D */ FTM3_MOD = FTM_MOD_MOD(0x493D); /* Set up modulo register */ /* FTM3_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=0,??=0,DMA=0 */ FTM3_C0SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* Set up channel status and control register */ /* FTM3_C0V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0 */ FTM3_C0V = FTM_CnV_VAL(0x00); /* Set up channel value register */ /* FTM3_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=0,??=0,DMA=0 */ FTM3_C1SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* Set up channel status and control register */ /* FTM3_C1V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0 */ FTM3_C1V = FTM_CnV_VAL(0x00); /* Set up channel value register */ /* FTM3_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=0,??=0,DMA=0 */ FTM3_C3SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* Set up channel status and control register */ /* FTM3_C3V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0 */ FTM3_C3V = FTM_CnV_VAL(0x00); /* Set up channel value register */ /* FTM3_C2SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=0,??=0,DMA=0 */ FTM3_C2SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* Set up channel status and control register */ /* FTM3_C2V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0 */ FTM3_C2V = FTM_CnV_VAL(0x00); /* Set up channel value register */ /* FTM3_OUTINIT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CH7OI=0,CH6OI=0,CH5OI=0,CH4OI=0,CH3OI=1,CH2OI=1,CH1OI=1,CH0OI=1 */ FTM3_OUTINIT = FTM_OUTINIT_CH3OI_MASK | FTM_OUTINIT_CH2OI_MASK | FTM_OUTINIT_CH1OI_MASK | FTM_OUTINIT_CH0OI_MASK; /* Set up Initial State for Channel Output register */ /* FTM3_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=1,FTMEN=0 */ FTM3_MODE = (FTM_MODE_FAULTM(0x00) | FTM_MODE_WPDIS_MASK | FTM_MODE_INIT_MASK); /* Initialize the Output Channels */ /* PORTD_PCR0: ISF=0,MUX=4 */ PORTD_PCR0 = (uint32_t)((PORTD_PCR0 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTD_PCR1: ISF=0,MUX=4 */ PORTD_PCR1 = (uint32_t)((PORTD_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTD_PCR3: ISF=0,MUX=4 */ PORTD_PCR3 = (uint32_t)((PORTD_PCR3 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTD_PCR2: ISF=0,MUX=4 */ PORTD_PCR2 = (uint32_t)((PORTD_PCR2 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* FTM3_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=1,PS=6 */ FTM3_SC = (FTM_SC_CLKS(0x01) | FTM_SC_PS(0x06)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU2_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
/* ===================================================================*/ LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr) { TU1_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID] == NULL) { /* Allocate device structure */ /* {MQXLite RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU1_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* Interrupt vector(s) allocation */ /* {MQXLite RTOS Adapter} Save old and set new interrupt vector (function handler and ISR parameter) */ /* Note: Exception handler for interrupt is not saved, because it is not modified */ DeviceDataPrv->SavedISRSettings_TUInterrupt.isrData = _int_get_isr_data(LDD_ivIndex_INT_FTM0); DeviceDataPrv->SavedISRSettings_TUInterrupt.isrFunction = _int_install_isr(LDD_ivIndex_INT_FTM0, TU1_Interrupt, DeviceDataPrv); /* SIM_SCGC6: FTM0=1 */ SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; /* FTM0_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */ FTM0_MODE = (FTM_MODE_FAULTM(0x00) | FTM_MODE_WPDIS_MASK); /* Set up mode register */ /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */ FTM0_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00)); /* Clear status and control register */ /* FTM0_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */ FTM0_CNTIN = FTM_CNTIN_INIT(0x00); /* Clear counter initial register */ /* FTM0_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ FTM0_CNT = FTM_CNT_COUNT(0x00); /* Reset counter register */ /* FTM0_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C0SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C1SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C2SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C2SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C3SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C4SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C4SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C5SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C5SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C6SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C6SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C7SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C7SC = 0x00U; /* Clear channel status and control register */ /* FTM0_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0x927B */ FTM0_MOD = FTM_MOD_MOD(0x927B); /* Set up modulo register */ DeviceDataPrv->EnEvents = 0x0100U; /* Enable selected events */ /* NVICIP42: PRI42=0x70 */ NVICIP42 = NVIC_IP_PRI42(0x70); /* NVICISER1: SETENA|=0x0400 */ NVICISER1 |= NVIC_ISER_SETENA(0x0400); /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=1,CPWMS=0,CLKS=1,PS=4 */ FTM0_SC = (FTM_SC_TOIE_MASK | FTM_SC_CLKS(0x01) | FTM_SC_PS(0x04)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
void gpio_init(void) { // enable clock to ports SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTB_MASK; // configure pin as GPIO LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1); // led off - enable output LED_CONNECTED_GPIO->PDOR = 1UL << LED_CONNECTED_BIT; LED_CONNECTED_GPIO->PDDR = 1UL << LED_CONNECTED_BIT; // led on LED_CONNECTED_GPIO->PCOR |= 1UL << LED_CONNECTED_BIT; #if defined(INTERFACE_GEN_32KHZ) // we use PTD6 to generate 32kHz clk // ftm0_ch6 (alternate function 4) PORTD->PCR[CLK_32K_PIN] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK; // enable clk for ftm0 SIM->SCGC6 |= SIM_SCGC6_FTM0_MASK; // configure PWM to generate a 32kHz clock used // by the RTC module of the target. // Choose EDGE-Aligned PWM: selected when QUADEN=0, DECAPEN=0, COMBINE=0, CPWMS=0, and MSnB=1 (page 964) //disable write protection FTM0->MODE |= FTM_MODE_WPDIS_MASK; //FTMEN is bit 0, need to set to zero so DECAPEN can be set to 0 FTM0->MODE &= ~FTM_MODE_FTMEN_MASK; //QUADEN = 0; DECAPEN = 0; COMBINE = 0; CPWMS = 0; MSnB = 1 FTM0->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK; FTM0->COMBINE &= ~FTM_COMBINE_DECAPEN3_MASK; FTM0->COMBINE &= ~FTM_COMBINE_COMBINE3_MASK; FTM0->SC &= ~FTM_SC_CPWMS_MASK; FTM0->CONTROLS[6].CnSC |= FTM_CnSC_MSB_MASK; // ELSnB:ELSnA = 1:0 FTM0->CONTROLS[6].CnSC |= FTM_CnSC_ELSB_MASK; FTM0->CONTROLS[6].CnSC &= ~FTM_CnSC_ELSA_MASK; // set CNT, MOD (period) and CNTIN FTM0->CNT = 0x0; FTM0->MOD = FTM0_MOD_VALUE; FTM0->CNTIN = 0; // set pulsewidth to period/2 FTM0->CONTROLS[6].CnV = FTM0_MOD_VALUE/2; // select clock (system core clock) FTM0->SC = FTM_SC_PS(0) | FTM_SC_CLKS(1); //enable write protection FTM0->MODE &= ~FTM_MODE_WPDIS_MASK; #elif defined(INTERFACE_POWER_EN) // POWER_EN (PTD5) and VTRG_FAULT_B (PTD7) // VTRG_FAULT_B not currently implemented. Just power the target ;) // configure pin as GPIO PORTD->PCR[POWER_EN_PIN] = PORT_PCR_MUX(1); // force always on logic 1 PTD->PDOR |= 1UL << POWER_EN_PIN; PTD->PDDR |= 1UL << POWER_EN_PIN; #endif }
// Setup inline void LCD_setup() { // Register Scan CLI dictionary CLI_registerDictionary( lcdCLIDict, lcdCLIDictName ); // Initialize SPI SPI_setup(); // Setup Register Control Signal (A0) // Start in display register mode (1) GPIOC_PDDR |= (1<<7); PORTC_PCR7 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1); GPIOC_PSOR |= (1<<7); // Setup LCD Reset pin (RST) // 0 - Reset, 1 - Normal Operation // Start in normal mode (1) GPIOC_PDDR |= (1<<8); PORTC_PCR8 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1); GPIOC_PSOR |= (1<<8); // Run LCD intialization sequence LCD_initialize(); // Write default image to LCD for ( uint8_t page = 0; page < LCD_TOTAL_VISIBLE_PAGES; page++ ) LCD_writeDisplayReg( page, (uint8_t*)&STLcdDefaultImage[page * LCD_PAGE_LEN], LCD_PAGE_LEN ); // Setup Backlight SIM_SCGC6 |= SIM_SCGC6_FTM0; FTM0_CNT = 0; // Reset counter // PWM Period // 16-bit maximum FTM0_MOD = 0xFFFF; // Set FTM to PWM output - Edge Aligned, Low-true pulses FTM0_C0SC = 0x24; // MSnB:MSnA = 10, ELSnB:ELSnA = 01 FTM0_C1SC = 0x24; FTM0_C2SC = 0x24; // Base FTM clock selection (72 MHz system clock) // @ 0xFFFF period, 72 MHz / (0xFFFF * 2) = Actual period // Higher pre-scalar will use the most power (also look the best) // Pre-scalar calculations // 0 - 72 MHz -> 549 Hz // 1 - 36 MHz -> 275 Hz // 2 - 18 MHz -> 137 Hz // 3 - 9 MHz -> 69 Hz (Slightly visible flicker) // 4 - 4 500 kHz -> 34 Hz (Visible flickering) // 5 - 2 250 kHz -> 17 Hz // 6 - 1 125 kHz -> 9 Hz // 7 - 562 500 Hz -> 4 Hz // Using a higher pre-scalar without flicker is possible but FTM0_MOD will need to be reduced // Which will reduce the brightness range // System clock, /w prescalar setting FTM0_SC = FTM_SC_CLKS(1) | FTM_SC_PS( STLcdBacklightPrescalar_define ); // Red FTM0_C0V = STLcdBacklightRed_define; PORTC_PCR1 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(4); // Green FTM0_C1V = STLcdBacklightGreen_define; PORTC_PCR2 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(4); // Blue FTM0_C2V = STLcdBacklightBlue_define; PORTC_PCR3 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(4); }
/* ** =================================================================== ** Method : PWMMotor_Init (component TimerUnit_LDD) ** ** Description : ** Initializes the device. Allocates memory for the device data ** structure, allocates interrupt vectors and sets interrupt ** priority, sets pin routing, sets timing, etc. If the ** property <"Enable in init. code"> is set to "yes" value then ** the device is also enabled (see the description of the ** <Enable> method). In this case the <Enable> method is not ** necessary and needn't to be generated. This method can be ** called only once. Before the second call of Init the <Deinit> ** must be called first. ** Parameters : ** NAME - DESCRIPTION ** * UserDataPtr - Pointer to the user or ** RTOS specific data. This pointer will be ** passed as an event or callback parameter. ** Returns : ** --- - Pointer to the dynamically allocated ** private structure or NULL if there was an ** error. ** =================================================================== */ LDD_TDeviceData* PWMMotor_Init(LDD_TUserData *UserDataPtr) { /* Allocate device structure */ PWMMotor_TDeviceData *DeviceDataPrv; /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ /* Interrupt vector(s) allocation */ /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */ INT_FTM0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv; /* SIM_SCGC6: FTM0=1 */ SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; /* FTM0_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */ FTM0_MODE = FTM_MODE_WPDIS_MASK; /* Set up mode register */ /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */ FTM0_SC = 0x00U; /* Clear status and control register */ /* FTM0_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */ FTM0_CNTIN = 0x00U; /* Clear counter initial register */ /* FTM0_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ FTM0_CNT = 0x00U; /* Reset counter register */ /* FTM0_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C0SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C1SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C2SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C2SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C3SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C4SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C4SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C5SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C5SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C6SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C6SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C7SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C7SC = 0x00U; /* Clear channel status and control register */ /* FTM0_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0x1388 */ FTM0_MOD = FTM_MOD_MOD(0x1388); /* Set up modulo register */ /* FTM0_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */ FTM0_C0SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK | FTM_CnSC_ELSA_MASK); /* Set up channel status and control register */ /* FTM0_C0V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0x03E8 */ FTM0_C0V = FTM_CnV_VAL(0x03E8); /* Set up channel value register */ /* FTM0_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */ FTM0_C3SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK | FTM_CnSC_ELSA_MASK); /* Set up channel status and control register */ /* FTM0_C3V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0x03E8 */ FTM0_C3V = FTM_CnV_VAL(0x03E8); /* Set up channel value register */ /* PORTC_PCR1: ISF=0,MUX=4 */ PORTC_PCR1 = (uint32_t)((PORTC_PCR1 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTC_PCR4: ISF=0,MUX=4 */ PORTC_PCR4 = (uint32_t)((PORTC_PCR4 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); DeviceDataPrv->EnEvents = 0x0100U; /* Enable selected events */ /* NVICIP62: PRI62=0x80 */ NVICIP62 = NVIC_IP_PRI62(0x80); /* NVICISER1: SETENA|=0x40000000 */ NVICISER1 |= NVIC_ISER_SETENA(0x40000000); /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=1,CPWMS=0,CLKS=1,PS=0 */ FTM0_SC = (FTM_SC_TOIE_MASK | FTM_SC_CLKS(0x01)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_PWMMotor_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
/* * LPLD_FTM_PWM_Init * FTM模块PWM模式初始化,内部调用 */ static uint8 LPLD_FTM_PWM_Init(FTM_InitTypeDef ftm_init_structure) { uint32 bus_clk_hz; uint32 mod, mod2; uint8 ps; uint32 freq = ftm_init_structure.FTM_PwmFreq; uint32 dt_en = ftm_init_structure.FTM_PwmDeadtimeCfg; uint8 dt_div = ftm_init_structure.FTM_PwmDeadtimeDiv; uint8 dt_val = ftm_init_structure.FTM_PwmDeadtimeVal; FTM_MemMapPtr ftmx = ftm_init_structure.FTM_Ftmx; //参数检查 //ASSERT( freq ); //判断频率 //ASSERT( dt_val<=63 ); //判断死区插入值 if (dt_val > 63) return 0; bus_clk_hz = g_bus_clock; if(freq>bus_clk_hz) return 0; //这段代码写的比较有趣... if((mod=bus_clk_hz/(freq*128)) < 0xFFFFu) { ps = 7; mod2=mod; if((mod=bus_clk_hz/(freq*64)) < 0xFFFFu) { ps = 6; mod2=mod; if((mod=bus_clk_hz/(freq*32)) < 0xFFFFu) { ps = 5; mod2=mod; if((mod=bus_clk_hz/(freq*16)) < 0xFFFFu) { ps = 4; mod2=mod; if((mod=bus_clk_hz/(freq*8)) < 0xFFFFu) { ps = 3; mod2=mod; if((mod=bus_clk_hz/(freq*4)) < 0xFFFFu) { ps = 2; mod2=mod; if((mod=bus_clk_hz/(freq*2)) < 0xFFFFu) { ps = 1; mod2=mod; if((mod=bus_clk_hz/(freq*1)) < 0xFFFFu) { ps = 0; mod2=mod; } } } } } } } } else { return 0; } ftmx->SC = 0; // 设置PWM周期及占空比 // PWM周期 = (MOD-CNTIN+1)*FTM时钟周期 : // 配置FTM计数初始值 ftmx->CNT = 0; ftmx->CNTIN = 0; // 配置FTM计数MOD值 ftmx->MOD = mod2; ftmx->DEADTIME = FTM_DEADTIME_DTPS(dt_div) | FTM_DEADTIME_DTVAL(dt_val); ftmx->COMBINE = dt_en; //使能死区 // 配置FTM控制寄存器 // 禁用中断, 加计数模式, 时钟源:System clock(Bus Clk), 分频系数:8 // 假设SysClk = 50MHz, SC_PS=3, FTM Clk = 50MHz/2^3 = 6.25MHz ftmx->SC = FTM_SC_CLKS(1)|FTM_SC_PS(ps); return 1; }
/* ===================================================================*/ LDD_TDeviceData* TU1_Init(LDD_TUserData *UserDataPtr) { TU1_TDeviceData *DeviceDataPrv; if (PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID] == NULL) { /* Allocate device structure */ /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */ DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr = 1U; /* First initialization */ } else { /* Memory is already allocated */ DeviceDataPrv = (TU1_TDeviceDataPtr) PE_LDD_DeviceDataList[PE_LDD_COMPONENT_TU1_ID]; DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */ DeviceDataPrv->InitCntr++; /* Increment counter of initialization */ return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ } /* SIM_SCGC6: FTM0=1 */ SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK; /* FTM0_MODE: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,FAULTIE=0,FAULTM=0,CAPTEST=0,PWMSYNC=0,WPDIS=1,INIT=0,FTMEN=0 */ FTM0_MODE = (FTM_MODE_FAULTM(0x00) | FTM_MODE_WPDIS_MASK); /* Set up mode register */ /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=0,PS=0 */ FTM0_SC = (FTM_SC_CLKS(0x00) | FTM_SC_PS(0x00)); /* Clear status and control register */ /* FTM0_CNTIN: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,INIT=0 */ FTM0_CNTIN = FTM_CNTIN_INIT(0x00); /* Clear counter initial register */ /* FTM0_CNT: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COUNT=0 */ FTM0_CNT = FTM_CNT_COUNT(0x00); /* Reset counter register */ /* FTM0_C0SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C0SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C1SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C2SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C2SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C3SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C3SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C4SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C4SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C5SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C5SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C6SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C6SC = 0x00U; /* Clear channel status and control register */ /* FTM0_C7SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=0,MSA=0,ELSB=0,ELSA=0,??=0,DMA=0 */ FTM0_C7SC = 0x00U; /* Clear channel status and control register */ /* FTM0_MOD: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,MOD=0xF5C2 */ FTM0_MOD = FTM_MOD_MOD(0xF5C2); /* Set up modulo register */ /* FTM0_C4SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */ FTM0_C4SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK | FTM_CnSC_ELSA_MASK); /* Set up channel status and control register */ /* FTM0_C4V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0 */ FTM0_C4V = FTM_CnV_VAL(0x00); /* Set up channel value register */ /* FTM0_C1SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CHF=0,CHIE=0,MSB=1,MSA=0,ELSB=1,ELSA=1,??=0,DMA=0 */ FTM0_C1SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK | FTM_CnSC_ELSA_MASK); /* Set up channel status and control register */ /* FTM0_C1V: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,VAL=0 */ FTM0_C1V = FTM_CnV_VAL(0x00); /* Set up channel value register */ /* PORTD_PCR4: ISF=0,MUX=4 */ PORTD_PCR4 = (uint32_t)((PORTD_PCR4 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* PORTC_PCR2: ISF=0,MUX=4 */ PORTC_PCR2 = (uint32_t)((PORTC_PCR2 & (uint32_t)~(uint32_t)( PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x03) )) | (uint32_t)( PORT_PCR_MUX(0x04) )); /* FTM0_SC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TOF=0,TOIE=0,CPWMS=0,CLKS=1,PS=0 */ FTM0_SC = (FTM_SC_CLKS(0x01) | FTM_SC_PS(0x00)); /* Set up status and control register */ /* Registration of the device structure */ PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_TU1_ID,DeviceDataPrv); return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the device data structure */ }
void FTM2_CH1_PWM_Start(unsigned long u16DutyCycle) { FTM2_C1V = u16DutyCycle; FTM2_PWMCH1_PORT = PORT_PCR_MUX(3); //Enables PWM Output FTM2_SC |= FTM_SC_CLKS(1); //System clock on FTM2, start generating PWM }