byte H1BIT_Get(byte* entry, unsigned h) { /* entry address into the bitmap.*/ byte *bbmp = H1BIT_BYTE(entry, h); byte v = *bbmp; uint field_selector = GET_BIT_FIELD( h, H_GRAIN_BITS, H1B_FS_BITS ); uint res = GET_BIT_FIELD(v, field_selector, 1 ); return res; }
void H1BIT_Clear(byte* entry, unsigned h) { /* entry address into the bitmap.*/ byte *bbmp = H1BIT_BYTE(entry, h); byte v = *bbmp; uint field_selector = GET_BIT_FIELD( h, H_GRAIN_BITS, H1B_FS_BITS ); CLEAR_BIT_FIELD(v, field_selector, 1 ); *bbmp = v; }
/* Initiate a read and then poll FIFO for data, reading out as it appears. */ static void smi_read_fifo(struct bcm2835_smi_instance *inst, uint32_t *dest, int n_bytes) { if (read_smi_reg(inst, SMICS) & SMICS_RXD) { smi_dump_context_labelled(inst, "WARNING: read FIFO not empty at start of read call."); while (read_smi_reg(inst, SMICS)) ; } /* Dispatch the read: */ if (inst->settings.data_width == SMI_WIDTH_8BIT) smi_init_programmed_read(inst, n_bytes); else if (inst->settings.data_width == SMI_WIDTH_16BIT) smi_init_programmed_read(inst, n_bytes / 2); else { dev_err(inst->dev, "Unsupported data width for read."); return; } /* Poll FIFO to keep it empty */ while (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) if (read_smi_reg(inst, SMICS) & SMICS_RXD) *dest++ = read_smi_reg(inst, SMID); /* Ensure that the FIFO is emptied */ if (read_smi_reg(inst, SMICS) & SMICS_RXD) { int fifo_count; fifo_count = GET_BIT_FIELD(read_smi_reg(inst, SMIFD), SMIFD_FCNT); while (fifo_count--) *dest++ = read_smi_reg(inst, SMID); } if (!(read_smi_reg(inst, SMICS) & SMICS_DONE)) smi_dump_context_labelled(inst, "WARNING: transaction finished but done bit not set."); if (read_smi_reg(inst, SMICS) & SMICS_RXD) smi_dump_context_labelled(inst, "WARNING: read FIFO not empty at end of read call."); }
struct smi_settings *bcm2835_smi_get_settings_from_regs (struct bcm2835_smi_instance *inst) { struct smi_settings *settings = &inst->settings; int smidsr, smidsw, smidc; spin_lock(&inst->transaction_lock); smidsr = read_smi_reg(inst, SMIDSR0); smidsw = read_smi_reg(inst, SMIDSW0); smidc = read_smi_reg(inst, SMIDC); settings->pack_data = (read_smi_reg(inst, SMICS) & SMICS_PXLDAT) ? true : false; settings->data_width = GET_BIT_FIELD(smidsr, SMIDSR_RWIDTH); settings->read_setup_time = GET_BIT_FIELD(smidsr, SMIDSR_RSETUP); settings->read_hold_time = GET_BIT_FIELD(smidsr, SMIDSR_RHOLD); settings->read_pace_time = GET_BIT_FIELD(smidsr, SMIDSR_RPACE); settings->read_strobe_time = GET_BIT_FIELD(smidsr, SMIDSR_RSTROBE); settings->write_setup_time = GET_BIT_FIELD(smidsw, SMIDSW_WSETUP); settings->write_hold_time = GET_BIT_FIELD(smidsw, SMIDSW_WHOLD); settings->write_pace_time = GET_BIT_FIELD(smidsw, SMIDSW_WPACE); settings->write_strobe_time = GET_BIT_FIELD(smidsw, SMIDSW_WSTROBE); settings->dma_read_thresh = GET_BIT_FIELD(smidc, SMIDC_REQR); settings->dma_write_thresh = GET_BIT_FIELD(smidc, SMIDC_REQW); settings->dma_panic_read_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICR); settings->dma_panic_write_thresh = GET_BIT_FIELD(smidc, SMIDC_PANICW); settings->dma_passthrough_enable = (smidc & SMIDC_DMAP) ? true : false; settings->dma_enable = (smidc & SMIDC_DMAEN) ? true : false; spin_unlock(&inst->transaction_lock); return settings; }