/** * @brief Enables or disables the CEC Listen Mode. * @param NewState: new state of the Listen Mode. * This parameter can be: ENABLE or DISABLE. * @retval None */ void CEC_ListenModeCmd(FunctionalState NewState) { assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CFGR_LSTN_BB = (uint32_t)NewState; }
/** * @brief Enables or disables the WakeUp Pin functionality. * @param NewState: new state of the WakeUp Pin functionality. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_WakeUpPinCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState; }
/** * @brief Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. * @param CANx: where x can be 1 or 2 to to select the CAN peripheral. * @param CAN_InitStruct: pointer to a CAN_InitTypeDef structure that * contains the configuration information for the CAN peripheral. * @retval Constant indicates initialization succeed which will be * CANINITFAILED or CANINITOK. */ uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct) { uint8_t InitStatus = CANINITFAILED; uint32_t wait_ack = 0x00000000; /* Check the parameters */ assert_param(IS_CAN_ALL_PERIPH(CANx)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); /* exit from sleep mode */ CANx->MCR &= ~MCR_SLEEP; /* Request initialisation */ CANx->MCR |= MCR_INRQ ; /* Wait the acknowledge */ while (((CANx->MSR & MSR_INAK) != MSR_INAK) && (wait_ack != INAK_TimeOut)) { wait_ack++; } /* ...and check acknowledged */ if ((CANx->MSR & MSR_INAK) != MSR_INAK) { InitStatus = CANINITFAILED; } else { /* Set the time triggered communication mode */ if (CAN_InitStruct->CAN_TTCM == ENABLE) { CANx->MCR |= MCR_TTCM; } else { CANx->MCR &= ~MCR_TTCM; } /* Set the automatic bus-off management */ if (CAN_InitStruct->CAN_ABOM == ENABLE) { CANx->MCR |= MCR_ABOM; } else { CANx->MCR &= ~MCR_ABOM; } /* Set the automatic wake-up mode */ if (CAN_InitStruct->CAN_AWUM == ENABLE) { CANx->MCR |= MCR_AWUM; } else { CANx->MCR &= ~MCR_AWUM; } /* Set the no automatic retransmission */ if (CAN_InitStruct->CAN_NART == ENABLE) { CANx->MCR |= MCR_NART; } else { CANx->MCR &= ~MCR_NART; } /* Set the receive FIFO locked mode */ if (CAN_InitStruct->CAN_RFLM == ENABLE) { CANx->MCR |= MCR_RFLM; } else { CANx->MCR &= ~MCR_RFLM; } /* Set the transmit FIFO priority */ if (CAN_InitStruct->CAN_TXFP == ENABLE) { CANx->MCR |= MCR_TXFP; } else { CANx->MCR &= ~MCR_TXFP; } /* Set the bit timing register */ CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1); /* Request leave initialisation */ CANx->MCR &= ~MCR_INRQ; /* Wait the acknowledge */ wait_ack = 0x00; while (((CANx->MSR & MSR_INAK) == MSR_INAK) && (wait_ack != INAK_TimeOut)) { wait_ack++; } /* ...and check acknowledged */ if ((CANx->MSR & MSR_INAK) == MSR_INAK) { InitStatus = CANINITFAILED; } else { InitStatus = CANINITOK ; } } /* At this step, return the status of initialization */ return InitStatus; }
/** * @brief Enables the interrupt and starts ADC conversion of regular channels. * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc) { __IO uint32_t counter = 0; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); /* Process locked */ __HAL_LOCK(hadc); /* Check if an injected conversion is ongoing */ if(hadc->State == HAL_ADC_STATE_BUSY_INJ) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; } else { /* Change ADC state */ hadc->State = HAL_ADC_STATE_BUSY_REG; } /* Set ADC error code to none */ hadc->ErrorCode = HAL_ADC_ERROR_NONE; /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); while(counter != 0) { counter--; } } /* Enable the ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Enable the ADC end of conversion interrupt for regular group */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_EOC); /* Process unlocked */ __HAL_UNLOCK(hadc); /* Check if Multimode enabled */ if(HAL_IS_BIT_CLR(ADC->CCR, ADC_CCR_MULTI)) { /* if no external trigger present enable software conversion of regular channels */ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } else { /* if instance of handle correspond to ADC1 and no external trigger present enable software conversion of regular channels */ if((hadc->Instance == (ADC_TypeDef*)0x40012000) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } /* Return function status */ return HAL_OK; }
/** * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { __IO uint32_t counter = 0; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); /* Process locked */ __HAL_LOCK(hadc); /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); /* Enable ADC DMA mode */ hadc->Instance->CR2 |= ADC_CR2_DMA; /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError ; /* Enable the DMA Stream */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Change ADC state */ hadc->State = HAL_ADC_STATE_BUSY_REG; /* Process unlocked */ __HAL_UNLOCK(hadc); /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); /* Delay for ADC stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000)); while(counter != 0) { counter--; } } /* if no external trigger present enable software conversion of regular channels */ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= ADC_CR2_SWSTART; } /* Return function status */ return HAL_OK; }
/** * @brief Enables or disables the Tamper Pin activation. * @param NewState: new state of the Tamper Pin activation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void BKP_TamperPinCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_TPE_BB = (uint32_t)NewState; }
/** * @brief Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @retval HAL status */ HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan) { uint32_t status = CAN_INITSTATUS_FAILED; /* Default init status */ uint32_t tickstart = 0; /* Check CAN handle */ if(hcan == NULL) { return HAL_ERROR; } /* Check the parameters */ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM)); assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP)); assert_param(IS_CAN_MODE(hcan->Init.Mode)); assert_param(IS_CAN_SJW(hcan->Init.SJW)); assert_param(IS_CAN_BS1(hcan->Init.BS1)); assert_param(IS_CAN_BS2(hcan->Init.BS2)); assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler)); if(hcan->State == HAL_CAN_STATE_RESET) { /* Init the low level hardware */ HAL_CAN_MspInit(hcan); } /* Initialize the CAN state*/ hcan->State = HAL_CAN_STATE_BUSY; /* Exit from sleep mode */ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP); /* Request initialisation */ hcan->Instance->MCR |= CAN_MCR_INRQ ; /* Get timeout */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { if((HAL_GetTick()-tickstart) > INAK_TIMEOUT) { hcan->State= HAL_CAN_STATE_TIMEOUT; return HAL_TIMEOUT; } } /* Check acknowledge */ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { /* Set the time triggered communication mode */ if (hcan->Init.TTCM == ENABLE) { hcan->Instance->MCR |= CAN_MCR_TTCM; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM; } /* Set the automatic bus-off management */ if (hcan->Init.ABOM == ENABLE) { hcan->Instance->MCR |= CAN_MCR_ABOM; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM; } /* Set the automatic wake-up mode */ if (hcan->Init.AWUM == ENABLE) { hcan->Instance->MCR |= CAN_MCR_AWUM; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM; } /* Set the no automatic retransmission */ if (hcan->Init.NART == ENABLE) { hcan->Instance->MCR |= CAN_MCR_NART; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART; } /* Set the receive FIFO locked mode */ if (hcan->Init.RFLM == ENABLE) { hcan->Instance->MCR |= CAN_MCR_RFLM; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM; } /* Set the transmit FIFO priority */ if (hcan->Init.TXFP == ENABLE) { hcan->Instance->MCR |= CAN_MCR_TXFP; } else { hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP; } /* Set the bit timing register */ hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \ ((uint32_t)hcan->Init.SJW) | \ ((uint32_t)hcan->Init.BS1) | \ ((uint32_t)hcan->Init.BS2) | \ ((uint32_t)hcan->Init.Prescaler - 1); /* Request leave initialisation */ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ; /* Get timeout */ tickstart = HAL_GetTick(); /* Wait the acknowledge */ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) { if((HAL_GetTick()-tickstart) > INAK_TIMEOUT) { hcan->State= HAL_CAN_STATE_TIMEOUT; return HAL_TIMEOUT; } } /* Check acknowledged */ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) { status = CAN_INITSTATUS_SUCCESS; } } if(status == CAN_INITSTATUS_SUCCESS) { /* Set CAN error code to none */ hcan->ErrorCode = HAL_CAN_ERROR_NONE; /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_READY; /* Return function status */ return HAL_OK; } else { /* Initialize the CAN state */ hcan->State = HAL_CAN_STATE_ERROR; /* Return function status */ return HAL_ERROR; } }
/** * @brief Sends CE-ATA command (CMD61). * @param NewState: new state of CE-ATA command. This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_SendCEATACmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t*)CMD_ATACMD_BB = (uint32_t)NewState; }
/** * @brief Initializes the ARINC429R channelx peripheral according to the specified * sparameters in the ARINC429R_InitChannelStruct. * @param ARINC429R_CHANNELx: Slect the ARINC429R channel. * This parameter can be one of the following values: * @arg ARINC429R_CHANNEL1 * @arg ARINC429R_CHANNEL2 * @arg ARINC429R_CHANNEL3 * @arg ARINC429R_CHANNEL4 * @arg ARINC429R_CHANNEL5 * @arg ARINC429R_CHANNEL6 * @arg ARINC429R_CHANNEL7 * @arg ARINC429R_CHANNEL8 * @note Available only for MC MDR1986BE3 * @arg ARINC429R_CHANNEL9 * @arg ARINC429R_CHANNEL10 * @arg ARINC429R_CHANNEL11 * @arg ARINC429R_CHANNEL12 * @arg ARINC429R_CHANNEL13 * @arg ARINC429R_CHANNEL14 * @param ARINC429R_InitChannelStruct: pointer to a ARINC429R_InitChannelTypeDef structure * that contains the configuration information for the specified ARINC429R channel. * @retval None */ void ARINC429R_ChannelInit(uint32_t ARINC429R_CHANNELx, ARINC429R_InitChannelTypeDef * ARINC429R_InitChannelStruct) { MDR_ARINC429R_TypeDef * ARINC429Rx; uint32_t tmpreg_CONTROL1; uint32_t tmpreg_CONTROL2; uint32_t tmpreg_CONTROL3; uint32_t tmpreg_CONTROL4; uint32_t tmpreg_CONTROL5; uint32_t tmpreg_CONTROL6; uint32_t tmpreg_CONTROL7; /* Check the parameters */ assert_param(IS_ARINC429R_CHANNEL(ARINC429R_CHANNELx)); assert_param(IS_ARINC429R_CLK(ARINC429R_InitChannelStruct->ARINC429R_CLK)); assert_param(IS_FUNCTIONAL_STATE(ARINC429R_InitChannelStruct->ARINC429R_LB)); assert_param(IS_FUNCTIONAL_STATE(ARINC429R_InitChannelStruct->ARINC429R_SD)); assert_param(IS_BIT_STATUS(ARINC429R_InitChannelStruct->ARINC429R_SDI1)); assert_param(IS_BIT_STATUS(ARINC429R_InitChannelStruct->ARINC429R_SDI2)); assert_param(IS_ARINC429R_DIV(ARINC429R_InitChannelStruct->ARINC429R_DIV)); ARINC429Rx = MDR_ARINC429R; /* Set the speed of receiving data for specified ARINC429R_CHANNELx */ tmpreg_CONTROL1 = ARINC429Rx->CONTROL1; tmpreg_CONTROL1 &= ~(1<<(ARINC429R_CONTROL1_CLK1_Pos + ARINC429R_CHANNELx)); tmpreg_CONTROL1 |= ARINC429R_InitChannelStruct->ARINC429R_CLK << (ARINC429R_CONTROL1_CLK1_Pos + ARINC429R_CHANNELx); ARINC429Rx->CONTROL1 = tmpreg_CONTROL1; /* Set resolution tag detection and resolution decoding 9 and 10 data bits */ tmpreg_CONTROL2 = ARINC429Rx->CONTROL2; tmpreg_CONTROL2 &= ~( (1<<(ARINC429R_CONTROL2_LB_EN1_Pos + ARINC429R_CHANNELx))\ |(1<<(ARINC429R_CONTROL2_SD_EN1_Pos + ARINC429R_CHANNELx))); tmpreg_CONTROL2 |= ( (ARINC429R_InitChannelStruct->ARINC429R_LB << (ARINC429R_CONTROL2_LB_EN1_Pos + ARINC429R_CHANNELx))\ |(ARINC429R_InitChannelStruct->ARINC429R_SD << (ARINC429R_CONTROL2_SD_EN1_Pos + ARINC429R_CHANNELx))); ARINC429Rx->CONTROL2 = tmpreg_CONTROL2; /* Set bit comparison SDI1 and bit comparison SDI2 */ tmpreg_CONTROL3 = ARINC429Rx->CONTROL3; tmpreg_CONTROL3 &= ~( (1<<(ARINC429R_CONTROL3_SDI1_1_Pos +ARINC429R_CHANNELx))\ |(1<<(ARINC429R_CONTROL3_SDI2_1_Pos +ARINC429R_CHANNELx))); tmpreg_CONTROL3 |= ( (ARINC429R_InitChannelStruct->ARINC429R_SDI1 << (ARINC429R_CONTROL3_SDI1_1_Pos +ARINC429R_CHANNELx))\ |(ARINC429R_InitChannelStruct->ARINC429R_SDI2 << (ARINC429R_CONTROL3_SDI2_1_Pos +ARINC429R_CHANNELx))); ARINC429Rx->CONTROL3 = tmpreg_CONTROL3; /* Set core frequency divider for frequency reference channel ARINC429R_CHANNELx */ switch (ARINC429R_CHANNELx){ case ARINC429R_CHANNEL1: case ARINC429R_CHANNEL2: case ARINC429R_CHANNEL3: case ARINC429R_CHANNEL4: tmpreg_CONTROL4 = ARINC429Rx->CONTROL4; tmpreg_CONTROL4 &= ~(0xFF<<(ARINC429R_CHANNELx*8)); tmpreg_CONTROL4 |= ARINC429R_InitChannelStruct->ARINC429R_DIV << (ARINC429R_CHANNELx*8); ARINC429Rx->CONTROL4 = tmpreg_CONTROL4; break; case ARINC429R_CHANNEL5: case ARINC429R_CHANNEL6: case ARINC429R_CHANNEL7: case ARINC429R_CHANNEL8: tmpreg_CONTROL5 = ARINC429Rx->CONTROL5; tmpreg_CONTROL5 &= ~(0xFF<<((ARINC429R_CHANNELx - ARINC429R_CHANNEL5)*8)); tmpreg_CONTROL5 |= ARINC429R_InitChannelStruct->ARINC429R_DIV << ((ARINC429R_CHANNELx - ARINC429R_CHANNEL5)*8); ARINC429Rx->CONTROL5 = tmpreg_CONTROL5; break; #if defined (USE_MDR1986VE3) case ARINC429R_CHANNEL9: case ARINC429R_CHANNEL10: case ARINC429R_CHANNEL11: case ARINC429R_CHANNEL12: tmpreg_CONTROL6 = ARINC429Rx->CONTROL6; tmpreg_CONTROL6 &= ~(0xFF<<((ARINC429R_CHANNELx - ARINC429R_CHANNEL9)*8)); tmpreg_CONTROL6 |= ARINC429R_InitChannelStruct->ARINC429R_DIV << ((ARINC429R_CHANNELx - ARINC429R_CHANNEL9)*8); ARINC429Rx->CONTROL6 = tmpreg_CONTROL6; break; case ARINC429R_CHANNEL13: case ARINC429R_CHANNEL14: tmpreg_CONTROL7 = ARINC429Rx->CONTROL7; tmpreg_CONTROL7 &= ~(0xFF<<((ARINC429R_CHANNELx - ARINC429R_CHANNEL13)*8)); tmpreg_CONTROL7 |= ARINC429R_InitChannelStruct->ARINC429R_DIV << ((ARINC429R_CHANNELx - ARINC429R_CHANNEL13)*8); ARINC429Rx->CONTROL7 = tmpreg_CONTROL7; break; #endif } }
/** * @brief Enables or disables the command completion signal. * @param NewState: new state of command completion signal. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_CommandCompletionCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t*)CMD_ENCMDCOMPL_BB = (uint32_t)NewState; }
/** * @brief Enables or disables the CE-ATA interrupt. * @param NewState: new state of CE-ATA interrupt. This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_CEATAITCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t*)CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1)); }
/** * @brief Enables or disables the SD I/O Mode Operation. * @param NewState: new state of SDIO specific operation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_SetSDIOOperation(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t*)DCTRL_SDIOEN_BB = (uint32_t)NewState; }
/** * @brief Stops the SD I/O Read Wait operation. * @param NewState: new state of the Stop SDIO Read Wait operation. * This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_StopSDIOReadWait(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t*)DCTRL_RWSTOP_BB = (uint32_t)NewState; }
/** * @brief Enables or disables the SDIO Clock. * @param NewState: new state of the SDIO Clock. This parameter can be: ENABLE or DISABLE. * @retval None */ void SDIO_ClockCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t*)CLKCR_CLKEN_BB = (uint32_t)NewState; }
/** * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral * * @note Caution: This function must be used only with the ADC master. * * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { __IO uint32_t counter = 0U; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); /* Process locked */ __HAL_LOCK(hadc); /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ counter = (ADC_STAB_DELAY_US * (SystemCoreClock / 1000000U)); while(counter != 0U) { counter--; } } /* Start conversion if ADC is effectively enabled */ if(HAL_IS_BIT_SET(hadc->Instance->CR2, ADC_CR2_ADON)) { /* Set ADC state */ /* - Clear state bitfield related to regular group conversion results */ /* - Set state bitfield related to regular group operation */ ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_READY | HAL_ADC_STATE_REG_EOC | HAL_ADC_STATE_REG_OVR, HAL_ADC_STATE_REG_BUSY); /* If conversions on group regular are also triggering group injected, */ /* update ADC state. */ if (READ_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO) != RESET) { ADC_STATE_CLR_SET(hadc->State, HAL_ADC_STATE_INJ_EOC, HAL_ADC_STATE_INJ_BUSY); } /* State machine update: Check if an injected conversion is ongoing */ if (HAL_IS_BIT_SET(hadc->State, HAL_ADC_STATE_INJ_BUSY)) { /* Reset ADC error code fields related to conversions on group regular */ CLEAR_BIT(hadc->ErrorCode, (HAL_ADC_ERROR_OVR | HAL_ADC_ERROR_DMA)); } else { /* Reset ADC all error code fields */ ADC_CLEAR_ERRORCODE(hadc); } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); if (hadc->Init.DMAContinuousRequests != DISABLE) { /* Enable the selected ADC DMA request after last transfer */ ADC->CCR |= ADC_CCR_DDS; } else { /* Disable the selected ADC EOC rising on each regular channel conversion */ ADC->CCR &= ~ADC_CCR_DDS; } /* Enable the DMA Stream */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length); /* if no external trigger present enable software conversion of regular channels */ if((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } } /* Return function status */ return HAL_OK; }
/** * @brief Initializes the ETHERNETx peripheral according to the specified * parameters in the ETH_InitStruct. * @param ETHERNETx: Slect the ETHERNET peripheral. * This parameter can be one of the following values: * MMDR_ETHERNET1, MDR_ETHERNET2 for MDR1986VE3 and * MDR_ETHERNET1 for MDR1986VE1T. * @param ETH_InitStruct: pointer to a ETH_InitTypeDef structure that contains * the configuration information for the specified ETHERNET peripheral. * @retval None * */ void ETH_Init(MDR_ETHERNET_TypeDef * ETHERNETx, ETH_InitTypeDef * ETH_InitStruct) { uint32_t tmpreg_PHY_Control; uint32_t tmpreg_X_CFG; uint32_t tmpreg_R_CFG; uint16_t tmpreg_G_CFGh; uint16_t tmpreg_G_CFGl; /* Check the parameters */ assert_param(IS_ETH_ALL_PERIPH(ETHERNETx)); assert_param(IS_ETH_DELIMITER(ETH_InitStruct->ETH_Dilimiter)); assert_param(IS_ETH_PHY_ADDRESS(ETH_InitStruct->ETH_PHY_Address)); assert_param(IS_ETH_PHY_MODE(ETH_InitStruct->ETH_PHY_Mode)); assert_param(IS_ETH_DBG_MODE(ETH_InitStruct->ETH_DBG_Mode)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_DBG_XF)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_DBG_RF)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Loopback_Mode)); assert_param(IS_BIT_STATUS(ETH_InitStruct->ETH_Receiver_RST)); assert_param(IS_BIT_STATUS(ETH_InitStruct->ETH_Transmitter_RST)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Register_CLR)); assert_param(IS_ETH_BUFFER_MODE(ETH_InitStruct->ETH_Buffer_Mode)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Extension_Mode)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_HalfDuplex_Mode)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_DTRM)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Pause)); assert_param(IS_ETH_COL_WND(ETH_InitStruct->ETH_ColWnd)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Transmitter_State)); assert_param(IS_ETH_TRANSMITTER_BE(ETH_InitStruct->ETH_Transmitter_BE)); assert_param(IS_ETH_TRANSMITTER_BITS_ORDER(ETH_InitStruct->ETH_Transmitter_Bits_Order)); assert_param(IS_ETH_TRANSMITTER_EVENT_MODE(ETH_InitStruct->ETH_Transmitter_Event_Mode)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Automatic_Pad_Strip)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Automatic_Preamble)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Automatic_CRC_Strip)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Automatic_IPG)); assert_param(IS_ETH_RETRY_COUNTER(ETH_InitStruct->ETH_Retry_Counter)); assert_param(IS_ETH_RECEIVER_BE(ETH_InitStruct->ETH_Receiver_BE)); assert_param(IS_ETH_RECEIVER_BITS_ORDER(ETH_InitStruct->ETH_Receiver_Bits_Order)); assert_param(IS_ETH_RECEIVER_EVENT_MODE(ETH_InitStruct->ETH_Receiver_Event_Mode)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Receive_All_Packets)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Short_Frames_Reception)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Long_Frames_Reception)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Broadcast_Frames_Reception)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Error_CRC_Frames_Reception)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Control_Frames_Reception)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Unicast_Frames_Reception)); assert_param(IS_FUNCTIONAL_STATE(ETH_InitStruct->ETH_Source_Addr_HASH_Filter)); /* Set the buffer size of transmitter and receiver */ ETHERNETx->ETH_Dilimiter = ETH_InitStruct->ETH_Dilimiter; /* Config the PHY control register */ tmpreg_PHY_Control = (ETH_InitStruct->ETH_PHY_Address << ETH_PHY_CONTROL_PHYADD_Pos) | (ETH_InitStruct->ETH_PHY_Mode) | (ETH_InitStruct->ETH_PHY_Interface); ETHERNETx->PHY_Control |= tmpreg_PHY_Control; /* Config the G_CFGh register */ tmpreg_G_CFGh = ETH_InitStruct->ETH_DBG_Mode | (ETH_InitStruct->ETH_DBG_XF << ETH_G_CFGh_DBG_XF_EN_Pos) | (ETH_InitStruct->ETH_DBG_RF << ETH_G_CFGh_DBG_RF_EN_Pos) | (ETH_InitStruct->ETH_Loopback_Mode << ETH_G_CFGh_DLB_Pos ) | (ETH_InitStruct->ETH_Receiver_RST << ETH_G_CFGh_RRST_Pos) | (ETH_InitStruct->ETH_Transmitter_RST << ETH_G_CFGh_XRST_Pos); /* Write to ETH_G_CFGh */ ETHERNETx->ETH_G_CFGh = tmpreg_G_CFGh; /* Config the G_CFGl register */ tmpreg_G_CFGl = (ETH_InitStruct->ETH_Register_CLR << ETH_G_CFGl_RCLR_EN_Pos) | (ETH_InitStruct->ETH_Buffer_Mode) | (ETH_InitStruct->ETH_Extension_Mode << ETH_G_CFGl_EXT_EN_Pos) | (ETH_InitStruct->ETH_HalfDuplex_Mode << ETH_G_CFGl_HD_EN_Pos) | (ETH_InitStruct->ETH_DTRM << ETH_G_CFGl_DTRM_EN_Pos) | (ETH_InitStruct->ETH_Pause << ETH_G_CFGl_PAUSE_EN_Pos) | (ETH_InitStruct->ETH_ColWnd); /* Write to G_CFGl */ ETHERNETx->ETH_G_CFGl = tmpreg_G_CFGl; /* Config the X_CFG register */ tmpreg_X_CFG = (ETH_InitStruct->ETH_Transmitter_State << ETH_X_CFG_EN_Pos) | (ETH_InitStruct->ETH_Transmitter_BE) | (ETH_InitStruct->ETH_Transmitter_Bits_Order) | (ETH_InitStruct->ETH_Transmitter_Event_Mode) | (ETH_InitStruct->ETH_Automatic_Pad_Strip << ETH_X_CFG_PAD_EN_Pos) | (ETH_InitStruct->ETH_Automatic_Preamble << ETH_X_CFG_PRE_EN_Pos) | (ETH_InitStruct->ETH_Automatic_CRC_Strip << ETH_X_CFG_CRC_EN_Pos) | (ETH_InitStruct->ETH_Automatic_IPG << ETH_X_CFG_IPG_EN_Pos) | (ETH_InitStruct->ETH_Retry_Counter); /* Write to X_CFG */ ETHERNETx->ETH_X_CFG = tmpreg_X_CFG; /* Config the R_CFG register */ tmpreg_R_CFG = (ETH_InitStruct->ETH_Receiver_State << ETH_R_CFG_EN_Pos) | (ETH_InitStruct->ETH_Receiver_BE) | (ETH_InitStruct->ETH_Receiver_Bits_Order) | (ETH_InitStruct->ETH_Receiver_Event_Mode); /* Configure the received packets */ tmpreg_R_CFG |= (ETH_InitStruct->ETH_Short_Frames_Reception << ETH_R_CFG_LF_EN_Pos) | (ETH_InitStruct->ETH_Long_Frames_Reception << ETH_R_CFG_LF_EN_Pos) | (ETH_InitStruct->ETH_Broadcast_Frames_Reception << ETH_R_CFG_BCA_EN_Pos) | (ETH_InitStruct->ETH_Error_CRC_Frames_Reception << ETH_R_CFG_EF_EN_Pos) | (ETH_InitStruct->ETH_Control_Frames_Reception << ETH_R_CFG_CF_EN_Pos) | (ETH_InitStruct->ETH_Unicast_Frames_Reception << ETH_R_CFG_UCA_EN_Pos) | (ETH_InitStruct->ETH_Source_Addr_HASH_Filter << ETH_R_CFG_MCA_EN_Pos) | (ETH_InitStruct->ETH_Receive_All_Packets << ETH_R_CFG_AC_EN_Pos); /* Write to R_CFG */ ETHERNETx->ETH_R_CFG = tmpreg_R_CFG; /* Write the MAC address */ ETHERNETx->ETH_MAC_T = ETH_InitStruct->ETH_MAC_Address[0]; ETHERNETx->ETH_MAC_M = ETH_InitStruct->ETH_MAC_Address[1]; ETHERNETx->ETH_MAC_H = ETH_InitStruct->ETH_MAC_Address[2]; /* Set the hash table */ ETHERNETx->ETH_HASH0 = ETH_InitStruct->ETH_Hash_Table_Low & 0x0000FFFF; ETHERNETx->ETH_HASH1 = (ETH_InitStruct->ETH_Hash_Table_Low & 0xFFFF0000) >> 16; ETHERNETx->ETH_HASH2 = ETH_InitStruct->ETH_Hash_Table_High & 0x0000FFFF; ETHERNETx->ETH_HASH3 = (ETH_InitStruct->ETH_Hash_Table_High & 0xFFFF0000) >> 16; /* Set the pacet interval fo falf duplex mode. */ ETHERNETx->ETH_IPG = ETH_InitStruct->ETH_IPG; /* Set the prescaler increment values ​​BAG and JitterWnd. */ ETHERNETx->ETH_PSC = ETH_InitStruct->ETH_PSC; /* Set period the following of packages.*/ ETHERNETx->ETH_BAG = ETH_InitStruct->ETH_BAG; /* Set jitter of packets transmitted. */ ETHERNETx->ETH_JitterWnd = ETH_InitStruct->ETH_JitterWnd; }
/** * @brief Configures for the selected ADC injected channel its corresponding * rank in the sequencer and its sample time. * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param sConfigInjected: ADC configuration structure for injected channel. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { #ifdef USE_FULL_ASSERT uint32_t tmp = 0; #endif /* USE_FULL_ASSERT */ /* Check the parameters */ assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_ADC_EXT_INJEC_TRIG(sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_INJECTED_LENGTH(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); #ifdef USE_FULL_ASSERT tmp = ADC_GET_RESOLUTION(hadc); assert_param(IS_ADC_RANGE(tmp, sConfigInjected->InjectedOffset)); #endif /* USE_FULL_ASSERT */ if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START) { assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); } /* Process locked */ __HAL_LOCK(hadc); /* if ADC_Channel_10 ... ADC_Channel_18 is selected */ if (sConfigInjected->InjectedChannel > ADC_CHANNEL_9) { /* Clear the old sample time */ hadc->Instance->SMPR1 &= ~ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel); /* Set the new sample time */ hadc->Instance->SMPR1 |= ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); } else /* ADC_Channel include in ADC_Channel_[0..9] */ { /* Clear the old sample time */ hadc->Instance->SMPR2 &= ~ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel); /* Set the new sample time */ hadc->Instance->SMPR2 |= ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); } /*---------------------------- ADCx JSQR Configuration -----------------*/ hadc->Instance->JSQR &= ~(ADC_JSQR_JL); hadc->Instance->JSQR |= ADC_SQR1(sConfigInjected->InjectedNbrOfConversion); /* Rank configuration */ /* Clear the old SQx bits for the selected rank */ hadc->Instance->JSQR &= ~ADC_JSQR(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); /* Set the SQx bits for the selected rank */ hadc->Instance->JSQR |= ADC_JSQR(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank,sConfigInjected->InjectedNbrOfConversion); /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if(sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { /* Select external trigger to start conversion */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConv; /* Select external trigger polarity */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); hadc->Instance->CR2 |= sConfigInjected->ExternalTrigInjecConvEdge; } else { /* Reset the external trigger */ hadc->Instance->CR2 &= ~(ADC_CR2_JEXTSEL); hadc->Instance->CR2 &= ~(ADC_CR2_JEXTEN); } if (sConfigInjected->AutoInjectedConv != DISABLE) { /* Enable the selected ADC automatic injected group conversion */ hadc->Instance->CR1 |= ADC_CR1_JAUTO; } else { /* Disable the selected ADC automatic injected group conversion */ hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO); } if (sConfigInjected->InjectedDiscontinuousConvMode != DISABLE) { /* Enable the selected ADC injected discontinuous mode */ hadc->Instance->CR1 |= ADC_CR1_JDISCEN; } else { /* Disable the selected ADC injected discontinuous mode */ hadc->Instance->CR1 &= ~(ADC_CR1_JDISCEN); } switch(sConfigInjected->InjectedRank) { case 1: /* Set injected channel 1 offset */ hadc->Instance->JOFR1 &= ~(ADC_JOFR1_JOFFSET1); hadc->Instance->JOFR1 |= sConfigInjected->InjectedOffset; break; case 2: /* Set injected channel 2 offset */ hadc->Instance->JOFR2 &= ~(ADC_JOFR2_JOFFSET2); hadc->Instance->JOFR2 |= sConfigInjected->InjectedOffset; break; case 3: /* Set injected channel 3 offset */ hadc->Instance->JOFR3 &= ~(ADC_JOFR3_JOFFSET3); hadc->Instance->JOFR3 |= sConfigInjected->InjectedOffset; break; default: /* Set injected channel 4 offset */ hadc->Instance->JOFR4 &= ~(ADC_JOFR4_JOFFSET4); hadc->Instance->JOFR4 |= sConfigInjected->InjectedOffset; break; } /* if ADC1 Channel_18 is selected enable VBAT Channel */ if ((hadc->Instance == ADC1) && (sConfigInjected->InjectedChannel == ADC_CHANNEL_VBAT)) { /* Enable the VBAT channel*/ ADC->CCR |= ADC_CCR_VBATE; } /* if ADC1 Channel_16 or Channel_17 is selected enable TSVREFE Channel(Temperature sensor and VREFINT) */ if ((hadc->Instance == ADC1) && ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT))) { /* Enable the TSVREFE channel*/ ADC->CCR |= ADC_CCR_TSVREFE; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; }
/** * @brief Enables ADC, starts conversion of regular group and transfers result * through DMA. * Multimode must have been previously configured using * HAL_ADCEx_MultiModeConfigChannel() function. * Interruptions enabled in this function: * - DMA transfer complete * - DMA half transfer * Each of these interruptions has its dedicated callback function. * @note: On STM32F1 devices, ADC slave regular group must be configured * with conversion trigger ADC_SOFTWARE_START. * @note: ADC slave can be enabled preliminarily using single-mode * HAL_ADC_Start() function. * @param hadc: ADC handle of ADC master (handle of ADC slave must not be used) * @param pData: The destination Buffer address. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; ADC_HandleTypeDef tmphadcSlave; /* Check the parameters */ assert_param(IS_ADC_MULTIMODE_MASTER_INSTANCE(hadc->Instance)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); /* Process locked */ __HAL_LOCK(hadc); /* Set a temporary handle of the ADC slave associated to the ADC master */ ADC_MULTI_SLAVE(hadc, &tmphadcSlave); /* On STM32F1 devices, ADC slave regular group must be configured with */ /* conversion trigger ADC_SOFTWARE_START. */ /* Note: External trigger of ADC slave must be enabled, it is already done */ /* into function "HAL_ADC_Init()". */ if ((tmphadcSlave.Instance == NULL) || (! ADC_IS_SOFTWARE_START_REGULAR(&tmphadcSlave)) ) { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; /* Process unlocked */ __HAL_UNLOCK(hadc); return HAL_ERROR; } /* Enable the ADC peripherals: master and slave (in case if not already */ /* enabled previously) */ tmp_hal_status = ADC_Enable(hadc); if (tmp_hal_status != HAL_ERROR) { tmp_hal_status = ADC_Enable(&tmphadcSlave); } /* Start conversion all ADCs of multimode are effectively enabled */ if (tmp_hal_status != HAL_ERROR) { /* State machine update (ADC master): Check if an injected conversion is */ /* ongoing. */ if(hadc->State == HAL_ADC_STATE_BUSY_INJ) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_BUSY_INJ_REG; } else { /* Change ADC state */ hadc->State = HAL_ADC_STATE_BUSY_REG; } /* Process unlocked */ /* Unlock before starting ADC conversions: in case of potential */ /* interruption, to let the process to ADC IRQ Handler. */ __HAL_UNLOCK(hadc); /* Set ADC error code to none */ ADC_CLEAR_ERRORCODE(hadc); /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_DMAError; /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC */ /* start (in case of SW start): */ /* Clear regular group conversion flag and overrun flag */ /* (To ensure of no unknown state from potential previous ADC operations) */ __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC); /* Enable ADC DMA mode of ADC master */ SET_BIT(hadc->Instance->CR2, ADC_CR2_DMA); /* Start the DMA channel */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length); /* Start conversion of regular group if software start has been selected. */ /* If external trigger has been selected, conversion will start at next */ /* trigger event. */ /* Note: Alternate trigger for single conversion could be to force an */ /* additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/ if (ADC_IS_SOFTWARE_START_REGULAR(hadc)) { /* Start ADC conversion on regular group with SW start */ SET_BIT(hadc->Instance->CR2, (ADC_CR2_SWSTART | ADC_CR2_EXTTRIG)); } else { /* Start ADC conversion on regular group with external trigger */ SET_BIT(hadc->Instance->CR2, ADC_CR2_EXTTRIG); } } else { /* Process unlocked */ __HAL_UNLOCK(hadc); } /* Return function status */ return tmp_hal_status; }
/** * @brief Enables or disables the Tamper Pin Interrupt. * @param NewState: new state of the Tamper Pin Interrupt. * This parameter can be: ENABLE or DISABLE. * @retval None */ void BKP_ITConfig(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CSR_TPIE_BB = (uint32_t)NewState; }
/** * @brief Configures the ADC injected group and the selected channel to be * linked to the injected group. * @note Possibility to update parameters on the fly: * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. * The setting of these parameters is conditioned to ADC state: * this function must be called when ADC is not under conversion. * @param hadc: ADC handle * @param sConfigInjected: Structure of ADC injected group and ADC channel for * injected group. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { HAL_StatusTypeDef tmp_hal_status = HAL_OK; __IO uint32_t wait_loop_index = 0; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } /* Process locked */ __HAL_LOCK(hadc); /* Configuration of injected group sequencer: */ /* - if scan mode is disabled, injected channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, injected channels sequence length is set to */ /* parameter "InjectedNbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) { if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Clear the old SQx bits for all injected ranks */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 , ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1, 0x01) ); } /* If another injected rank than rank1 was intended to be set, and could */ /* not due to ScanConvMode disabled, error is reported. */ else { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; tmp_hal_status = HAL_ERROR; } } else { /* Since injected channels rank conv. order depends on total number of */ /* injected conversions, selected rank must be below or equal to total */ /* number of injected conversions to be updated. */ if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) { /* Clear the old SQx bits for the selected rank */ /* Set the SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) , ADC_JSQR_JL_SHIFT(sConfigInjected->InjectedNbrOfConversion) | ADC_JSQR_RK_JL(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) ); } else { /* Clear the old SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_RK_JL(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) , 0x00000000 ); } } /* Configuration of injected group */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - external trigger to start conversion */ /* Parameters update not conditioned to ADC state: */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ /* Note: In case of ADC already enabled, caution to not launch an unwanted */ /* conversion while modifying register CR2 by writing 1 to bit ADON. */ if (ADC_IS_ENABLE(hadc) == RESET) { MODIFY_REG(hadc->Instance->CR2 , ADC_CR2_JEXTSEL | ADC_CR2_ADON , ADC_CFGR_JEXTSEL(hadc, sConfigInjected->ExternalTrigInjecConv) ); } /* Configuration of injected group */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ /* Automatic injected conversion can be enabled if injected group */ /* external triggers are disabled. */ if (sConfigInjected->AutoInjectedConv == ENABLE) { if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); } else { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; tmp_hal_status = HAL_ERROR; } } /* Injected discontinuous can be enabled only if auto-injected mode is */ /* disabled. */ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) { if (sConfigInjected->AutoInjectedConv == DISABLE) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); } else { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; tmp_hal_status = HAL_ERROR; } } /* InjectedChannel sampling time configuration */ /* For channels 10 to 17 */ if (sConfigInjected->InjectedChannel >= ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR1 , ADC_SMPR1(ADC_SMPR1_SMP10, sConfigInjected->InjectedChannel) , ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } else /* For channels 0 to 9 */ { MODIFY_REG(hadc->Instance->SMPR2 , ADC_SMPR2(ADC_SMPR2_SMP0, sConfigInjected->InjectedChannel) , ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } /* If ADC1 InjectedChannel_16 or InjectedChannel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); } /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ switch(sConfigInjected->InjectedRank) { case 1: /* Set injected channel 1 offset */ MODIFY_REG(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1, sConfigInjected->InjectedOffset); break; case 2: /* Set injected channel 2 offset */ MODIFY_REG(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2, sConfigInjected->InjectedOffset); break; case 3: /* Set injected channel 3 offset */ MODIFY_REG(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3, sConfigInjected->InjectedOffset); break; case 4: default: MODIFY_REG(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4, sConfigInjected->InjectedOffset); break; } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) { /* For STM32F1 devices with several ADC: Only ADC1 can access internal */ /* measurement channels (VrefInt/TempSensor). If these channels are */ /* intended to be set on other ADC instances, an error is reported. */ if (hadc->Instance == ADC1) { if (READ_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE) == RESET) { SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) { /* Delay for temperature sensor stabilization time */ /* Compute number of CPU cycles to wait for */ wait_loop_index = (ADC_TEMPSENSOR_DELAY_US * (SystemCoreClock / 1000000)); while(wait_loop_index != 0) { wait_loop_index--; } } } } else { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; tmp_hal_status = HAL_ERROR; } } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmp_hal_status; }
/** * @brief Configures the CAN reception filter according to the specified * parameters in the CAN_FilterInitStruct. * @param hcan: pointer to a CAN_HandleTypeDef structure that contains * the configuration information for the specified CAN. * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that * contains the filter configuration information. * @retval None */ HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig) { uint32_t filternbrbitpos = 0; /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber)); assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode)); assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale)); assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment)); assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation)); assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber)); filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber; /* Initialisation mode for the filter */ hcan->Instance->FMR |= (uint32_t)CAN_FMR_FINIT; /* Filter Deactivation */ hcan->Instance->FA1R &= ~(uint32_t)filternbrbitpos; /* Filter Scale */ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT) { /* 16-bit scale for the filter */ hcan->Instance->FS1R &= ~(uint32_t)filternbrbitpos; /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) | (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh); } if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT) { /* 32-bit scale for the filter */ hcan->Instance->FS1R |= filternbrbitpos; /* 32-bit identifier or First 32-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR1 = ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) | (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow); /* 32-bit mask or Second 32-bit identifier */ hcan->Instance->sFilterRegister[sFilterConfig->FilterNumber].FR2 = ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) | (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow); } /* Filter Mode */ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK) { /*Id/Mask mode for the filter*/ hcan->Instance->FM1R &= ~(uint32_t)filternbrbitpos; } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /*Identifier list mode for the filter*/ hcan->Instance->FM1R |= (uint32_t)filternbrbitpos; } /* Filter FIFO assignment */ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0) { /* FIFO 0 assignation for the filter */ hcan->Instance->FFA1R &= ~(uint32_t)filternbrbitpos; } if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1) { /* FIFO 1 assignation for the filter */ hcan->Instance->FFA1R |= (uint32_t)filternbrbitpos; } /* Filter activation */ if (sFilterConfig->FilterActivation == ENABLE) { hcan->Instance->FA1R |= filternbrbitpos; } /* Leave the initialisation mode for the filter */ hcan->Instance->FMR &= ~((uint32_t)CAN_FMR_FINIT); /* Return function status */ return HAL_OK; }
/** * @brief POWER_PVDenable - Enables or disables the Power Voltage Detectors (PVD, PVBD). * @param NewState: new state of the PVDs. * This parameter can be: ENABLE or DISABLE. * @retval None */ void POWER_PVDenable(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) POWER_PVDEN_BB = (uint32_t)NewState; }
/** * @brief Handles ADC interrupt request * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc) { uint32_t tmp1 = 0, tmp2 = 0; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_REGULAR_LENGTH(hadc->Init.NbrOfConversion)); assert_param(IS_ADC_EOCSelection(hadc->Init.EOCSelection)); tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC); tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC); /* Check End of conversion flag for regular channels */ if(tmp1 && tmp2) { /* Check if an injected conversion is ready */ if(hadc->State == HAL_ADC_STATE_EOC_INJ) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; } else { /* Change ADC state */ hadc->State = HAL_ADC_STATE_EOC_REG; } if((hadc->Init.ContinuousConvMode == DISABLE) && ((hadc->Instance->CR2 & ADC_CR2_EXTEN) == RESET)) { if(hadc->Init.EOCSelection == ADC_EOC_SEQ_CONV) { /* DISABLE the ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* DISABLE the ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); } else { if (hadc->NbrOfCurrentConversionRank == 0) { hadc->NbrOfCurrentConversionRank = hadc->Init.NbrOfConversion; } /* Decrement the number of conversion when an interrupt occurs */ hadc->NbrOfCurrentConversionRank--; /* Check if all conversions are finished */ if(hadc->NbrOfCurrentConversionRank == 0) { /* DISABLE the ADC end of conversion interrupt for regular group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC); /* DISABLE the ADC overrun interrupt */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_OVR); } } } /* Conversion complete callback */ HAL_ADC_ConvCpltCallback(hadc); /* Clear the ADCx flag for regular end of conversion */ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_EOC); } tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC); tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC); /* Check End of conversion flag for injected channels */ if(tmp1 && tmp2) { /* Check if a regular conversion is ready */ if(hadc->State == HAL_ADC_STATE_EOC_REG) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_EOC_INJ_REG; } else { /* Change ADC state */ hadc->State = HAL_ADC_STATE_EOC_INJ; } tmp1 = HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO); tmp2 = HAL_IS_BIT_CLR(hadc->Instance->CR2, ADC_CR2_JEXTEN); if(((hadc->Init.ContinuousConvMode == DISABLE) || tmp1) && tmp2) { /* DISABLE the ADC end of conversion interrupt for injected group */ __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC); } /* Conversion complete callback */ HAL_ADCEx_InjectedConvCpltCallback(hadc); /* Clear the ADCx flag for injected end of conversion */ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_JEOC); } tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD); tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD); /* Check Analog watchdog flag */ if(tmp1 && tmp2) { /* Change ADC state */ hadc->State = HAL_ADC_STATE_AWD; /* Clear the ADCx's Analog watchdog flag */ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD); /* Level out of window callback */ HAL_ADC_LevelOutOfWindowCallback(hadc); } tmp1 = __HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR); tmp2 = __HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR); /* Check Overrun flag */ if(tmp1 && tmp2) { /* Change ADC state to overrun state */ hadc->State = HAL_ADC_STATE_ERROR; /* Set ADC error code to overrun */ hadc->ErrorCode |= HAL_ADC_ERROR_OVR; /* Clear the Overrun flag */ __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_OVR); /* Error callback */ HAL_ADC_ErrorCallback(hadc); } }
/** * @brief Enables ADC DMA request after last transfer (Multi-ADC mode) and enables ADC peripheral * * @note Caution: This function must be used only with the ADC master. * * @param hadc: pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. * @param Length: The length of data to be transferred from ADC peripheral to memory. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) { uint16_t counter = 0; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode)); assert_param(IS_ADC_EXT_TRIG_EDGE(hadc->Init.ExternalTrigConvEdge)); assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests)); /* Process locked */ __HAL_LOCK(hadc); /* Enable ADC overrun interrupt */ __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR); if (hadc->Init.DMAContinuousRequests != DISABLE) { /* Enable the selected ADC DMA request after last transfer */ ADC->CCR |= ADC_CCR_DDS; } else { /* Disable the selected ADC EOC rising on each regular channel conversion */ ADC->CCR &= ~ADC_CCR_DDS; } /* Set the DMA transfer complete callback */ hadc->DMA_Handle->XferCpltCallback = ADC_MultiModeDMAConvCplt; /* Set the DMA half transfer complete callback */ hadc->DMA_Handle->XferHalfCpltCallback = ADC_MultiModeDMAHalfConvCplt; /* Set the DMA error callback */ hadc->DMA_Handle->XferErrorCallback = ADC_MultiModeDMAError ; /* Enable the DMA Stream */ HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&ADC->CDR, (uint32_t)pData, Length); /* Change ADC state */ hadc->State = HAL_ADC_STATE_BUSY_REG; /* Check if ADC peripheral is disabled in order to enable it and wait during Tstab time the ADC's stabilization */ if((hadc->Instance->CR2 & ADC_CR2_ADON) != ADC_CR2_ADON) { /* Enable the Peripheral */ __HAL_ADC_ENABLE(hadc); /* Delay inserted to wait during Tstab time the ADC's stabilazation */ for(; counter <= 540; counter++) { __NOP(); } } /* if no external trigger present enable software conversion of regular channels */ if (hadc->Init.ExternalTrigConvEdge == ADC_EXTERNALTRIGCONVEDGE_NONE) { /* Enable the selected ADC software conversion for regular group */ hadc->Instance->CR2 |= (uint32_t)ADC_CR2_SWSTART; } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return HAL_OK; }
/** * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. * @retval An ErrorStatus enumeration value: * - SUCCESS: EXTI registers are initialized * - ERROR: not applicable */ uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) { ErrorStatus status = SUCCESS; /* Check the parameters */ assert_param(IS_LL_EXTI_LINE_0_31(EXTI_InitStruct->Line_0_31)); assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); /* ENABLE LineCommand */ if (EXTI_InitStruct->LineCommand != DISABLE) { assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); /* Configure EXTI Lines in range from 0 to 31 */ if (EXTI_InitStruct->Line_0_31 != LL_EXTI_LINE_NONE) { switch (EXTI_InitStruct->Mode) { case LL_EXTI_MODE_IT: /* First Disable Event on provided Lines */ LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); /* Then Enable IT on provided Lines */ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); break; case LL_EXTI_MODE_EVENT: /* First Disable IT on provided Lines */ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); /* Then Enable Event on provided Lines */ LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); break; case LL_EXTI_MODE_IT_EVENT: /* Directly Enable IT & Event on provided Lines */ LL_EXTI_EnableIT_0_31(EXTI_InitStruct->Line_0_31); LL_EXTI_EnableEvent_0_31(EXTI_InitStruct->Line_0_31); break; default: status = ERROR; break; } if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) { switch (EXTI_InitStruct->Trigger) { case LL_EXTI_TRIGGER_RISING: /* First Disable Falling Trigger on provided Lines */ LL_EXTI_DisableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); /* Then Enable Rising Trigger on provided Lines */ LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); break; case LL_EXTI_TRIGGER_FALLING: /* First Disable Rising Trigger on provided Lines */ LL_EXTI_DisableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); /* Then Enable Falling Trigger on provided Lines */ LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); break; case LL_EXTI_TRIGGER_RISING_FALLING: LL_EXTI_EnableRisingTrig_0_31(EXTI_InitStruct->Line_0_31); LL_EXTI_EnableFallingTrig_0_31(EXTI_InitStruct->Line_0_31); break; default: status = ERROR; break; } } } } /* DISABLE LineCommand */ else { /* De-configure EXTI Lines in range from 0 to 31 */ LL_EXTI_DisableIT_0_31(EXTI_InitStruct->Line_0_31); LL_EXTI_DisableEvent_0_31(EXTI_InitStruct->Line_0_31); } return status; }
/** * @brief Configures the ADC injected group and the selected channel to be * linked to the injected group. * @note Possibility to update parameters on the fly: * This function initializes injected group, following calls to this * function can be used to reconfigure some parameters of structure * "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC. * The setting of these parameters is conditioned to ADC state: * this function must be called when ADC is not under conversion. * @param hadc: ADC handle * @param sConfigInjected: Structure of ADC injected group and ADC channel for * injected group. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) { HAL_StatusTypeDef tmpHALStatus = HAL_OK; /* Check the parameters */ assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance)); assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel)); assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv)); assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv)); assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset)); if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE) { assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank)); assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion)); assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode)); } if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START) { assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge)); } /* Process locked */ __HAL_LOCK(hadc); /* Configuration of injected group sequencer: */ /* - if scan mode is disabled, injected channels sequence length is set to */ /* 0x00: 1 channel converted (channel on regular rank 1) */ /* Parameter "InjectedNbrOfConversion" is discarded. */ /* Note: Scan mode is present by hardware on this device and, if */ /* disabled, discards automatically nb of conversions. Anyway, nb of */ /* conversions is forced to 0x00 for alignment over all STM32 devices. */ /* - if scan mode is enabled, injected channels sequence length is set to */ /* parameter ""InjectedNbrOfConversion". */ if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE) { if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1) { /* Clear the old SQx bits for all injected ranks */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 , __ADC_JSQR_RK(sConfigInjected->InjectedChannel, ADC_INJECTED_RANK_1, 0x01) ); } /* If another injected rank than rank1 was intended to be set, and could */ /* not due to ScanConvMode disabled, error is reported. */ else { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; tmpHALStatus = HAL_ERROR; } } else { /* Since injected channels rank conv. order depends on total number of */ /* injected conversions, selected rank must be below or equal to total */ /* number of injected conversions to be updated. */ if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion) { /* Clear the old SQx bits for the selected rank */ /* Set the SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | __ADC_JSQR_RK(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) , __ADC_JSQR_JL(sConfigInjected->InjectedNbrOfConversion) | __ADC_JSQR_RK(sConfigInjected->InjectedChannel, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) ); } else { /* Clear the old SQx bits for the selected rank */ MODIFY_REG(hadc->Instance->JSQR , ADC_JSQR_JL | __ADC_JSQR_RK(ADC_JSQR_JSQ1, sConfigInjected->InjectedRank, sConfigInjected->InjectedNbrOfConversion) , 0x00000000 ); } } /* Enable external trigger if trigger selection is different of software */ /* start. */ /* Note: This configuration keeps the hardware feature of parameter */ /* ExternalTrigConvEdge "trigger edge none" equivalent to */ /* software start. */ if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START) { MODIFY_REG(hadc->Instance->CR2 , ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL , sConfigInjected->ExternalTrigInjecConv | sConfigInjected->ExternalTrigInjecConvEdge ); } else { MODIFY_REG(hadc->Instance->CR2, ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL , 0x00000000 ); } /* Configuration of injected group */ /* Parameters update conditioned to ADC state: */ /* Parameters that can be updated only when ADC is disabled: */ /* - Automatic injected conversion */ /* - Injected discontinuous mode */ if ((__HAL_ADC_IS_ENABLED(hadc) == RESET)) { hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO | ADC_CR1_JDISCEN ); /* Automatic injected conversion can be enabled if injected group */ /* external triggers are disabled. */ if (sConfigInjected->AutoInjectedConv == ENABLE) { if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO); } else { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; tmpHALStatus = HAL_ERROR; } } /* Injected discontinuous can be enabled only if auto-injected mode is */ /* disabled. */ if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE) { if (sConfigInjected->AutoInjectedConv == DISABLE) { SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN); } else { /* Update ADC state machine to error */ hadc->State = HAL_ADC_STATE_ERROR; tmpHALStatus = HAL_ERROR; } } } /* InjectedChannel sampling time configuration */ /* For InjectedChannels 0 to 9 */ if (sConfigInjected->InjectedChannel < ADC_CHANNEL_10) { MODIFY_REG(hadc->Instance->SMPR3, __ADC_SMPR3(ADC_SMPR3_SMP0, sConfigInjected->InjectedChannel), __ADC_SMPR3(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } /* For InjectedChannels 10 to 19 */ else if (sConfigInjected->InjectedChannel < ADC_CHANNEL_20) { MODIFY_REG(hadc->Instance->SMPR2, __ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel), __ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } /* For InjectedChannels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */ /* For InjectedChannels 20 to 29 for devices Cat4, Cat.5 */ else if (sConfigInjected->InjectedChannel <= ADC_SMPR1_CHANNEL_MAX) { MODIFY_REG(hadc->Instance->SMPR1, __ADC_SMPR1(ADC_SMPR1_SMP20, sConfigInjected->InjectedChannel), __ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) ); } /* For InjectedChannels 30 to 31 for devices Cat4, Cat.5 */ else { __ADC_SMPR0_CHANNEL_SET(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel); } /* Configure the offset: offset enable/disable, InjectedChannel, offset value */ switch(sConfigInjected->InjectedRank) { case 1: /* Set injected channel 1 offset */ MODIFY_REG(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1, sConfigInjected->InjectedOffset); break; case 2: /* Set injected channel 2 offset */ MODIFY_REG(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2, sConfigInjected->InjectedOffset); break; case 3: /* Set injected channel 3 offset */ MODIFY_REG(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3, sConfigInjected->InjectedOffset); break; case 4: default: MODIFY_REG(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4, sConfigInjected->InjectedOffset); break; } /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor */ /* and VREFINT measurement path. */ if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) || (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT) ) { SET_BIT(ADC->CCR, ADC_CCR_TSVREFE); } /* Process unlocked */ __HAL_UNLOCK(hadc); /* Return function status */ return tmpHALStatus; }
/** * @brief Enables or disables the Power Voltage Detector(PVD). * @param NewState: new state of the PVD. * This parameter can be: ENABLE or DISABLE. * @retval None */ void PWR_PVDCmd(FunctionalState NewState) { /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState; }
/******************************************************************************* * Function Name : CAN_Init * Description : Initializes the CAN peripheral according to the specified * parameters in the CAN_InitStruct. * Input : CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains the configuration information for the CAN peripheral. * Output : None. * Return : Constant indicates initialization succeed which will be * CANINITFAILED or CANINITOK. *******************************************************************************/ u8 CAN_Init(CAN_InitTypeDef* CAN_InitStruct) { u8 InitStatus = 0; u16 WaitAck = 0; /* Check the parameters */ assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM)); assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP)); assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode)); assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW)); assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1)); assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2)); assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler)); /* Request initialisation */ CAN->MCR = MCR_INRQ; /* ...and check acknowledged */ if ((CAN->MSR & MSR_INAK) == 0) { InitStatus = CANINITFAILED; } else { /* Set the time triggered communication mode */ if (CAN_InitStruct->CAN_TTCM == ENABLE) { CAN->MCR |= MCR_TTCM; } else { CAN->MCR &= ~MCR_TTCM; } /* Set the automatic bus-off management */ if (CAN_InitStruct->CAN_ABOM == ENABLE) { CAN->MCR |= MCR_ABOM; } else { CAN->MCR &= ~MCR_ABOM; } /* Set the automatic wake-up mode */ if (CAN_InitStruct->CAN_AWUM == ENABLE) { CAN->MCR |= MCR_AWUM; } else { CAN->MCR &= ~MCR_AWUM; } /* Set the no automatic retransmission */ if (CAN_InitStruct->CAN_NART == ENABLE) { CAN->MCR |= MCR_NART; } else { CAN->MCR &= ~MCR_NART; } /* Set the receive FIFO locked mode */ if (CAN_InitStruct->CAN_RFLM == ENABLE) { CAN->MCR |= MCR_RFLM; } else { CAN->MCR &= ~MCR_RFLM; } /* Set the transmit FIFO priority */ if (CAN_InitStruct->CAN_TXFP == ENABLE) { CAN->MCR |= MCR_TXFP; } else { CAN->MCR &= ~MCR_TXFP; } /* Set the bit timing register */ CAN->BTR = (u32)((u32)CAN_InitStruct->CAN_Mode << 30) | ((u32)CAN_InitStruct->CAN_SJW << 24) | ((u32)CAN_InitStruct->CAN_BS1 << 16) | ((u32)CAN_InitStruct->CAN_BS2 << 20) | ((u32)CAN_InitStruct->CAN_Prescaler - 1); InitStatus = CANINITOK; /* Request leave initialisation */ CAN->MCR &= ~MCR_INRQ; /* Wait the acknowledge */ for(WaitAck = 0x400; WaitAck > 0x0; WaitAck--) { } /* ...and check acknowledged */ if ((CAN->MSR & MSR_INAK) == MSR_INAK) { InitStatus = CANINITFAILED; } } /* At this step, return the status of initialization */ return InitStatus; }
/** * @brief Initializes the CAN peripheral according to the specified * parameters in the CAN_FilterInitStruct. * @param CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef * structure that contains the configuration information. * @retval None. */ void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct) { uint32_t filter_number_bit_pos = 0; /* Check the parameters */ assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber)); assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode)); assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale)); assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment)); assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation)); filter_number_bit_pos = ((uint32_t)0x00000001) << CAN_FilterInitStruct->CAN_FilterNumber; /* Initialisation mode for the filter */ CAN1->FMR |= FMR_FINIT; /* Filter Deactivation */ CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos; /* Filter Scale */ if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit) { /* 16-bit scale for the filter */ CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos; /* First 16-bit identifier and First 16-bit mask */ /* Or First 16-bit identifier and Second 16-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); /* Second 16-bit identifier and Second 16-bit mask */ /* Or Third 16-bit identifier and Fourth 16-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh); } if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit) { /* 32-bit scale for the filter */ CAN1->FS1R |= filter_number_bit_pos; /* 32-bit identifier or First 32-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow); /* 32-bit mask or Second 32-bit identifier */ CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) | (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow); } /* Filter Mode */ if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask) { /*Id/Mask mode for the filter*/ CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos; } else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */ { /*Identifier list mode for the filter*/ CAN1->FM1R |= (uint32_t)filter_number_bit_pos; } /* Filter FIFO assignment */ if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO0) { /* FIFO 0 assignation for the filter */ CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos; } if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_FilterFIFO1) { /* FIFO 1 assignation for the filter */ CAN1->FFA1R |= (uint32_t)filter_number_bit_pos; } /* Filter activation */ if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE) { CAN1->FA1R |= filter_number_bit_pos; } /* Leave the initialisation mode for the filter */ CAN1->FMR &= ~FMR_FINIT; }
/** * @brief Enables or disables the CEC peripheral. * @param NewState: new state of the CEC peripheral. * This parameter can be: ENABLE or DISABLE. * @retval None */ void CEC_Cmd(FunctionalState NewState) { assert_param(IS_FUNCTIONAL_STATE(NewState)); *(__IO uint32_t *) CR_CECEN_BB = (uint32_t)NewState; }