VOID RT3070_PowerTuning( IN PRTMP_ADAPTER pAd, IN RSSI_SAMPLE *pRssi) { /* request by Gary, if Rssi0 > -42, BBP 82 need to be changed from 0x62 to 0x42, , bbp 67 need to be changed from 0x20 to 0x18 */ if (!pAd->CommonCfg.HighPowerPatchDisabled) { if (((IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201)) || IS_RT2070(pAd)) && !RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_IDLE_RADIO_OFF)) { UCHAR RFValue; if ((pRssi->AvgRssi0 != 0) && (pRssi->AvgRssi0 > (pAd->BbpRssiToDbmDelta - 35))) { /*RT30xxWriteRFRegister(pAd, RF_R27, 0x20); */ RT30xxReadRFRegister(pAd, RF_R27, (PUCHAR)&RFValue); RFValue &= ~0x3; RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)RFValue); } else { /*RT30xxWriteRFRegister(pAd, RF_R27, 0x23); */ RT30xxReadRFRegister(pAd, RF_R27, (PUCHAR)&RFValue); RFValue |= 0x3; RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)RFValue); } } } }
VOID RT30xx_ChipAGCInit( IN PRTMP_ADAPTER pAd, IN UCHAR BandWidth) { UCHAR R66 = 0x30; if (pAd->LatchRfRegs.Channel <= 14) { /* BG band*/ /* Gary was verified Amazon AP and find that RT307x has BBP_R66 invalid default value */ if (IS_RT3070(pAd)||IS_RT3090(pAd) || IS_RT3390(pAd)) { R66 = 0x1C + 2*GET_LNA_GAIN(pAd); AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL); } } else { /* A band */ if (BandWidth == BW_20) { R66 = (UCHAR)(0x32 + (GET_LNA_GAIN(pAd)*5)/3); AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL); } #ifdef DOT11_N_SUPPORT else { R66 = (UCHAR)(0x3A + (GET_LNA_GAIN(pAd)*5)/3); AsicBBPWriteWithRxChain(pAd, BBP_R66, R66, RX_CHAIN_ALL); } #endif // DOT11_N_SUPPORT // } }
VOID RT30xxHaltAction( IN PRTMP_ADAPTER pAd) { UINT32 TxPinCfg = 0x00050F0F; // // Turn off LNA_PE or TRSW_POL // if (IS_RT3070(pAd) || IS_RT3071(pAd) || IS_RT3572(pAd) || IS_RT5390(pAd)) { if ((IS_RT3071(pAd) || IS_RT3572(pAd) || IS_RT5390(pAd)) #ifdef RTMP_EFUSE_SUPPORT && (pAd->bUseEfuse) #endif // RTMP_EFUSE_SUPPORT // ) { TxPinCfg &= 0xFFFBF0F0; // bit18 off } else { TxPinCfg &= 0xFFFFF0F0; } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); } }
VOID RtmpChipOpsRFHook( IN RTMP_ADAPTER *pAd) { RTMP_CHIP_OP *pChipOps = &pAd->chipOps; pChipOps->pRFRegTable = NULL; pChipOps->pBBPRegTable = NULL; pChipOps->AsicRfInit = NULL; pChipOps->AsicRfTurnOn = NULL; pChipOps->AsicRfTurnOff = NULL; pChipOps->AsicReverseRfFromSleepMode = NULL; pChipOps->AsicHaltAction = NULL; /* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */ #ifdef RT30xx #ifdef RT3593 if (IS_RT3593(pAd)) { pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup; pChipOps->pRFRegTable = RF3053RegTable; pChipOps->AsicRfInit = NICInitRT3593RFRegisters; pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup; pChipOps->AsicHaltAction = RT30xxHaltAction; } #endif // RT3593 // if (IS_RT30xx(pAd)) { /* WARNING: Currently following table are shared by all RT30xx based IC, change it carefully when you add a new IC here. */ pChipOps->pRFRegTable = RT3020_RFRegTable; pChipOps->AsicHaltAction = RT30xxHaltAction; pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup; pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup; #ifdef RT3070 if((IS_RT3070(pAd) || IS_RT3071(pAd)) && (pAd->infType == RTMP_DEV_INF_USB)) { pChipOps->AsicRfInit = NICInitRT3070RFRegisters; } #endif // RT3070 // } #endif // RT30xx // if (pChipOps->pBBPRegTable != NULL) pChipOps->bbpRegTbSize = (sizeof(*(pChipOps->pBBPRegTable)) / sizeof(REG_PAIR)); DBGPRINT(RT_DEBUG_TRACE, ("Chip specific bbpRegTbSize=%d!\n", pChipOps->bbpRegTbSize)); }
/* ======================================================================== Routine Description: Initialize RT35xx. Arguments: pAd - WLAN control block pointer Return Value: None Note: ======================================================================== */ VOID RT30xx_Init( IN PRTMP_ADAPTER pAd) { RTMP_CHIP_OP *pChipOps = &pAd->chipOps; RTMP_CHIP_CAP *pChipCap = &pAd->chipCap; /* init capability */ /* WARNING: Currently following table are shared by all RT30xx based IC, change it carefully when you add a new IC here. */ pChipCap->pRFRegTable = RT3020_RFRegTable; pChipCap->MaxNumOfBbpId = 185; /* init operator */ if((IS_RT3070(pAd) || IS_RT3071(pAd)) || IS_RT3090(pAd)) { #ifdef RT3070 if (pAd->infType == RTMP_DEV_INF_USB) { pChipOps->AsicRfInit = NICInitRT3070RFRegisters; } #endif /* RT3070 */ pChipOps->AsicHaltAction = RT30xxHaltAction; pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup; pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup; pChipOps->ChipSwitchChannel = RT30xx_ChipSwitchChannel; pChipOps->ChipBBPAdjust = RT30xx_ChipBBPAdjust; pChipOps->RTMPSetAGCInitValue = RT30xx_RTMPSetAGCInitValue; /* 1T1R only */ if (!IS_RT3071(pAd)) { pChipOps->SetRxAnt = RT30xxSetRxAnt; pAd->Mlme.bEnableAutoAntennaCheck = FALSE; } pChipOps->ChipResumeMsduTransmission = NULL; pChipOps->VdrTuning1 = NULL; pChipOps->RxSensitivityTuning = NULL; #ifdef RTMP_FREQ_CALIBRATION_SUPPORT pChipOps->AsicFreqCalInit = NULL; pChipOps->AsicFreqCalStop = NULL; pChipOps->AsicFreqCal = NULL; pChipOps->AsicFreqOffsetGet = NULL; #endif /* RTMP_FREQ_CALIBRATION_SUPPORT */ } }
/* Antenna divesity use GPIO3 and EESK pin for control Antenna and EEPROM access are both using EESK pin, Therefor we should avoid accessing EESK at the same time Then restore antenna after EEPROM access The original name of this function is AsicSetRxAnt(), now change to */ VOID RT30xxSetRxAnt( IN PRTMP_ADAPTER pAd, IN UCHAR Ant) { UINT32 Value; if (/*(!pAd->NicConfig2.field.AntDiversity) ||*/ (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RESET_IN_PROGRESS)) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_HALT_IN_PROGRESS)) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_RADIO_OFF)) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) { return; } /* the antenna selection is through firmware and MAC register(GPIO3) */ if (IS_RT2070(pAd) || (IS_RT3070(pAd) && pAd->RfIcType == RFIC_3020) || (IS_RT3090(pAd) && pAd->RfIcType == RFIC_3020)) { if (Ant == 0) { /* Main antenna E2PROM_CSR only in PCI bus Reg., USB Bus need MCU commad to control the EESK pin. */ #ifdef RTMP_MAC_USB AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x1, 0x0); #endif /* RTMP_MAC_USB */ RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value); Value &= ~(0x0808); RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value); DBGPRINT(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to main antenna\n")); } else { /* Aux antenna E2PROM_CSR only in PCI bus Reg., USB Bus need MCU commad to control the EESK pin. */ #ifdef RTMP_MAC_USB AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x0, 0x0); #endif /* RTMP_MAC_USB */ RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value); Value &= ~(0x0808); Value |= 0x08; RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value); DBGPRINT(RT_DEBUG_TRACE, ("AsicSetRxAnt, switch to aux antenna\n")); } } }
VOID RT35xxLoadRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; #ifdef RT35xx if(IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, 0x00); #endif /* RT35xx */ if(!IS_RT3572(pAd)) { /* RF_BLOCK_en. RF R1 register Bit 0 to 0*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue &= (~0x01); RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 0*/ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue &= (~0x30); RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0*/ RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue &= (~0x0E); RT30xxWriteRFRegister(pAd, RF_R09, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 0*/ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x80); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } /* Don't touch LDO_CFG0 for 3090F & 3593, possibly the board is single power scheme*/ if (IS_RT3090(pAd) || /*IS_RT3090 including RT309x and RT3071/72*/ IS_RT3572(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if (!IS_RT3572(pAd)) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); RFValue |= 0x77; RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue |= 0x1D000000; RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ VOID RT30xxReverseRFSleepModeSetup( IN PRTMP_ADAPTER pAd, IN BOOLEAN FlgIsInitState) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { /* RF_BLOCK_en, RF R1 register Bit 0 to 1*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1*/ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue |= 0x20; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1*/ RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue |= 0x0E; RT30xxWriteRFRegister(pAd, RF_R09, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 1*/ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72*/ IS_RT3390(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); if ((pAd->MACVersion & 0xffff) < 0x0211) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } /* RT3071 version E has fixed this issue*/ } }
/* ========================================================================== Description: Load RF sleep-mode setup ========================================================================== */ void RT30xxLoadRFSleepModeSetup(struct rt_rtmp_adapter *pAd) { u8 RFValue; u32 MACValue; #ifdef RTMP_MAC_USB if (!IS_RT3572(pAd)) #endif /* RTMP_MAC_USB // */ { /* RF_BLOCK_en. RF R1 register Bit 0 to 0 */ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue &= (~0x01); RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 0 */ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue &= (~0x30); RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0 */ RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue &= (~0x0E); RT30xxWriteRFRegister(pAd, RF_R09, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 0 */ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x80); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72 */ IS_RT3572(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { #ifdef RTMP_MAC_USB if (!IS_RT3572(pAd)) #endif /* RTMP_MAC_USB // */ { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); RFValue |= 0x77; RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue |= 0x1D000000; RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } }
/* Antenna divesity use GPIO3 and EESK pin for control Antenna and EEPROM access are both using EESK pin, Therefor we should avoid accessing EESK at the same time Then restore antenna after EEPROM access The original name of this function is AsicSetRxAnt(), now change to */ VOID RT30xxSetRxAnt( IN PRTMP_ADAPTER pAd, IN UCHAR Ant) { UINT32 Value; /* the antenna selection is through firmware and MAC register(GPIO3) */ if (IS_RT3070(pAd) && pAd->RfIcType == RFIC_3020) // if (IS_RT2070(pAd) || (IS_RT3070(pAd) && pAd->RfIcType == RFIC_3020) || // (IS_RT3090(pAd) && pAd->RfIcType == RFIC_3020)) { if (Ant == 0) { /* Main antenna E2PROM_CSR only in PCI bus Reg., USB Bus need MCU commad to control the EESK pin. */ #ifdef RTMP_MAC_USB AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x1, 0x0); #endif /* RTMP_MAC_USB */ RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value); Value &= ~(0x0808); RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value); DBGPRINT(RT_DEBUG_TRACE, "AsicSetRxAnt, switch to main antenna\n"); } else { /* Aux antenna E2PROM_CSR only in PCI bus Reg., USB Bus need MCU commad to control the EESK pin. */ #ifdef RTMP_MAC_USB AsicSendCommandToMcu(pAd, 0x73, 0xFF, 0x0, 0x0); #endif /* RTMP_MAC_USB */ RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value); Value &= ~(0x0808); Value |= 0x08; RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value); DBGPRINT(RT_DEBUG_TRACE, "AsicSetRxAnt, switch to aux antenna\n"); } } else{ DBGPRINT(RT_DEBUG_ERROR, "RfIcType(%d) is unknow!!\n", pAd->RfIcType); } }
/* ========================================================================== Description: Load RF sleep-mode setup ========================================================================== */ VOID RT33xxLoadRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; { // RF_BLOCK_en. RF R1 register Bit 0 to 0 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue &= (~0x01); RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // VCO_IC, RF R7 register Bit 4 & Bit 5 to 0 RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue &= (~0x30); RT30xxWriteRFRegister(pAd, RF_R07, RFValue); // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue &= (~0x0E); RT30xxWriteRFRegister(pAd, RF_R09, RFValue); // RX_CTB_en, RF R21 register Bit 7 to 0 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x80); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72 IS_RT3572(pAd) || IS_RT3390(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); RFValue |= 0x77; RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue |= 0x1D000000; RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } }
void RT30xxHaltAction(struct rt_rtmp_adapter *pAd) { u32 TxPinCfg = 0x00050F0F; /* */ /* Turn off LNA_PE or TRSW_POL */ /* */ if (IS_RT3070(pAd) || IS_RT3071(pAd) || IS_RT3572(pAd)) { if ((IS_RT3071(pAd) || IS_RT3572(pAd)) #ifdef RTMP_EFUSE_SUPPORT && (pAd->bUseEfuse) #endif /* RTMP_EFUSE_SUPPORT // */ ) { TxPinCfg &= 0xFFFBF0F0; /* bit18 off */ } else { TxPinCfg &= 0xFFFFF0F0; } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); } }
VOID RT30xx_RTMPSetAGCInitValue( IN PRTMP_ADAPTER pAd, IN UCHAR BandWidth) { UCHAR R66 = 0x30; if (pAd->LatchRfRegs.Channel <= 14) { /* BG band*/ /* Gary was verified Amazon AP and find that RT307x has BBP_R66 invalid default value */ if (IS_RT3070(pAd)||IS_RT3090(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd)) { R66 = 0x1C + 2*GET_LNA_GAIN(pAd); { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, R66); } } } }
void RtmpChipOpsRFHook(struct rt_rtmp_adapter *pAd) { struct rt_rtmp_chip_op *pChipOps = &pAd->chipOps; pChipOps->pRFRegTable = NULL; pChipOps->AsicRfInit = NULL; pChipOps->AsicRfTurnOn = NULL; pChipOps->AsicRfTurnOff = NULL; pChipOps->AsicReverseRfFromSleepMode = NULL; pChipOps->AsicHaltAction = NULL; /* We depends on RfICType and MACVersion to assign the corresponding operation callbacks. */ #ifdef RT30xx if (IS_RT30xx(pAd)) { pChipOps->pRFRegTable = RT30xx_RFRegTable; pChipOps->AsicHaltAction = RT30xxHaltAction; #ifdef RT3070 if ((IS_RT3070(pAd) || IS_RT3071(pAd)) && (pAd->infType == RTMP_DEV_INF_USB)) { pChipOps->AsicRfInit = NICInitRT3070RFRegisters; if (IS_RT3071(pAd)) { pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup; pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup; } } #endif /* RT3070 // */ #ifdef RT3090 if (IS_RT3090(pAd) && (pAd->infType == RTMP_DEV_INF_PCI)) { pChipOps->AsicRfTurnOff = RT30xxLoadRFSleepModeSetup; pChipOps->AsicRfInit = NICInitRT3090RFRegisters; pChipOps->AsicReverseRfFromSleepMode = RT30xxReverseRFSleepModeSetup; } #endif /* RT3090 // */ } #endif /* RT30xx // */ }
static const struct firmware *rtmp_get_firmware(struct rt_rtmp_adapter *adapter) { const char *name; const struct firmware *fw = NULL; u8 min_version; struct device *dev; int err; if (adapter->firmware) return adapter->firmware; #ifdef RTMP_MAC_USB if (IS_RT3071(adapter)) { name = FIRMWARE_3071_FILENAME; min_version = FIRMWARE_3071_MIN_VERSION; } else if (IS_RT3070(adapter)) { name = FIRMWARE_3070_FILENAME; min_version = FIRMWARE_3070_MIN_VERSION; } else { name = FIRMWARE_2870_FILENAME; min_version = FIRMWARE_2870_MIN_VERSION; } dev = &((struct os_cookie *)adapter->OS_Cookie)->pUsb_Dev->dev; #else /* RTMP_MAC_PCI */ if (IS_RT3090(adapter) || IS_RT3390(adapter)) { name = FIRMWARE_3090_FILENAME; min_version = FIRMWARE_3090_MIN_VERSION; } else { name = FIRMWARE_2860_FILENAME; min_version = FIRMWARE_2860_MIN_VERSION; } dev = &((struct os_cookie *)adapter->OS_Cookie)->pci_dev->dev; #endif err = request_firmware(&fw, name, dev); if (err) { dev_err(dev, "firmware file %s request failed (%d)\n", name, err); return NULL; } if (fw->size < FIRMWAREIMAGE_LENGTH) { dev_err(dev, "firmware file %s size is invalid\n", name); goto invalid; } /* is it new enough? */ adapter->FirmwareVersion = fw->data[FIRMWAREIMAGE_LENGTH - 3]; if (adapter->FirmwareVersion < min_version) { dev_err(dev, "firmware file %s is too old;" " driver requires v%d or later\n", name, min_version); goto invalid; } /* is the internal CRC correct? */ if (crc_ccitt(0xffff, fw->data, FIRMWAREIMAGE_LENGTH - 2) != (fw->data[FIRMWAREIMAGE_LENGTH - 2] | (fw->data[FIRMWAREIMAGE_LENGTH - 1] << 8))) { dev_err(dev, "firmware file %s failed internal CRC\n", name); goto invalid; } adapter->firmware = fw; return fw; invalid: release_firmware(fw); return NULL; }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ VOID RT30xxReverseRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { #ifdef RT53xx if (IS_RT5390(pAd)) { UCHAR rfreg; RT30xxReadRFRegister(pAd, RF_R01, &rfreg); if (IS_RT5392(pAd)) { rfreg = ((rfreg & ~0x3F) | 0x3F); } else { rfreg = ((rfreg & ~0x0F) | 0x0F); // Enable rf_block_en, pll_en, rx0_en and tx0_en } RT30xxWriteRFRegister(pAd, RF_R01, rfreg); RT30xxReadRFRegister(pAd, RF_R06, &rfreg); if (IS_RT5390F(pAd) || IS_RT5392C(pAd)) { rfreg = ((rfreg & ~0xC0) | 0xC0); // vco_ic (VCO bias current control, 11: high) } else { rfreg = ((rfreg & ~0xC0) | 0x80); // vco_ic (VCO bias current control, 10: mid.) } RT30xxWriteRFRegister(pAd, RF_R06, rfreg); if (!IS_RT5392(pAd)) { RT30xxReadRFRegister(pAd, RF_R02, &rfreg); rfreg = ((rfreg & ~0x80) | 0x80); // rescal_en (initiate calibration) RT30xxWriteRFRegister(pAd, RF_R02, rfreg); } RT30xxReadRFRegister(pAd, RF_R22, &rfreg); rfreg = ((rfreg & ~0xE0) | 0x20); // cp_ic (reference current control, 001: 0.33 mA) RT30xxWriteRFRegister(pAd, RF_R22, rfreg); RT30xxReadRFRegister(pAd, RF_R42, &rfreg); rfreg = ((rfreg & ~0x40) | 0x40); // rx_ctb_en RT30xxWriteRFRegister(pAd, RF_R42, rfreg); RT30xxReadRFRegister(pAd, RF_R20, &rfreg); rfreg = ((rfreg & ~0x77) | 0x00); // ldo_rf_vc and ldo_pll_vc ( 111: +0.15) RT30xxWriteRFRegister(pAd, RF_R20, rfreg); RT30xxReadRFRegister(pAd, RF_R03, &rfreg); rfreg = ((rfreg & ~0x80) | 0x80); // vcocal_en (initiate VCO calibration (reset after completion)) RT30xxWriteRFRegister(pAd, RF_R03, rfreg); } else #endif // RT53xx // { // RF_BLOCK_en, RF R1 register Bit 0 to 1 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // VCO_IC, RF R7 register Bit 5 to 1 (VCO bias current control, 11: high) RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue |= 0x30; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1 RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue |= 0x0E; RT30xxWriteRFRegister(pAd, RF_R09, RFValue); // RX_CTB_en, RF R21 register Bit 7 to 1 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } } if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72 IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd) || IS_RT5390(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if ((!IS_RT3572(pAd)) && (!IS_RT3593(pAd)) && (!IS_RT5390(pAd)) && (!IS_RT3390(pAd)) && (!IS_RT3090(pAd))) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); if ((pAd->MACVersion & 0xffff) < 0x0211) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } // RT3071 version E has fixed this issue if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { // patch tx EVM issue temporarily RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } // else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd)) || (pAd->CommonCfg.PatchHWControl.field.LDOCfg == 1)) else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd) && !IS_RT5390(pAd))) { RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } if(IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, 0x80); }
/* ========================================================================== Description: Load RF sleep-mode setup ========================================================================== */ VOID RT30xxLoadRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { #ifdef RT53xx if (IS_RT5390(pAd)) { UCHAR rfreg; RT30xxReadRFRegister(pAd, RF_R01, &rfreg); rfreg = ((rfreg & ~0x01) | 0x00); // vco_en RT30xxWriteRFRegister(pAd, RF_R01, rfreg); RT30xxReadRFRegister(pAd, RF_R06, &rfreg); rfreg = ((rfreg & ~0xC0) | 0x00); // vco_ic (VCO bias current control, 00: off) RT30xxWriteRFRegister(pAd, RF_R06, rfreg); RT30xxReadRFRegister(pAd, RF_R22, &rfreg); rfreg = ((rfreg & ~0xE0) | 0x00); // cp_ic (reference current control, 000: 0.25 mA) RT30xxWriteRFRegister(pAd, RF_R22, rfreg); RT30xxReadRFRegister(pAd, RF_R42, &rfreg); rfreg = ((rfreg & ~0x40) | 0x00); // rx_ctb_en RT30xxWriteRFRegister(pAd, RF_R42, rfreg); /* RT30xxReadRFRegister(pAd, RF_R20, &rfreg); rfreg = ((rfreg & ~0x77) | 0x77); // ldo_pll_vc and ldo_rf_vc (111: -0.15) RT30xxWriteRFRegister(pAd, RF_R20, rfreg); */ } else #endif // RT53xx // { // RF_BLOCK_en. RF R1 register Bit 0 to 0 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue &= (~0x01); RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // VCO_IC, RF R7 register Bit 4 & Bit 5 to 0 RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue &= (~0x30); RT30xxWriteRFRegister(pAd, RF_R07, RFValue); // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue &= (~0x0E); RT30xxWriteRFRegister(pAd, RF_R09, RFValue); // RX_CTB_en, RF R21 register Bit 7 to 0 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x80); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } } // Don't touch LDO_CFG0 for 3090F & 3593, possibly the board is single power scheme if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72 IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT5390(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if (!IS_RT3572(pAd) && !IS_RT3390(pAd) && !IS_RT5390(pAd) && !IS_RT3090(pAd)) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); RFValue |= 0x77; RT30xxWriteRFRegister(pAd, RF_R27, RFValue); RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue |= 0x1D000000; RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } }
VOID NICInitRT3070RFRegisters(IN PRTMP_ADAPTER pAd) { INT i; UCHAR RFValue; /* Driver must read EEPROM to get RfIcType before initial RF registers Initialize RF register to default value */ if (IS_RT3070(pAd) || IS_RT3071(pAd)) { /* Init RF calibration Driver should toggle RF R30 bit7 before init RF registers */ UINT8 RfReg = 0; UINT32 data; RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); /* set default antenna as main */ if (pAd->RfIcType == RFIC_3020 || pAd->RfIcType == RFIC_2020) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); /* Initialize RF register to default value */ for (i = 0; i < NUM_RF_3020_REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RT3020_RFRegTable[i].Register, RT3020_RFRegTable[i].Value); } RT30xxWriteRFRegister(pAd, RF_R31, 0x14); /* add by johnli */ if (IS_RT3070(pAd)) { /* The DAC issue(LDO_CFG0) has been fixed in RT3070(F). The voltage raising patch is no longer needed for RT3070(F) */ if ((pAd->MACVersion & 0xffff) < 0x0201) { /* Update MAC 0x05D4 from 01xxxxxx to 0Dxxxxxx (voltage 1.2V to 1.35V) for RT3070 to improve yield rate */ RTUSBReadMACRegister(pAd, LDO_CFG0, &data); data = ((data & 0xF0FFFFFF) | 0x0D000000); RTUSBWriteMACRegister(pAd, LDO_CFG0, data); } } else if (IS_RT3071(pAd)) { /* Driver should set RF R6 bit6 on before init RF registers */ RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg); /* RT3071 version E has fixed this issue */ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily */ RTUSBReadMACRegister(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTUSBWriteMACRegister(pAd, LDO_CFG0, data); } else { RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } /* patch LNA_PE_G1 failed issue */ RTUSBReadMACRegister(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTUSBWriteMACRegister(pAd, GPIO_SWITCH, data); } /* For RF filter Calibration */ RTMPFilterCalibration(pAd); /* Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F). Raising RF voltage is no longer needed for RT3070(F) */ if ((IS_RT3070(pAd)) && ((pAd->MACVersion & 0xffff) < 0x0201)) { RT30xxWriteRFRegister(pAd, RF_R27, 0x3); } else if ((IS_RT3071(pAd)) && ((pAd->MACVersion & 0xffff) < 0x0211)) { RT30xxWriteRFRegister(pAd, RF_R27, 0x3); } /* set led open drain enable */ RTUSBReadMACRegister(pAd, OPT_14, &data); data |= 0x01; RTUSBWriteMACRegister(pAd, OPT_14, data); if (IS_RT3071(pAd)) { /* RF power sequence setup, load RF normal operation-mode setup */ RT30xxLoadRFNormalModeSetup(pAd); } else if (IS_RT3070(pAd)) { /* TX_LO1_en, RF R17 register Bit 3 to 0 */ RT30xxReadRFRegister(pAd, RF_R17, &RFValue); RFValue &= (~0x08); /* to fix rx long range issue */ if (pAd->NicConfig2.field.ExternalLNAForG == 0) { if ((IS_RT3071(pAd) && ((pAd->MACVersion & 0xffff) >= 0x0211)) || IS_RT3070(pAd)) { RFValue |= 0x20; } } /* set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h */ if (pAd->TxMixerGain24G >= 1) { RFValue &= (~0x7); /* clean bit [2:0] */ RFValue |= pAd->TxMixerGain24G; } RT30xxWriteRFRegister(pAd, RF_R17, RFValue); /* add by johnli, reset RF_R27 when interface down & up to fix throughput problem */ /* LDORF_VC, RF R27 register Bit 2 to 0 */ RT30xxReadRFRegister(pAd, RF_R27, &RFValue); /* TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F). Raising RF voltage is no longer needed for RT3070(F) */ if ((pAd->MACVersion & 0xffff) < 0x0201) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); /* end johnli */ } } }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ void RT30xxReverseRFSleepModeSetup(struct rt_rtmp_adapter *pAd) { u8 RFValue; u32 MACValue; #ifdef RTMP_MAC_USB if (!IS_RT3572(pAd)) #endif /* RTMP_MAC_USB // */ { /* RF_BLOCK_en, RF R1 register Bit 0 to 1 */ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1 */ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue |= 0x20; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1 */ RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue |= 0x0E; RT30xxWriteRFRegister(pAd, RF_R09, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 1 */ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72 */ IS_RT3572(pAd) || IS_RT3390(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { #ifdef RTMP_MAC_USB if (!IS_RT3572(pAd)) #endif /* RTMP_MAC_USB // */ { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); if ((pAd->MACVersion & 0xffff) < 0x0211) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } /* RT3071 version E has fixed this issue */ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily */ RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } else { RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, 0x80); }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ VOID RT30xxReverseRFSleepModeSetup( IN PRTMP_ADAPTER pAd, IN BOOLEAN FlgIsInitState) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { { /* RF_BLOCK_en, RF R1 register Bit 0 to 1*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1*/ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue |= 0x20; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1*/ RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue |= 0x0E; RT30xxWriteRFRegister(pAd, RF_R09, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 1*/ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } } if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72*/ IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if ((!IS_RT3572(pAd)) && (!IS_RT3593(pAd))) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); if ((pAd->MACVersion & 0xffff) < 0x0211) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } /* RT3071 version E has fixed this issue*/ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily*/ RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd))) { RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } if(IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, 0x80); }