static void __init wzrhpag300h_setup(void)
{
u8 *eeprom1 = (u8 *) KSEG1ADDR(0x1f051000);
u8 *eeprom2 = (u8 *) KSEG1ADDR(0x1f055000);
u8 *mac1 = eeprom1 + WZRHPAG300H_MAC_OFFSET;
u8 *mac2 = eeprom2 + WZRHPAG300H_MAC_OFFSET;
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 1);
ath79_register_mdio(0, ~(BIT(0) | BIT(4)));
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = BIT(4);
ath79_register_eth(0);
ath79_register_eth(1);
gpio_request_one(2, GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
ath79_register_usb();
ath79_register_leds_gpio(-1, ARRAY_SIZE(wzrhpag300h_leds_gpio),
wzrhpag300h_leds_gpio);
ath79_register_gpio_keys_polled(-1, WZRHPAG300H_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wzrhpag300h_gpio_keys),
wzrhpag300h_gpio_keys);
ath79_register_m25p80_multi(&wzrhpag300h_flash_data);
ap94_pci_init(eeprom1, mac1, eeprom2, mac2);
ap9x_pci_setup_wmac_led_pin(0, 1);
ap9x_pci_setup_wmac_led_pin(1, 5);
ap9x_pci_setup_wmac_leds(0, wzrhpag300h_wmac0_leds_gpio,
ARRAY_SIZE(wzrhpag300h_wmac0_leds_gpio));
ap9x_pci_setup_wmac_leds(1, wzrhpag300h_wmac1_leds_gpio,
ARRAY_SIZE(wzrhpag300h_wmac1_leds_gpio));
}
static inline void au1200_usb_init(void)
{
void __iomem *base =
(void __iomem *)KSEG1ADDR(AU1200_USB_CTL_PHYS_ADDR);
__raw_writel(USBCFG_INIT_AU1200, base + AU1200_USBCFG);
wmb();
udelay(1000);
}
static void prom_putchar_ar71xx(unsigned char ch)
{
void __iomem *base = (void __iomem *)(KSEG1ADDR(AR71XX_UART_BASE));
prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
__raw_writel(ch, base + UART_TX * 4);
prom_putchar_wait(base + UART_LSR * 4, BOTH_EMPTY, BOTH_EMPTY);
}
static void __init prom_init_cmdline(void)
{
int argc = fw_arg0;
char **argv = (char **) KSEG1ADDR(fw_arg1);
int i;
arcs_cmdline[0] = '\0';
for (i = 0; i < argc; i++) {
char *p = (char *) KSEG1ADDR(argv[i]);
if (CPHYSADDR(p) && *p) {
strlcat(arcs_cmdline, p, sizeof(arcs_cmdline));
strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline));
}
}
}
/******************************************************************************
* memory setup:
* Read the ATW regs and assume that any region with a memory controller base
* address of ZERO is Linux.
* Next, Calculate total memory size and assume that any memory left over that
* has not been mapped by the ATW's is Linux memory (HIGHMEM).
*****************************************************************************/
void __init plat_mem_setup(void)
{
int i;
memc_atw_regs *atws = (memc_atw_regs *)KSEG1ADDR(BCHP_MEMC_ATW_UBUS_0_REG_START);
addr_trans *linux_trans = NULL;
u32 memc_min = 0xffffffff;
u32 memc_max = 0;
u32 memsize;
for (i = 0; i < NUM_ATWS; i++)
{
addr_trans *att = &addr_trans_table[i];
if (atws->enable[i] & 1)
{
att->memc_base = atws->dest_addr[i];
att->ubus_base = atws->source_addr[i];
att->size = atws->size_mask[i] + 0x10000;
if (att->memc_base == 0)
{
linux_trans = att;
}
else
{
add_memory_region(att->memc_base,
att->size,
BOOT_MEM_RESERVED);
printk("Added NON Linux Memory Region %08x - %08x ubus %08x\n",
att->memc_base,
att->memc_base + att->size,
att->ubus_base);
if (att->memc_base < memc_min)
memc_min = att->memc_base;
}
if ((att->memc_base + att->size) > memc_max)
memc_max = att->memc_base + att->size;
}
else
{
memset(att, 0, sizeof(addr_trans));
}
}
BUG_ON(!linux_trans);
linux_trans->size = memc_min;
add_memory_region(linux_trans->memc_base, linux_trans->size, BOOT_MEM_RAM);
printk("Added Linux Memory Region %08x - %08x ubus %08x\n",
linux_trans->memc_base,
linux_trans->memc_base + linux_trans->size,
linux_trans->ubus_base);
memsize = ddr_mem_size();
if (memsize > memc_max)
{
u32 highmemsize = memsize - memc_max;
add_memory_region(HIGHMEM_START, highmemsize, BOOT_MEM_RAM);
printk("Added Linux Memory Region %08x - %08x ubus %08x\n",
HIGHMEM_START, HIGHMEM_START + highmemsize, HIGHMEM_START);
}
}
/* should be the first function */
void entry(unsigned long icache_size, unsigned long icache_lsize,
unsigned long dcache_size, unsigned long dcache_lsize,
unsigned long fw_arg0, unsigned long fw_arg1,
unsigned long fw_arg2, unsigned long fw_arg3)
{
CLzmaDec state;
ISzAlloc dummy;
ISeqInStream stream;
ELzmaStatus status;
unsigned int i; /* temp value */
unsigned int osize; /* uncompressed size */
dummy.Alloc = dummy_alloc;
dummy.Free = dummy_free;
stream.Read = read_bytes;
/* look for trx header, 32-bit data access */
for (data = ((unsigned char *)KSEG1ADDR(BCM4710_FLASH));
((struct trx_header *)data)->magic != TRX_MAGIC; data += 65536);
/* compressed kernel is in the partition 1 */
data += ((struct trx_header *)data)->offsets[1];
offset = 0;
/* read lzma stream header */
SeqInStream_Read(&stream, workspace, LZMA_PROPS_SIZE + 8);
/* read the lower half of uncompressed size in the header */
osize = (workspace[LZMA_PROPS_SIZE + 0]) +
(workspace[LZMA_PROPS_SIZE + 1] << 8) +
(workspace[LZMA_PROPS_SIZE + 2] << 16) +
(workspace[LZMA_PROPS_SIZE + 3] << 24);
LzmaDec_Construct(&state);
LzmaDec_AllocateProbs(&state, workspace, LZMA_PROPS_SIZE, &dummy);
state.dic = (unsigned char *)LOADADDR;
state.dicBufSize = osize;
/* decompress kernel */
LzmaDec_Init(&state);
do {
i = LZMA_REQUIRED_INPUT_MAX;
SeqInStream_Read(&stream, workspace, i);
if (LzmaDec_DecodeToDic(&state, osize, workspace, &i,
LZMA_FINISH_ANY, &status) != SZ_OK) {
/* something went wrong */
return;
}
} while (status == LZMA_STATUS_NEEDS_MORE_INPUT);
blast_dcache(dcache_size, dcache_lsize);
blast_icache(icache_size, icache_lsize);
/* jump to load address */
((void (*)(unsigned long, unsigned long, unsigned long,
unsigned long))LOADADDR)(fw_arg0, fw_arg1, fw_arg2, fw_arg3);
}
static void __init common_setup(bool dualband)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
ath79_register_m25p80(&wdr3500_flash_data);
if (dualband)
{
tplink_register_builtin_wmac1(WDR3500_WMAC_CALDATA_OFFSET, mac, -1);
}
ap9x_pci_setup_wmac_led_pin(0, 0);
tplink_register_ap91_wmac2(WDR3500_PCIE_CALDATA_OFFSET, mac, 2);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
/* LAN */
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
/* WAN */
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
/* GMAC0 is connected to the PHY4 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(4);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(4);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
if (dualband)
{
gpio_request_one(WDR3500_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
}
ath79_register_usb();
ath79_gpio_output_select(WDR3500_GPIO_LED_LAN1,
AR934X_GPIO_OUT_LED_LINK3);
ath79_gpio_output_select(WDR3500_GPIO_LED_LAN2,
AR934X_GPIO_OUT_LED_LINK2);
ath79_gpio_output_select(WDR3500_GPIO_LED_LAN3,
AR934X_GPIO_OUT_LED_LINK1);
ath79_gpio_output_select(WDR3500_GPIO_LED_LAN4,
AR934X_GPIO_OUT_LED_LINK0);
ath79_gpio_output_select(WDR3500_GPIO_LED_WAN,
AR934X_GPIO_OUT_LED_LINK4);
}
static void __init tl_wr1043nd_v2_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
ath79_register_m25p80(&wr1043nd_v2_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr1043_v2_leds_gpio),
tl_wr1043_v2_leds_gpio);
ath79_register_gpio_keys_polled(-1, TL_WR1043_V2_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr1043_v2_gpio_keys),
tl_wr1043_v2_gpio_keys);
ath79_register_wmac(art + TL_WR1043_V2_WMAC_CALDATA_OFFSET, mac);
mdiobus_register_board_info(wr1043nd_v2_mdio0_info,
ARRAY_SIZE(wr1043nd_v2_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_setup_qca955x_eth_cfg(QCA955X_ETH_CFG_RGMII_EN);
/* GMAC0 is connected to the RMGII interface */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x56000000;
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 1);
ath79_register_eth(0);
/* GMAC1 is connected to the SGMII interface */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_eth1_pll_data.pll_1000 = 0x03000101;
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
ath79_register_eth(1);
ath79_register_usb();
gpio_request_one(TL_WR1043_V2_GPIO_USB_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB power");
}
void dmac5_debug(void)
{
#ifdef SHARED_MEM_DEBUG
volatile uint32_t *d5_chcr = KSEG1ADDR(D5_CHCR);
volatile uint32_t *d5_qwc = KSEG1ADDR(D5_QWC);
volatile uint32_t *d5_madr = KSEG1ADDR(D5_MADR);
#endif
iop_prints("D5_CHCR 0x");
iop_printx(*d5_chcr);
iop_prints("\n");
iop_prints("D5_MADR 0x");
iop_printx(*d5_madr);
iop_prints("\n");
iop_prints("D5_QWC 0x");
iop_printx(*d5_qwc);
iop_prints("\n");
}
void *
osl_uncached(void *va)
{
#ifdef mips
return ((void*)KSEG1ADDR(va));
#else
return ((void*)va);
#endif
}
void __init ls1x_gmac_setup(void)
{
u32 x;
x = __raw_readl(LS1X_MUX_CTRL1);
x &= ~PHY_INTF_SELI;
#if defined(CONFIG_LS1X_GMAC0_RMII)
x |= 0x4 << PHY_INTF_SELI_SHIFT;
#endif
__raw_writel(x, LS1X_MUX_CTRL1);
x = __raw_readl(LS1X_MUX_CTRL0);
__raw_writel(x & (~GMAC_SHUT), LS1X_MUX_CTRL0);
#if defined(CONFIG_LS1X_GMAC0_RMII)
__raw_writel(0x400, (void __iomem *)KSEG1ADDR(LS1X_GMAC0_BASE + 0x14));
#endif
__raw_writel(0xe4b, (void __iomem *)KSEG1ADDR(LS1X_GMAC0_BASE + 0x10));
}
static void __init om2p_hs_setup(void)
{
u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
/* make lan / wan leds software controllable */
ath79_gpio_output_select(OM2P_GPIO_LED_LAN, AR934X_GPIO_OUT_GPIO);
ath79_gpio_output_select(OM2P_GPIO_LED_WAN, AR934X_GPIO_OUT_GPIO);
/* enable reset button */
ath79_gpio_output_select(OM2P_GPIO_BTN_RESET, AR934X_GPIO_OUT_GPIO);
ath79_gpio_function_enable(AR934X_GPIO_FUNC_JTAG_DISABLE);
om2p_leds_gpio[4].gpio = OM2P_GPIO_LED_WAN;
om2p_leds_gpio[5].gpio = OM2P_GPIO_LED_LAN;
ath79_register_m25p80(&om2p_lc_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
om2p_leds_gpio);
ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om2p_gpio_keys),
om2p_gpio_keys);
ath79_register_wmac(art, NULL);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
}
int amazon_se_switch_recv(struct eth_device *dev)
{
int length = 0;
int tmp;
amazon_se_rx_descriptor_t * rx_desc;
int anchor_num=0;
int i;
for (;;)
{
rx_desc = KSEG1ADDR(&rx_des_ring[rx_num]);
if ((rx_desc->status.field.C == 0) || (rx_desc->status.field.OWN == 1))
{
break;
}
length = rx_desc->status.field.DataLen;
if (length)
{
/*tmp=(int)KSEG1ADDR(NetRxPackets[rx_num]);
printf("%08x\n",tmp);
*/
NetReceive((void*)KSEG1ADDR(NetRxPackets[rx_num]), length - 4);
// serial_putc('*');
}
else
{
printf("Zero length!!!\n");
}
rx_desc->status.field.Sop=0;
rx_desc->status.field.Eop=0;
rx_desc->status.field.C=0;
rx_desc->status.field.DataLen=PKTSIZE_ALIGN;
rx_desc->status.field.OWN=1;
rx_num++;
if(rx_num==NUM_RX_DESC) rx_num=0;
}
return length;
}
static void __init dir825b1_setup(void)
{
u8 mac1[ETH_ALEN], mac2[ETH_ALEN];
dir825b1_read_ascii_mac(mac1, DIR825B1_MAC_LOCATION_0);
dir825b1_read_ascii_mac(mac2, DIR825B1_MAC_LOCATION_1);
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 2);
ath79_eth0_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.speed = SPEED_1000;
ath79_eth0_data.duplex = DUPLEX_FULL;
ath79_eth0_pll_data.pll_1000 = 0x11110000;
ath79_init_mac(ath79_eth1_data.mac_addr, mac1, 3);
ath79_eth1_data.mii_bus_dev = &dir825b1_rtl8366s_device.dev;
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth1_data.phy_mask = 0x10;
ath79_eth1_pll_data.pll_1000 = 0x11110000;
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_m25p80(&dir825b1_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir825b1_leds_gpio),
dir825b1_leds_gpio);
ath79_register_gpio_keys_polled(-1, DIR825B1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir825b1_gpio_keys),
dir825b1_gpio_keys);
ath79_register_usb();
platform_device_register(&dir825b1_rtl8366s_device);
ap9x_pci_setup_wmac_led_pin(0, 5);
ap9x_pci_setup_wmac_led_pin(1, 5);
ap94_pci_init((u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_0), mac1,
(u8 *) KSEG1ADDR(DIR825B1_CAL_LOCATION_1), mac2);
}
static void __init wdr4300_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *art = (u8 *) KSEG1ADDR(0x1fff0000);
u8 tmpmac[ETH_ALEN];
ath79_register_m25p80(&wdr4300_flash_data);
ath79_register_leds_gpio(-1, ARRAY_SIZE(wdr4300_leds_gpio),
wdr4300_leds_gpio);
ath79_register_gpio_keys_polled(-1, WDR4300_KEYS_POLL_INTERVAL,
ARRAY_SIZE(wdr4300_gpio_keys),
wdr4300_gpio_keys);
ath79_init_mac(tmpmac, mac, -1);
ath79_register_wmac(art + WDR4300_WMAC_CALDATA_OFFSET, tmpmac);
ath79_init_mac(tmpmac, mac, 0);
ap9x_pci_setup_wmac_led_pin(0, 0);
ap91_pci_init(art + WDR4300_PCIE_CALDATA_OFFSET, tmpmac);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0);
mdiobus_register_board_info(wdr4300_mdio0_info,
ARRAY_SIZE(wdr4300_mdio0_info));
ath79_register_mdio(0, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -2);
/* GMAC0 is connected to an AR8327N switch */
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
gpio_request_one(WDR4300_GPIO_USB1_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB1 power");
gpio_request_one(WDR4300_GPIO_USB2_POWER,
GPIOF_OUT_INIT_HIGH | GPIOF_EXPORT_DIR_FIXED,
"USB2 power");
ath79_register_usb();
}
void * __ioremap(phys_t phys_addr, phys_t size, unsigned long flags)
{
struct vm_struct * area;
unsigned long offset;
phys_t last_addr;
void * addr;
/* Don't allow wraparound or zero size */
last_addr = phys_addr + size - 1;
if (!size || last_addr < phys_addr)
return NULL;
/*
* Map uncached objects in the low 512mb of address space using KSEG1,
* otherwise map using page tables.
*/
if (IS_LOW512(phys_addr) && IS_LOW512(last_addr) &&
flags == _CACHE_UNCACHED)
return (void *) KSEG1ADDR(phys_addr);
/*
* Don't allow anybody to remap normal RAM that we're using..
*/
if (phys_addr < virt_to_phys(high_memory)) {
char *t_addr, *t_end;
struct page *page;
t_addr = __va(phys_addr);
t_end = t_addr + (size - 1);
for(page = virt_to_page(t_addr); page <= virt_to_page(t_end); page++)
if(!PageReserved(page))
return NULL;
}
/*
* Mappings have to be page-aligned
*/
offset = phys_addr & ~PAGE_MASK;
phys_addr &= PAGE_MASK;
size = PAGE_ALIGN(last_addr + 1) - phys_addr;
/*
* Ok, go for it..
*/
area = get_vm_area(size, VM_IOREMAP);
if (!area)
return NULL;
addr = area->addr;
if (remap_area_pages((unsigned long) addr, phys_addr, size, flags)) {
vunmap(addr);
return NULL;
}
return (void *) (offset + (char *)addr);
}
/*
* Finds a free channel, and binds the requested device to it.
* Returns the allocated channel number, or negative on error.
* Requests the DMA done IRQ if irqhandler != NULL.
*/
int request_au1000_dma(int dev_id, const char *dev_str,
irq_handler_t irqhandler,
unsigned long irqflags,
void *irq_dev_id)
{
struct dma_chan *chan;
const struct dma_dev *dev;
int i, ret;
#if defined(CONFIG_SOC_AU1100)
if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
return -EINVAL;
#else
if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
return -EINVAL;
#endif
for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++)
if (au1000_dma_table[i].dev_id < 0)
break;
if (i == NUM_AU1000_DMA_CHANNELS)
return -ENODEV;
chan = &au1000_dma_table[i];
if (dev_id >= DMA_NUM_DEV) {
dev_id -= DMA_NUM_DEV;
dev = &dma_dev_table_bank2[dev_id];
} else
dev = &dma_dev_table[dev_id];
if (irqhandler) {
chan->irq_dev = irq_dev_id;
ret = request_irq(chan->irq, irqhandler, irqflags, dev_str,
chan->irq_dev);
if (ret) {
chan->irq_dev = NULL;
return ret;
}
} else {
chan->irq_dev = NULL;
}
/* fill it in */
chan->io = KSEG1ADDR(AU1000_DMA_PHYS_ADDR) + i * DMA_CHANNEL_LEN;
chan->dev_id = dev_id;
chan->dev_str = dev_str;
chan->fifo_addr = dev->fifo_addr;
chan->mode = dev->dma_mode;
/* initialize the channel before returning */
init_dma(i);
return i;
}
static void qihoo_c301_get_mac(const char *name, char *mac)
{
u8 *nvram = (u8 *) KSEG1ADDR(QIHOO_C301_NVRAM_ADDR);
int err;
err = ath79_nvram_parse_mac_addr(nvram, QIHOO_C301_NVRAM_SIZE,
name, mac);
if (err)
pr_err("no MAC address found for %s\n", name);
}
static void prom_putchar_ar933x(unsigned char ch)
{
void __iomem *base = (void __iomem *)(KSEG1ADDR(AR933X_UART_BASE));
prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
AR933X_UART_DATA_TX_CSR);
__raw_writel(AR933X_UART_DATA_TX_CSR | ch, base + AR933X_UART_DATA_REG);
prom_putchar_wait(base + AR933X_UART_DATA_REG, AR933X_UART_DATA_TX_CSR,
AR933X_UART_DATA_TX_CSR);
}
static void __init ubnt_airrouter_setup(void)
{
u8 *mac1 = (u8 *) KSEG1ADDR(0x1fff0000);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ar71xx_add_device_m25p80(NULL);
ar71xx_add_device_mdio(0, ~UBNT_M_WAN_PHYMASK);
ar71xx_init_mac(ar71xx_eth0_data.mac_addr, mac1, 0);
ubnt_init_secondary_mac(mac1);
ar71xx_add_device_eth(1);
ar71xx_add_device_eth(0);
ar71xx_add_device_usb();
ap91_pci_init(ee, NULL);
ar71xx_add_device_leds_gpio(-1, ARRAY_SIZE(ubnt_airrouter_leds_gpio),
ubnt_airrouter_leds_gpio);
}
static void __init om2p_lc_setup(void)
{
u8 *mac1 = (u8 *)KSEG1ADDR(0x1ffc0000);
u8 *mac2 = (u8 *)KSEG1ADDR(0x1ffc0000 + ETH_ALEN);
u8 *art = (u8 *)KSEG1ADDR(0x1ffc1000);
u32 t;
ath79_gpio_function_disable(AR933X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR933X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
t |= AR933X_BOOTSTRAP_MDIO_GPIO_EN;
ath79_reset_wr(AR933X_RESET_REG_BOOTSTRAP, t);
ath79_register_m25p80(&om2p_lc_flash_data);
om2p_leds_gpio[0].gpio = OM2P_LC_GPIO_LED_POWER;
om2p_leds_gpio[1].gpio = OM2P_LC_GPIO_LED_RED;
om2p_leds_gpio[2].gpio = OM2P_LC_GPIO_LED_YELLOW;
om2p_leds_gpio[3].gpio = OM2P_LC_GPIO_LED_GREEN;
om2p_leds_gpio[4].gpio = OM2P_LC_GPIO_LED_LAN;
om2p_leds_gpio[5].gpio = OM2P_LC_GPIO_LED_WAN;
ath79_register_leds_gpio(-1, ARRAY_SIZE(om2p_leds_gpio),
om2p_leds_gpio);
om2p_gpio_keys[0].gpio = OM2P_LC_GPIO_BTN_RESET;
ath79_register_gpio_keys_polled(-1, OM2P_KEYS_POLL_INTERVAL,
ARRAY_SIZE(om2p_gpio_keys),
om2p_gpio_keys);
ath79_init_mac(ath79_eth0_data.mac_addr, mac1, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac2, 0);
ath79_register_mdio(0, 0x0);
ath79_register_eth(0);
ath79_register_eth(1);
ath79_register_wmac(art, NULL);
}
void __init plat_setup(void)
{
extern void brcm_irq_setup(void);
extern int panic_timeout;
irq_setup = brcm_irq_setup;
#ifdef CONFIG_MIPS_BRCM
#if defined( CONFIG_MIPS_BCM7038A0 )
set_io_port_base(0xe0000000); /* start of PCI IO space. */
#elif defined( CONFIG_MIPS_BCM7038B0 ) || defined( CONFIG_MIPS_BCM7038C0 ) \
|| defined( CONFIG_MIPS_BCM7400 ) || defined( CONFIG_MIPS_BCM7401 ) \
|| defined( CONFIG_MIPS_BCM3560 )
set_io_port_base(0xf0000000); /* start of PCI IO space. */
#elif defined( CONFIG_MIPS_BCM7329 )
set_io_port_base(KSEG1ADDR(0x1af90000));
#elif defined ( CONFIG_BCM93730 )
set_io_port_base(KSEG1ADDR(0x13000000));
#else
set_io_port_base(0);
#endif
#endif
_machine_restart = brcm_machine_restart;
_machine_halt = brcm_machine_halt;
_machine_power_off = brcm_machine_power_off;
board_time_init = brcm_time_init;
board_timer_setup = brcm_timer_setup;
panic_timeout = 180;
#ifdef CONFIG_PC_KEYB
kbd_ops = &brcm_kbd_ops;
#endif
#ifdef CONFIG_VT
conswitchp = &dummy_con;
#endif
}
static void mynet_n750_get_mac(const char *name, char *mac)
{
u8 *nvram = (u8 *) KSEG1ADDR(MYNET_N750_NVRAM_ADDR);
int err;
err = ath79_nvram_parse_mac_addr(nvram, MYNET_N750_NVRAM_SIZE,
name, mac);
if (err)
pr_err("no MAC address found for %s\n", name);
}
static int __init rb2011_setup(u32 flags)
{
const struct rb_info *info;
char buf[64];
info = rb_init_info((void *) KSEG1ADDR(0x1f000000), 0x10000);
if (!info)
return -ENODEV;
scnprintf(buf, sizeof(buf), "Mikrotik RouterBOARD %s",
(info->board_name) ? info->board_name : "");
mips_set_machine_name(buf);
rb2011_init_partitions(info);
ath79_register_m25p80(&rb2011_spi_flash_data);
rb2011_nand_init();
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_RGMII_GMAC0 |
AR934X_ETH_CFG_SW_ONLY_MODE);
ath79_register_mdio(1, 0x0);
ath79_register_mdio(0, 0x0);
mdiobus_register_board_info(rb2011_mdio0_info,
ARRAY_SIZE(rb2011_mdio0_info));
/* GMAC0 is connected to an ar8327 switch */
ath79_init_mac(ath79_eth0_data.mac_addr, ath79_mac_base, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_RGMII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio0_device.dev;
ath79_eth0_pll_data.pll_1000 = 0x06000000;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 5);
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_eth1_data.speed = SPEED_1000;
ath79_eth1_data.duplex = DUPLEX_FULL;
ath79_register_eth(1);
if (flags & RB2011_FLAG_SFP)
rb2011_sfp_init();
if (flags & RB2011_FLAG_WLAN)
rb2011_wlan_init();
if (flags & RB2011_FLAG_USB)
ath79_register_usb();
return 0;
}
static void __init tl_wr841n_v8_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_leds_gpio(-1, ARRAY_SIZE(tl_wr841n_v8_leds_gpio),
tl_wr841n_v8_leds_gpio);
ath79_register_gpio_keys_polled(1, TL_WR841NV8_KEYS_POLL_INTERVAL,
ARRAY_SIZE(tl_wr841n_v8_gpio_keys),
tl_wr841n_v8_gpio_keys);
/* enable power for the USB port */
gpio_request(TL_WR841NV8_GPIO_USB_POWER, "USB power");
gpio_direction_input(TL_WR841NV8_GPIO_USB_POWER);
ath79_register_usb();
/* END for the USB port */
ath79_register_m25p80(&tl_wr841n_v8_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, -1);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 0);
/* GMAC0 is connected to the PHY0 of the internal switch */
ath79_switch_data.phy4_mii_en = 1;
ath79_switch_data.phy_poll_mask = BIT(0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
/* GMAC1 is connected to the internal switch */
ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_GMII;
ath79_register_eth(1);
ath79_register_wmac(ee, mac);
}
static void __init dir_600_a1_setup(void)
{
const char *nvram = (char *) KSEG1ADDR(DIR_600_A1_NVRAM_ADDR);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
u8 mac_buff[6];
u8 *mac = NULL;
if (ath79_nvram_parse_mac_addr(nvram, DIR_600_A1_NVRAM_SIZE,
"lan_mac=", mac_buff) == 0) {
ath79_init_mac(ath79_eth0_data.mac_addr, mac_buff, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac_buff, 1);
mac = mac_buff;
}
ath79_register_m25p80(NULL);
ath79_gpio_function_disable(AR724X_GPIO_FUNC_ETH_SWITCH_LED0_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED1_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED2_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED3_EN |
AR724X_GPIO_FUNC_ETH_SWITCH_LED4_EN);
ath79_register_leds_gpio(-1, ARRAY_SIZE(dir_600_a1_leds_gpio),
dir_600_a1_leds_gpio);
ath79_register_gpio_keys_polled(-1, DIR_600_A1_KEYS_POLL_INTERVAL,
ARRAY_SIZE(dir_600_a1_gpio_keys),
dir_600_a1_gpio_keys);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_init_mac(ath79_eth1_data.mac_addr, mac, 1);
ath79_register_mdio(0, 0x0);
/* LAN ports */
ath79_register_eth(1);
/* WAN port */
ath79_register_eth(0);
ap91_pci_init(ee, mac);
}
void __init bcsr_init(unsigned long bcsr1_phys, unsigned long bcsr2_phys)
{
int i;
bcsr1_phys = KSEG1ADDR(CPHYSADDR(bcsr1_phys));
bcsr2_phys = KSEG1ADDR(CPHYSADDR(bcsr2_phys));
bcsr_virt = (void __iomem *)bcsr1_phys;
for (i = 0; i < BCSR_CNT; i++) {
if (i >= BCSR_HEXLEDS)
bcsr_regs[i].raddr = (void __iomem *)bcsr2_phys +
(0x04 * (i - BCSR_HEXLEDS));
else
bcsr_regs[i].raddr = (void __iomem *)bcsr1_phys +
(0x04 * i);
spin_lock_init(&bcsr_regs[i].lock);
}
}
/* should be the first function */
void entry(unsigned long icache_size, unsigned long icache_lsize,
unsigned long dcache_size, unsigned long dcache_lsize)
{
unsigned int i; /* temp value */
unsigned int lc; /* literal context bits */
unsigned int lp; /* literal pos state bits */
unsigned int pb; /* pos state bits */
unsigned int osize; /* uncompressed size */
ILzmaInCallback callback;
callback.Read = read_byte;
/* look for trx header, 32-bit data access */
for (data = ((unsigned char *) KSEG1ADDR(BCM4710_FLASH));
((struct trx_header *)data)->magic != TRX_MAGIC; data += 65536);
/* compressed kernel is in the partition 0 or 1 */
if (((struct trx_header *)data)->offsets[1] > 65536)
data += ((struct trx_header *)data)->offsets[0];
else
data += ((struct trx_header *)data)->offsets[1];
offset = 0;
/* lzma args */
i = get_byte();
lc = i % 9, i = i / 9;
lp = i % 5, pb = i / 5;
/* skip rest of the LZMA coder property */
for (i = 0; i < 4; i++)
get_byte();
/* read the lower half of uncompressed size in the header */
osize = ((unsigned int)get_byte()) +
((unsigned int)get_byte() << 8) +
((unsigned int)get_byte() << 16) +
((unsigned int)get_byte() << 24);
/* skip rest of the header (upper half of uncompressed size) */
for (i = 0; i < 4; i++)
get_byte();
/* decompress kernel */
if (LzmaDecode(workspace, ~0, lc, lp, pb, &callback,
(unsigned char*)LOADADDR, osize, &i) == LZMA_RESULT_OK)
{
blast_dcache(dcache_size, dcache_lsize);
blast_icache(icache_size, icache_lsize);
/* Jump to load address */
((void (*)(void)) LOADADDR)();
}
}
static void __init tl_ap123_setup(void)
{
u8 *mac = (u8 *) KSEG1ADDR(0x1f01fc00);
u8 *ee = (u8 *) KSEG1ADDR(0x1fff1000);
ath79_register_m25p80(&tl_wax50re_flash_data);
ath79_setup_ar934x_eth_cfg(AR934X_ETH_CFG_SW_PHY_SWAP);
ath79_register_mdio(1, 0x0);
ath79_init_mac(ath79_eth0_data.mac_addr, mac, 0);
ath79_eth0_data.phy_if_mode = PHY_INTERFACE_MODE_MII;
ath79_eth0_data.phy_mask = BIT(0);
ath79_eth0_data.mii_bus_dev = &ath79_mdio1_device.dev;
ath79_register_eth(0);
ath79_register_wmac(ee, mac);
}
static void tew673gru_read_ascii_mac(u8 *dest, unsigned int src_addr)
{
int ret;
u8 *src = (u8 *)KSEG1ADDR(src_addr);
ret = sscanf(src, "%02hhx:%02hhx:%02hhx:%02hhx:%02hhx:%02hhx",
&dest[0], &dest[1], &dest[2],
&dest[3], &dest[4], &dest[5]);
if (ret != ETH_ALEN) memset(dest, 0, ETH_ALEN);
}
