static void get_addr_props(phandle_t node, uint32_t *addrp, uint32_t *sizep, int *pcip) { char type[64]; uint32_t addr, size; int pci, res; res = OF_getencprop(node, "#address-cells", &addr, sizeof(addr)); if (res == -1) addr = 2; res = OF_getencprop(node, "#size-cells", &size, sizeof(size)); if (res == -1) size = 1; pci = 0; if (addr == 3 && size == 2) { res = OF_getprop(node, "device_type", type, sizeof(type)); if (res != -1) { type[sizeof(type) - 1] = '\0'; pci = (strcmp(type, "pci") == 0) ? 1 : 0; } } if (addrp != NULL) *addrp = addr; if (sizep != NULL) *sizep = size; if (pcip != NULL) *pcip = pci; }
static int sdhci_fdt_probe(device_t dev) { struct sdhci_fdt_softc *sc = device_get_softc(dev); phandle_t node; pcell_t cid; sc->quirks = 0; sc->num_slots = 1; sc->max_clk = 0; if (!ofw_bus_status_okay(dev)) return (ENXIO); if (ofw_bus_is_compatible(dev, "sdhci_generic")) { device_set_desc(dev, "generic fdt SDHCI controller"); } else if (ofw_bus_is_compatible(dev, "xlnx,zy7_sdhci")) { sc->quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK; device_set_desc(dev, "Zynq-7000 generic fdt SDHCI controller"); } else return (ENXIO); node = ofw_bus_get_node(dev); /* Allow dts to patch quirks, slots, and max-frequency. */ if ((OF_getencprop(node, "quirks", &cid, sizeof(cid))) > 0) sc->quirks = cid; if ((OF_getencprop(node, "num-slots", &cid, sizeof(cid))) > 0) sc->num_slots = cid; if ((OF_getencprop(node, "max-frequency", &cid, sizeof(cid))) > 0) sc->max_clk = cid; return (0); }
int ofw_pci_nranges(phandle_t node, struct ofw_pci_cell_info *info) { ssize_t nbase_ranges; if (info == NULL) return (-1); info->host_address_cells = 1; info->size_cells = 2; info->pci_address_cell = 3; OF_getencprop(OF_parent(node), "#address-cells", &(info->host_address_cells), sizeof(info->host_address_cells)); OF_getencprop(node, "#address-cells", &(info->pci_address_cell), sizeof(info->pci_address_cell)); OF_getencprop(node, "#size-cells", &(info->size_cells), sizeof(info->size_cells)); nbase_ranges = OF_getproplen(node, "ranges"); if (nbase_ranges <= 0) return (-1); return (nbase_ranges / sizeof(cell_t) / (info->pci_address_cell + info->host_address_cells + info->size_cells)); }
static int aw_fdt_configure_pins(device_t dev, phandle_t cfgxref) { struct a10_gpio_softc *sc; phandle_t node; const char **pinlist = NULL; char *pin_function = NULL; uint32_t pin_drive, pin_pull; int pins_nb, pin_num, pin_func, i, ret; sc = device_get_softc(dev); node = OF_node_from_xref(cfgxref); ret = 0; /* Getting all prop for configuring pins */ pins_nb = ofw_bus_string_list_to_array(node, "allwinner,pins", &pinlist); if (pins_nb <= 0) return (ENOENT); if (OF_getprop_alloc(node, "allwinner,function", sizeof(*pin_function), (void **)&pin_function) == -1) { ret = ENOENT; goto out; } if (OF_getencprop(node, "allwinner,drive", &pin_drive, sizeof(pin_drive)) == -1) { ret = ENOENT; goto out; } if (OF_getencprop(node, "allwinner,pull", &pin_pull, sizeof(pin_pull)) == -1) { ret = ENOENT; goto out; } /* Configure each pin to the correct function, drive and pull */ for (i = 0; i < pins_nb; i++) { pin_num = aw_find_pinnum_by_name(sc, pinlist[i]); if (pin_num == -1) { ret = ENOENT; goto out; } pin_func = aw_find_pin_func(sc, pin_num, pin_function); if (pin_func == -1) { ret = ENOENT; goto out; } A10_GPIO_LOCK(sc); a10_gpio_set_function(sc, pin_num, pin_func); a10_gpio_set_drv(sc, pin_num, pin_drive); a10_gpio_set_pud(sc, pin_num, pin_pull); A10_GPIO_UNLOCK(sc); } out: free(pinlist, M_OFWPROP); free(pin_function, M_OFWPROP); return (ret); }
int opal_check(void) { phandle_t opal; cell_t val[2]; if (opal_initialized) return (0); opal = OF_finddevice("/ibm,opal"); if (opal == -1) return (ENOENT); if (!OF_hasprop(opal, "opal-base-address") || !OF_hasprop(opal, "opal-entry-address")) return (ENOENT); OF_getencprop(opal, "opal-base-address", val, sizeof(val)); opal_data = ((uint64_t)val[0] << 32) | val[1]; OF_getencprop(opal, "opal-entry-address", val, sizeof(val)); opal_entrypoint = ((uint64_t)val[0] << 32) | val[1]; opal_msr = mfmsr() & ~(PSL_EE | PSL_IR | PSL_DR | PSL_SE); opal_initialized = 1; return (0); }
static int ksz9021_load_values(struct mii_softc *sc, phandle_t node, uint32_t reg, char *field1, char *field2, char *field3, char *field4) { pcell_t dts_value[1]; int len; int val; val = 0; if ((len = OF_getproplen(node, field1)) > 0) { OF_getencprop(node, field1, dts_value, len); val = PS_TO_REG(dts_value[0]); } if ((len = OF_getproplen(node, field2)) > 0) { OF_getencprop(node, field2, dts_value, len); val |= PS_TO_REG(dts_value[0]) << 4; } if ((len = OF_getproplen(node, field3)) > 0) { OF_getencprop(node, field3, dts_value, len); val |= PS_TO_REG(dts_value[0]) << 8; } if ((len = OF_getproplen(node, field4)) > 0) { OF_getencprop(node, field4, dts_value, len); val |= PS_TO_REG(dts_value[0]) << 12; } micphy_write(sc, reg, val); return (0); }
static int parse_dts(struct ckb_softc *sc) { phandle_t node; pcell_t dts_value; pcell_t *keymap; int len, ret; const char *keymap_prop = NULL; if ((node = ofw_bus_get_node(sc->dev)) == -1) return (ENXIO); if ((len = OF_getproplen(node, "google,key-rows")) <= 0) return (ENXIO); OF_getencprop(node, "google,key-rows", &dts_value, len); sc->rows = dts_value; if ((len = OF_getproplen(node, "google,key-columns")) <= 0) return (ENXIO); OF_getencprop(node, "google,key-columns", &dts_value, len); sc->cols = dts_value; if ((len = OF_getproplen(node, "freebsd,intr-gpio")) <= 0) return (ENXIO); OF_getencprop(node, "freebsd,intr-gpio", &dts_value, len); sc->gpio = dts_value; if (OF_hasprop(node, "freebsd,keymap")) { keymap_prop = "freebsd,keymap"; device_printf(sc->dev, "using FreeBSD-specific keymap from FDT\n"); } else if (OF_hasprop(node, "linux,keymap")) { keymap_prop = "linux,keymap"; device_printf(sc->dev, "using Linux keymap from FDT\n"); } else { device_printf(sc->dev, "using built-in keymap\n"); } if (keymap_prop != NULL) { if ((ret = read_keymap(node, keymap_prop, &keymap, &len))) { device_printf(sc->dev, "failed to read keymap from FDT: %d\n", ret); return (ret); } ret = parse_keymap(sc, keymap, len); free(keymap, M_DEVBUF); if (ret) { return (ret); } } else { if ((ret = parse_keymap(sc, default_keymap, KEYMAP_LEN))) { return (ret); } } if ((sc->rows == 0) || (sc->cols == 0) || (sc->gpio == 0)) return (ENXIO); return (0); }
static int ofw_spibus_attach(device_t dev) { struct spibus_softc *sc = device_get_softc(dev); struct ofw_spibus_devinfo *dinfo; phandle_t child; pcell_t clock, paddr; device_t childdev; sc->dev = dev; bus_generic_probe(dev); bus_enumerate_hinted_children(dev); /* * Attach those children represented in the device tree. */ for (child = OF_child(ofw_bus_get_node(dev)); child != 0; child = OF_peer(child)) { /* * Try to get the CS number first from the spi-chipselect * property, then try the reg property. */ if (OF_getencprop(child, "spi-chipselect", &paddr, sizeof(paddr)) == -1) { if (OF_getencprop(child, "reg", &paddr, sizeof(paddr)) == -1) continue; } /* * Get the maximum clock frequency for device, zero means * use the default bus speed. */ if (OF_getencprop(child, "spi-max-frequency", &clock, sizeof(clock)) == -1) clock = 0; /* * Now set up the SPI and OFW bus layer devinfo and add it * to the bus. */ dinfo = malloc(sizeof(struct ofw_spibus_devinfo), M_DEVBUF, M_NOWAIT | M_ZERO); if (dinfo == NULL) continue; dinfo->opd_dinfo.cs = paddr; dinfo->opd_dinfo.clock = clock; if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) != 0) { free(dinfo, M_DEVBUF); continue; } childdev = device_add_child(dev, NULL, -1); device_set_ivars(childdev, dinfo); } return (bus_generic_attach(dev)); }
static int ofwbus_attach(device_t dev) { struct ofwbus_devinfo *ndi; struct ofwbus_softc *sc; device_t cdev; phandle_t node; sc = device_get_softc(dev); node = OF_peer(0); /* * If no Open Firmware, bail early */ if (node == -1) return (ENXIO); sc->sc_intr_rman.rm_type = RMAN_ARRAY; sc->sc_intr_rman.rm_descr = "Interrupts"; sc->sc_mem_rman.rm_type = RMAN_ARRAY; sc->sc_mem_rman.rm_descr = "Device Memory"; if (rman_init(&sc->sc_intr_rman) != 0 || rman_init(&sc->sc_mem_rman) != 0 || rman_manage_region(&sc->sc_intr_rman, 0, ~0) != 0 || rman_manage_region(&sc->sc_mem_rman, 0, BUS_SPACE_MAXADDR) != 0) panic("%s: failed to set up rmans.", __func__); /* * Allow devices to identify. */ bus_generic_probe(dev); /* * Some important numbers */ sc->acells = 2; OF_getencprop(node, "#address-cells", &sc->acells, sizeof(sc->acells)); sc->scells = 1; OF_getencprop(node, "#size-cells", &sc->scells, sizeof(sc->scells)); /* * Now walk the OFW tree and attach top-level devices. */ for (node = OF_child(node); node > 0; node = OF_peer(node)) { if ((ndi = ofwbus_setup_dinfo(dev, node)) == NULL) continue; cdev = device_add_child(dev, NULL, -1); if (cdev == NULL) { device_printf(dev, "<%s>: device_add_child failed\n", ndi->ndi_obdinfo.obd_name); ofwbus_destroy_dinfo(ndi); continue; } device_set_ivars(cdev, ndi); } return (bus_generic_attach(dev)); }
static void get_addr_props(phandle_t node, uint32_t *addrp, uint32_t *sizep) { *addrp = 2; *sizep = 1; OF_getencprop(node, "#address-cells", addrp, sizeof(*addrp)); OF_getencprop(node, "#size-cells", sizep, sizeof(*sizep)); }
/* * Bus capability support for GICv3. * Collects and configures device informations and finally * adds ITS device as a child of GICv3 in Newbus hierarchy. */ static int gic_v3_ofw_bus_attach(device_t dev) { struct gic_v3_ofw_devinfo *di; device_t child; phandle_t parent, node; pcell_t addr_cells, size_cells; parent = ofw_bus_get_node(dev); if (parent > 0) { addr_cells = 2; OF_getencprop(parent, "#address-cells", &addr_cells, sizeof(addr_cells)); size_cells = 2; OF_getencprop(parent, "#size-cells", &size_cells, sizeof(size_cells)); /* Iterate through all GIC subordinates */ for (node = OF_child(parent); node > 0; node = OF_peer(node)) { /* Allocate and populate devinfo. */ di = malloc(sizeof(*di), M_GIC_V3, M_WAITOK | M_ZERO); if (ofw_bus_gen_setup_devinfo(&di->di_dinfo, node)) { if (bootverbose) { device_printf(dev, "Could not set up devinfo for ITS\n"); } free(di, M_GIC_V3); continue; } /* Initialize and populate resource list. */ resource_list_init(&di->di_rl); ofw_bus_reg_to_rl(dev, node, addr_cells, size_cells, &di->di_rl); /* Should not have any interrupts, so don't add any */ /* Add newbus device for this FDT node */ child = device_add_child(dev, NULL, -1); if (!child) { if (bootverbose) { device_printf(dev, "Could not add child: %s\n", di->di_dinfo.obd_name); } resource_list_free(&di->di_rl); ofw_bus_gen_destroy_devinfo(&di->di_dinfo); free(di, M_GIC_V3); continue; } device_set_ivars(child, di); } } return (bus_generic_attach(dev)); }
static int opalflash_attach(device_t dev) { struct opalflash_softc *sc; phandle_t node; cell_t flash_blocksize, opal_id; uint32_t regs[2]; sc = device_get_softc(dev); sc->sc_dev = dev; node = ofw_bus_get_node(dev); OF_getencprop(node, "ibm,opal-id", &opal_id, sizeof(opal_id)); sc->sc_opal_id = opal_id; if (OF_getencprop(node, "ibm,flash-block-size", &flash_blocksize, sizeof(flash_blocksize)) < 0) { device_printf(dev, "Cannot determine flash block size.\n"); return (ENXIO); } if (!OF_hasprop(node, "no-erase")) sc->sc_erase = true; OPALFLASH_LOCK_INIT(sc); if (OF_getencprop(node, "reg", regs, sizeof(regs)) < 0) { device_printf(dev, "Unable to get flash size.\n"); return (ENXIO); } sc->sc_disk = disk_alloc(); sc->sc_disk->d_name = "opalflash"; sc->sc_disk->d_open = opalflash_open; sc->sc_disk->d_close = opalflash_close; sc->sc_disk->d_strategy = opalflash_strategy; sc->sc_disk->d_ioctl = opalflash_ioctl; sc->sc_disk->d_getattr = opalflash_getattr; sc->sc_disk->d_drv1 = sc; sc->sc_disk->d_maxsize = DFLTPHYS; sc->sc_disk->d_mediasize = regs[1]; sc->sc_disk->d_unit = device_get_unit(sc->sc_dev); sc->sc_disk->d_sectorsize = FLASH_BLOCKSIZE; sc->sc_disk->d_stripesize = flash_blocksize; sc->sc_disk->d_dump = NULL; disk_create(sc->sc_disk, DISK_VERSION); bioq_init(&sc->sc_bio_queue); kproc_create(&opalflash_task, sc, &sc->sc_p, 0, 0, "task: OPAL Flash"); return (0); }
static int ofw_iicbus_attach(device_t dev) { struct iicbus_softc *sc = IICBUS_SOFTC(dev); struct ofw_iicbus_devinfo *dinfo; phandle_t child; pcell_t paddr; device_t childdev; sc->dev = dev; mtx_init(&sc->lock, "iicbus", NULL, MTX_DEF); iicbus_reset(dev, IIC_FASTEST, 0, NULL); bus_generic_probe(dev); bus_enumerate_hinted_children(dev); /* * Attach those children represented in the device tree. */ for (child = OF_child(ofw_bus_get_node(dev)); child != 0; child = OF_peer(child)) { /* * Try to get the I2C address first from the i2c-address * property, then try the reg property. It moves around * on different systems. */ if (OF_getencprop(child, "i2c-address", &paddr, sizeof(paddr)) == -1) if (OF_getencprop(child, "reg", &paddr, sizeof(paddr)) == -1) continue; /* * Now set up the I2C and OFW bus layer devinfo and add it * to the bus. */ dinfo = malloc(sizeof(struct ofw_iicbus_devinfo), M_DEVBUF, M_NOWAIT | M_ZERO); if (dinfo == NULL) continue; dinfo->opd_dinfo.addr = paddr; if (ofw_bus_gen_setup_devinfo(&dinfo->opd_obdinfo, child) != 0) { free(dinfo, M_DEVBUF); continue; } childdev = device_add_child(dev, NULL, -1); device_set_ivars(childdev, dinfo); } return (bus_generic_attach(dev)); }
int ofw_bus_msimap(phandle_t node, uint16_t pci_rid, phandle_t *msi_parent, uint32_t *msi_rid) { pcell_t *map, mask, msi_base, rid_base, rid_length; ssize_t len; uint32_t masked_rid, rid; int err, i; /* TODO: This should be OF_searchprop_alloc if we had it */ len = OF_getencprop_alloc(node, "msi-map", sizeof(*map), (void **)&map); if (len < 0) { if (msi_parent != NULL) { *msi_parent = 0; OF_getencprop(node, "msi-parent", msi_parent, sizeof(*msi_parent)); } if (msi_rid != NULL) *msi_rid = pci_rid; return (0); } err = ENOENT; rid = 0; mask = 0xffffffff; OF_getencprop(node, "msi-map-mask", &mask, sizeof(mask)); masked_rid = pci_rid & mask; for (i = 0; i < len; i += 4) { rid_base = map[i + 0]; rid_length = map[i + 3]; if (masked_rid < rid_base || masked_rid >= (rid_base + rid_length)) continue; msi_base = map[i + 2]; if (msi_parent != NULL) *msi_parent = map[i + 1]; if (msi_rid != NULL) *msi_rid = masked_rid - rid_base + msi_base; err = 0; break; } free(map, M_OFWPROP); return (err); }
static int simplebus_attach(device_t dev) { struct simplebus_softc *sc; struct simplebus_devinfo *di; phandle_t node; device_t cdev; node = ofw_bus_get_node(dev); sc = device_get_softc(dev); sc->dev = dev; sc->node = node; /* * Some important numbers */ sc->acells = 2; OF_getencprop(node, "#address-cells", &sc->acells, sizeof(sc->acells)); sc->scells = 1; OF_getencprop(node, "#size-cells", &sc->scells, sizeof(sc->scells)); if (simplebus_fill_ranges(node, sc) < 0) { device_printf(dev, "could not get ranges\n"); return (ENXIO); } /* * In principle, simplebus could have an interrupt map, but ignore that * for now */ for (node = OF_child(node); node > 0; node = OF_peer(node)) { if ((di = simplebus_setup_dinfo(dev, node)) == NULL) continue; cdev = device_add_child(dev, NULL, -1); if (cdev == NULL) { device_printf(dev, "<%s>: device_add_child failed\n", di->obdinfo.obd_name); resource_list_free(&di->rl); ofw_bus_gen_destroy_devinfo(&di->obdinfo); free(di, M_DEVBUF); continue; } device_set_ivars(cdev, di); } return (bus_generic_attach(dev)); }
static int ofw_cpulist_attach(device_t dev) { struct ofw_cpulist_softc *sc; phandle_t root, child; device_t cdev; struct ofw_bus_devinfo *dinfo; sc = device_get_softc(dev); root = ofw_bus_get_node(dev); sc->sc_addr_cells = 1; OF_getencprop(root, "#address-cells", &sc->sc_addr_cells, sizeof(sc->sc_addr_cells)); for (child = OF_child(root); child != 0; child = OF_peer(child)) { dinfo = malloc(sizeof(*dinfo), M_OFWCPU, M_WAITOK | M_ZERO); if (ofw_bus_gen_setup_devinfo(dinfo, child) != 0) { free(dinfo, M_OFWCPU); continue; } cdev = device_add_child(dev, NULL, -1); if (cdev == NULL) { device_printf(dev, "<%s>: device_add_child failed\n", dinfo->obd_name); ofw_bus_gen_destroy_devinfo(dinfo); free(dinfo, M_OFWCPU); continue; } device_set_ivars(cdev, dinfo); } return (bus_generic_attach(dev)); }
static int l3remap(struct rstmgr_softc *sc, int remap, int enable) { uint32_t paddr; bus_addr_t vaddr; phandle_t node; int reg; /* * Control whether bridge is visible to L3 masters or not. * Register is write-only. */ reg = REMAP_MPUZERO; if (enable) reg |= (remap); else reg &= ~(remap); node = OF_finddevice("l3regs"); if (node == -1) { device_printf(sc->dev, "Can't find l3regs node\n"); return (1); } if ((OF_getencprop(node, "reg", &paddr, sizeof(paddr))) > 0) { if (bus_space_map(fdtbus_bs_tag, paddr, 0x4, 0, &vaddr) == 0) { bus_space_write_4(fdtbus_bs_tag, vaddr, L3REGS_REMAP, reg); return (0); } } return (1); }
static int pinmux_read_node(struct pinmux_softc *sc, phandle_t node, struct pincfg *cfg, char **pins, int *lpins) { int rv, i; *lpins = OF_getprop_alloc(node, "nvidia,pins", 1, (void **)pins); if (*lpins <= 0) return (ENOENT); /* Read function (mux) settings. */ rv = OF_getprop_alloc(node, "nvidia,function", 1, (void **)&cfg->function); if (rv <= 0) cfg->function = NULL; /* Read numeric properties. */ for (i = 0; i < PROP_ID_MAX_ID; i++) { rv = OF_getencprop(node, prop_names[i].name, &cfg->params[i], sizeof(cfg->params[i])); if (rv <= 0) cfg->params[i] = -1; } return (0); }
int uart_fdt_get_clock(phandle_t node, pcell_t *cell) { /* clock-frequency is a FreeBSD-only extention. */ if ((OF_getencprop(node, "clock-frequency", cell, sizeof(*cell))) <= 0) { /* Try to retrieve parent 'bus-frequency' */ /* XXX this should go to simple-bus fixup or so */ if ((OF_getencprop(OF_parent(node), "bus-frequency", cell, sizeof(*cell))) <= 0) *cell = 0; } return (0); }
static int mv_cp110_icu_attach(device_t dev) { struct mv_cp110_icu_softc *sc; phandle_t node, msi_parent; sc = device_get_softc(dev); sc->dev = dev; node = ofw_bus_get_node(dev); if (OF_getencprop(node, "msi-parent", &msi_parent, sizeof(phandle_t)) <= 0) { device_printf(dev, "cannot find msi-parent property\n"); return (ENXIO); } if ((sc->parent = OF_device_from_xref(msi_parent)) == NULL) { device_printf(dev, "cannot find msi-parent device\n"); return (ENXIO); } if (bus_alloc_resources(dev, mv_cp110_icu_res_spec, &sc->res) != 0) { device_printf(dev, "cannot allocate resources for device\n"); return (ENXIO); } if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { device_printf(dev, "Cannot register ICU\n"); goto fail; } return (0); fail: bus_release_resources(dev, mv_cp110_icu_res_spec, &sc->res); return (ENXIO); }
static int reset_hsic_hub(struct exynos_ehci_softc *esc, phandle_t hub) { device_t gpio_dev; pcell_t pin; /* TODO: check that hub is compatible with "smsc,usb3503" */ if (!OF_hasprop(hub, "freebsd,reset-gpio")) { return (1); } if (OF_getencprop(hub, "freebsd,reset-gpio", &pin, sizeof(pin)) < 0) { device_printf(esc->dev, "failed to decode reset GPIO pin number for HSIC hub\n"); return (1); } /* Get the GPIO device, we need this to give power to USB */ gpio_dev = devclass_get_device(devclass_find("gpio"), 0); if (gpio_dev == NULL) { device_printf(esc->dev, "Cant find gpio device\n"); return (1); } GPIO_PIN_SET(gpio_dev, pin, GPIO_PIN_LOW); DELAY(100); GPIO_PIN_SET(gpio_dev, pin, GPIO_PIN_HIGH); return (0); }
static int opaldev_probe(device_t dev) { phandle_t iparent; pcell_t *irqs; int i, n_irqs; if (!ofw_bus_is_compatible(dev, "ibm,opal-v3")) return (ENXIO); if (opal_check() != 0) return (ENXIO); device_set_desc(dev, "OPAL Abstraction Firmware"); /* Manually add IRQs before attaching */ if (OF_hasprop(ofw_bus_get_node(dev), "opal-interrupts")) { iparent = OF_finddevice("/interrupt-controller@0"); iparent = OF_xref_from_node(iparent); n_irqs = OF_getproplen(ofw_bus_get_node(dev), "opal-interrupts") / sizeof(*irqs); irqs = malloc(n_irqs * sizeof(*irqs), M_DEVBUF, M_WAITOK); OF_getencprop(ofw_bus_get_node(dev), "opal-interrupts", irqs, n_irqs * sizeof(*irqs)); for (i = 0; i < n_irqs; i++) bus_set_resource(dev, SYS_RES_IRQ, i, ofw_bus_map_intr(dev, iparent, 1, &irqs[i]), 1); free(irqs, M_DEVBUF); } return (BUS_PROBE_SPECIFIC); }
static int ofw_cpu_attach(device_t dev) { struct ofw_cpulist_softc *psc; struct ofw_cpu_softc *sc; phandle_t node; pcell_t cell; int rv; sc = device_get_softc(dev); psc = device_get_softc(device_get_parent(dev)); if (nitems(sc->sc_reg) < psc->sc_addr_cells) { if (bootverbose) device_printf(dev, "Too many address cells\n"); return (EINVAL); } node = ofw_bus_get_node(dev); /* Read and validate the reg property for use later */ sc->sc_reg_valid = false; rv = OF_getencprop(node, "reg", sc->sc_reg, sizeof(sc->sc_reg)); if (rv < 0) device_printf(dev, "missing 'reg' property\n"); else if ((rv % 4) != 0) { if (bootverbose) device_printf(dev, "Malformed reg property\n"); } else if ((rv / 4) != psc->sc_addr_cells) { if (bootverbose) device_printf(dev, "Invalid reg size %u\n", rv); } else sc->sc_reg_valid = true; sc->sc_cpu_pcpu = pcpu_find(device_get_unit(dev)); if (OF_getencprop(node, "clock-frequency", &cell, sizeof(cell)) < 0) { if (bootverbose) device_printf(dev, "missing 'clock-frequency' property\n"); } else sc->sc_nominal_mhz = cell / 1000000; /* convert to MHz */ bus_generic_probe(dev); return (bus_generic_attach(dev)); }
int uart_fdt_get_io_width(phandle_t node, pcell_t *cell) { if ((OF_getencprop(node, "reg-io-width", cell, sizeof(*cell))) <= 0) return (-1); return (0); }
static int at91_pinctrl_attach(device_t dev) { struct pinctrl_softc *sc; struct pinctrl_devinfo *di; phandle_t node; device_t cdev; sc = device_get_softc(dev); node = ofw_bus_get_node(dev); sc->dev = dev; sc->node = node; /* * Some important numbers */ sc->acells = 2; OF_getencprop(node, "#address-cells", &sc->acells, sizeof(sc->acells)); sc->scells = 1; OF_getencprop(node, "#size-cells", &sc->scells, sizeof(sc->scells)); if (at91_pinctrl_fill_ranges(node, sc) < 0) { device_printf(dev, "could not get ranges\n"); return (ENXIO); } for (node = OF_child(node); node > 0; node = OF_peer(node)) { if ((di = at91_pinctrl_setup_dinfo(dev, node)) == NULL) continue; cdev = device_add_child(dev, NULL, -1); if (cdev == NULL) { device_printf(dev, "<%s>: device_add_child failed\n", di->obdinfo.obd_name); resource_list_free(&di->rl); ofw_bus_gen_destroy_devinfo(&di->obdinfo); free(di, M_DEVBUF); continue; } device_set_ivars(cdev, di); } fdt_pinctrl_register(dev, "atmel,pins"); return (bus_generic_attach(dev)); }
int uart_fdt_get_shift(phandle_t node, pcell_t *cell) { if ((OF_getencprop(node, "reg-shift", cell, sizeof(*cell))) <= 0) return (-1); return (0); }
static int ofw_pci_fill_ranges(phandle_t node, struct ofw_pci_range *ranges) { int host_address_cells = 1, pci_address_cells = 3, size_cells = 2; cell_t *base_ranges; ssize_t nbase_ranges; int nranges; int i, j, k; OF_getencprop(OF_parent(node), "#address-cells", &host_address_cells, sizeof(host_address_cells)); OF_getencprop(node, "#address-cells", &pci_address_cells, sizeof(pci_address_cells)); OF_getencprop(node, "#size-cells", &size_cells, sizeof(size_cells)); nbase_ranges = OF_getproplen(node, "ranges"); if (nbase_ranges <= 0) return (-1); nranges = nbase_ranges / sizeof(cell_t) / (pci_address_cells + host_address_cells + size_cells); base_ranges = malloc(nbase_ranges, M_DEVBUF, M_WAITOK); OF_getencprop(node, "ranges", base_ranges, nbase_ranges); for (i = 0, j = 0; i < nranges; i++) { ranges[i].pci_hi = base_ranges[j++]; ranges[i].pci = 0; for (k = 0; k < pci_address_cells - 1; k++) { ranges[i].pci <<= 32; ranges[i].pci |= base_ranges[j++]; } ranges[i].host = 0; for (k = 0; k < host_address_cells; k++) { ranges[i].host <<= 32; ranges[i].host |= base_ranges[j++]; } ranges[i].size = 0; for (k = 0; k < size_cells; k++) { ranges[i].size <<= 32; ranges[i].size |= base_ranges[j++]; } } free(base_ranges, M_DEVBUF); return (nranges); }
static int gpioiic_attach(device_t dev) { device_t bitbang; #ifdef FDT phandle_t node; pcell_t pin; #endif struct gpiobus_ivar *devi; struct gpioiic_softc *sc; sc = device_get_softc(dev); sc->sc_dev = dev; sc->sc_busdev = device_get_parent(dev); if (resource_int_value(device_get_name(dev), device_get_unit(dev), "scl", &sc->scl_pin)) sc->scl_pin = SCL_PIN_DEFAULT; if (resource_int_value(device_get_name(dev), device_get_unit(dev), "sda", &sc->sda_pin)) sc->sda_pin = SDA_PIN_DEFAULT; #ifdef FDT if ((node = ofw_bus_get_node(dev)) == -1) return (ENXIO); if (OF_getencprop(node, "scl", &pin, sizeof(pin)) > 0) sc->scl_pin = (int)pin; if (OF_getencprop(node, "sda", &pin, sizeof(pin)) > 0) sc->sda_pin = (int)pin; #endif if (sc->scl_pin < 0 || sc->scl_pin > 1) sc->scl_pin = SCL_PIN_DEFAULT; if (sc->sda_pin < 0 || sc->sda_pin > 1) sc->sda_pin = SDA_PIN_DEFAULT; devi = GPIOBUS_IVAR(dev); device_printf(dev, "SCL pin: %d, SDA pin: %d\n", devi->pins[sc->scl_pin], devi->pins[sc->sda_pin]); /* add generic bit-banging code */ bitbang = device_add_child(dev, "iicbb", -1); device_probe_and_attach(bitbang); return (0); }
/* * UART Driver interface. */ static int uart_fdt_get_shift1(phandle_t node) { pcell_t shift; if ((OF_getencprop(node, "reg-shift", &shift, sizeof(shift))) <= 0) shift = 2; return ((int)shift); }
static void ksz90x1_load_values(struct mii_softc *sc, phandle_t node, uint32_t dev, uint32_t reg, char *field1, uint32_t f1mask, int f1off, char *field2, uint32_t f2mask, int f2off, char *field3, uint32_t f3mask, int f3off, char *field4, uint32_t f4mask, int f4off) { pcell_t dts_value[1]; int len; int val; if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9031) val = ksz9031_read(sc, dev, reg); else val = ksz9021_read(sc, reg); if ((len = OF_getproplen(node, field1)) > 0) { OF_getencprop(node, field1, dts_value, len); val &= ~(f1mask << f1off); val |= (PS_TO_REG(dts_value[0]) & f1mask) << f1off; } if (field2 != NULL && (len = OF_getproplen(node, field2)) > 0) { OF_getencprop(node, field2, dts_value, len); val &= ~(f2mask << f2off); val |= (PS_TO_REG(dts_value[0]) & f2mask) << f2off; } if (field3 != NULL && (len = OF_getproplen(node, field3)) > 0) { OF_getencprop(node, field3, dts_value, len); val &= ~(f3mask << f3off); val |= (PS_TO_REG(dts_value[0]) & f3mask) << f3off; } if (field4 != NULL && (len = OF_getproplen(node, field4)) > 0) { OF_getencprop(node, field4, dts_value, len); val &= ~(f4mask << f4off); val |= (PS_TO_REG(dts_value[0]) & f4mask) << f4off; } if (sc->mii_mpd_model == MII_MODEL_MICREL_KSZ9031) ksz9031_write(sc, dev, reg, val); else ksz9021_write(sc, reg, val); }