ExpressionPtr OrExpression::getDNFImpl() const
{
UnaryExpression * leftLeaf = dynamic_cast<UnaryExpression*>(left());
UnaryExpression * rightLeaf = dynamic_cast<UnaryExpression*>(right());
// A or B
if (leftLeaf && rightLeaf)
{
return clone();
}
// A or (B and C) => (A and B) or (A and C)
BinaryExpression * rightAnd = dynamic_cast<AndExpression*>(right());
if (leftLeaf && rightAnd)
{
return Or(And(leftLeaf, rightAnd->left()),
And(leftLeaf, rightAnd->right()));
}
// (A and B) or C => (A and C) or (B and C)
BinaryExpression * leftAnd = dynamic_cast<AndExpression*>(left());
if (leftAnd && rightLeaf)
{
return Or(And(leftAnd->left(), rightLeaf),
And(leftAnd->right(), rightLeaf));
}
return Or(left()->getDNF(), right()->getDNF());
}
void circuits( SD sd, Signal Init, Signal Clock,
Signal w, Signal x, Signal y, Signal z )
{
Module( (sd, "circuits"), (Init, Clock), (w, x, y, z) );
// Insert your declarations for any auxiliary Signals here
Signal W, X, Y, Z;
// Insert your DFFs here
Dff( SD("1b"), ( Init, W, Clock, Zero ), w );
Dff( SD("2b"), ( Zero, X, Clock, Init ), x );
Dff( SD("3b"), ( Init, Y, Clock, Zero ), y );
Dff( SD("4b"), ( Zero, Z, Clock, Init ), z );
// Insert your combinational logic here (Not, And, Or gates)
Signal notx, noty, notz;
Not ( SD(sd,"1d"), x, notx );
Not ( SD(sd,"2d"), y, noty );
Not ( SD(sd,"3d"), z, notz );
Signal and1, and2, and3, and4;
And ( SD(sd,"1e"), (notx, noty), and1 );
And ( SD(sd,"2e"), (x, notz), and2 );
And ( SD(sd,"3e"), (w, y), and3 );
And ( SD(sd,"4e"), (noty, notz), and4 );
Or ( SD(sd,"1f"), (and1, and1), W );
Or ( SD(sd,"2f"), (and2, and3), X );
Or ( SD(sd,"3f"), (z, z), Y );
Or ( SD(sd,"4f"), (and4, and4), Z );
}
int main( )
{
execute( Seq(
If( True( ), Print( String( "hello " ) ), Print( True( ) ) ),
If( Or( False( ), Neg( True( ) ) ), Print( Unit( ) ), Print( String( "world!\n" ) ) ) ) );
execute( Seq(
When( True( ), Print( String( "hello " ) ) ),
Unless( False( ), Print( String( "world!\n" ) ) ) ) );
execute( Print( Print( Seq( Print( True( ) ), Print( False( ) ) ) ) ) );
execute( Print( Concat( String( "4" ), Show( True( ) ) ) ) );
assert( value_to_bool( execute( IsDefined( String( "not defined" ) ) ) ) == false );
execute(
Seq( Set( String( "SomeVar" ), String( "12" ) ),
Seq( Print( Get( String( "SomeVar" ) ) ),
Seq( Set( Concat( String( "S" ), String( "omeVar" ) ), String( "345\n" ) ),
Print( Get( Concat( String( "Some" ), String( "Var" ) ) ) ) ) ) ) );
execute( Seq(
If( True( ), Set( String( "hello " ), String( "hellos \n" ) ), Print( True( ) ) ), Print( Get( String( "hello " ) ) ) ) );
execute( Seq( Scope( Set( String( "hi" ), True( ) ) ), Print( IsDefined( String( "hi" ) ) ) ) );
assert(
value_to_bool( execute( Seq( Seq( Set( String( "var" ), False( ) ), Scope( Set( String( "var" ), True( ) ) ) ), Get( String( "var" ) ) ) ) ) );
execute(
Seq(
Seq( Set( String( "b1" ), True( ) ), Set( String( "b2" ), True( ) ) ),
While(
Or( Get( String( "b1" ) ), Get( String( "b2" ) ) ),
If( Get( String( "b1" ) ),
Seq( Set( String( "b1" ), False( ) ), Print( String( "Hello" ) ) ),
Seq( Set( String( "b2" ), False( ) ), Print( String( "World" ) ) ) ) ) ) );
}
ExpressionPtr AndExpression::getDNFImpl() const
{
UnaryExpression * leftLeaf = dynamic_cast<UnaryExpression*>(left());
UnaryExpression * rightLeaf = dynamic_cast<UnaryExpression*>(right());
if (leftLeaf && rightLeaf)
{
return clone();
}
// (A or B) and C => (A and C) or (B and C)
if (OrExpression * leftOr = dynamic_cast<OrExpression*>(left()))
{
return Or(And(leftOr->left(), right()),
And(leftOr->right(), right()));
}
// A and (B or C) -> (A and B) or (A and C)
if (OrExpression * rightOr = dynamic_cast<OrExpression*>(right()))
{
return Or(And(left(), rightOr->left()),
And(left(), rightOr->right()));
}
return And(left()->getDNF(), right()->getDNF());
}
void alu(SD(sd),
const Signals& A,
const Signals& B,
const Signal& Cin,
const Signal& Ainvert,
const Signal& Binvert,
const Signal& Unsgn,
const Signals& Op,
const Signals& Res,
const Signal& C,
const Signal& V)
{
Module((sd, "32 Bit ALU"),
(A,B,Cin,Ainvert,Binvert,Unsgn,Op),
(Res,C,V)
);
Signal Cout(NUM_BITS);
Signal lessIn;
Signal lessOut;
Signal notV;
Signal notMSB;
Signal notUnsgn;
Signal lessJunk(NUM_BITS-1);
Signal set;
Signal setIntrm(3);
Signal Prod1;
Signal Prod2;
oneBitALU(SD(sd, "1d"), A[0], B[0], Cin, lessIn, Ainvert, Binvert, Op,
Res[0], Cout[0], lessJunk[0]);
for (int i = 1; i < NUM_BITS-1; ++i)
oneBitALU(SD(sd,"1d"), A[i], B[i], Cout[i-1], Zero, Ainvert, Binvert, Op,
Res[i], Cout[i], lessJunk[i]);
oneBitALU(SD(sd,"1d"), A[NUM_BITS-1], B[NUM_BITS-1], Cout[NUM_BITS-2], Zero,
Ainvert, Binvert, Op, Res[NUM_BITS-1], C, lessOut);
Not(SD(sd, "1d"), V, notV);
Not(SD(sd, "1d"), Res[NUM_BITS-1], notMSB);
Not(SD(sd, "1d"), Unsgn, notUnsgn);
And(SD(sd, "1d"), (notUnsgn, notV, Res[NUM_BITS-1]), setIntrm[0]);
And(SD(sd, "1d"), (notUnsgn, V, notMSB), setIntrm[1]);
And(SD(sd, "1d"), (Unsgn, V), setIntrm[2]);
Or(SD(sd, "1d"), setIntrm, set);
And(SD(sd, "1d"), (set, lessOut), lessIn);
Iand(SD(sd, "1d"), (Res[NUM_BITS-1]), (A[NUM_BITS-1],B[NUM_BITS-1]), Prod1);
Iand(SD(sd, "1d"), (A[NUM_BITS-1], B[NUM_BITS-1]), (Res[NUM_BITS-1]), Prod2);
Or(SD(sd, "1d"), (Prod1, Prod2), V);
}
/*
********************************************************************************
* *
* StoreRefutation() is called when a move at the current ply is so good it *
* "refutes" the move made at the previous ply. we then remember this so it *
* can be used to do the same the next time this position is reached. *
* *
********************************************************************************
*/
void StoreRefutation(int ply, int depth, int wtm, int bound)
{
register HASH_ENTRY *htablea, *htableb;
register BITBOARD word1, word2;
register int draft, age;
/*
----------------------------------------------------------
| |
| "fill in the blank" and build a table entry from |
| current search information. |
| |
----------------------------------------------------------
*/
word1=Shiftl((BITBOARD) (bound+65536),21);
word1=Or(word1,Shiftl((BITBOARD) ((transposition_id<<2)+LOWER_BOUND),59));
word1=Or(word1,(BITBOARD) current_move[ply]);
word2=Or(HashKey>>16,Shiftl((BITBOARD) depth,48));
/*
----------------------------------------------------------
| |
| if the draft of this entry is greater than the draft |
| of the entry in the "depth-priority" table, or if the |
| entry in the depth-priority table is from an old |
| search, move that entry to the always-store table and |
| then replace the depth-priority table entry by the new |
| hash result. |
| |
----------------------------------------------------------
*/
if (wtm) {
htablea=trans_ref_wa+(((int) HashKey) & hash_maska);
htableb=trans_ref_wb+(((int) HashKey) & hash_maskb);
}
else {
htablea=trans_ref_ba+(((int) HashKey) & hash_maska);
htableb=trans_ref_bb+(((int) HashKey) & hash_maskb);
}
draft=(int) Shiftr(htablea->word2,48);
age=(unsigned int) Shiftr(htablea->word1,61);
age=age && (age!=transposition_id);
if (age || (depth >= draft)) {
htableb->word1=htablea->word1;
htableb->word2=htablea->word2;
htablea->word1=word1;
htablea->word2=word2;
}
else {
htableb->word1=word1;
htableb->word2=word2;
}
}
/*
********************************************************************************
* *
* SwapXray() is used to determine if a piece is "behind" the piece on *
* <from>, and this piece would attack <to> if the piece on <from> were moved *
* (as in playing out sequences of swaps). if so, this indirect attacker is *
* added to the list of attackers bearing to <to>. *
* *
********************************************************************************
*/
BITBOARD SwapXray(BITBOARD attacks, int from, int direction)
{
switch (direction) {
case 1:
return(Or(attacks,
And(And(AttacksRank(from),RooksQueens),plus1dir[from])));
case 7:
return(Or(attacks,
And(And(AttacksDiaga1(from),BishopsQueens),plus7dir[from])));
case 8:
return(Or(attacks,
And(And(AttacksFile(from),RooksQueens),plus8dir[from])));
case 9:
return(Or(attacks,
And(And(AttacksDiagh1(from),BishopsQueens),plus9dir[from])));
case -1:
return(Or(attacks,
And(And(AttacksRank(from),RooksQueens),minus1dir[from])));
case -7:
return(Or(attacks,
And(And(AttacksDiaga1(from),BishopsQueens),minus7dir[from])));
case -8:
return(Or(attacks,
And(And(AttacksFile(from),RooksQueens),minus8dir[from])));
case -9:
return(Or(attacks,
And(And(AttacksDiagh1(from),BishopsQueens),minus9dir[from])));
}
return(attacks);
}
void circuits( SD sd, Signal Init, Signal Clock,
Signal w, Signal x, Signal y, Signal z )
{
Module( (sd, "circuits"), (Init, Clock), (w, x, y, z) );
// Insert your declarations for any auxiliary Signals here
Signal notw, notx, noty, notz, W, X, Y, Z;
// Insert your DFFs here
Dff (SD(sd,"2g"), (Init, W, Clock, Zero), w);
Dff (SD(sd,"3g"), (Zero, X, Clock, Init), x);
Dff (SD(sd,"4g"), (Init, Y, Clock, Zero), y);
Dff (SD(sd,"5g"), (Zero, Z, Clock, Init), z);
// Insert your combinational logic here (Not, And, Or gates)
Not (SD(sd,"2b"), w, notw);
Not (SD(sd,"3b"), x, notx);
Not (SD(sd,"4b"), y, noty);
Not (SD(sd,"5b"), z, notz);
// W = wx + yz + wy'
Signal wfirst, wsecond, wthird;
And (SD(sd, "2c"), (w, x), wfirst);
And (SD(sd, "3c"), (y, z), wsecond);
And (SD(sd, "4c"), (w, noty), wthird);
Or (SD(sd, "5c"), (wfirst, wsecond, wthird), W);
// X = xz' + wz + wy
Signal xfirst, xsecond, xthird;
And (SD(sd, "2d"), (x, notz), xfirst);
And (SD(sd, "3d"), (w, z), xsecond);
And (SD(sd, "4d"), (w, y), xthird);
Or (SD(sd, "6d"), (xfirst, xsecond, xthird), X);
// Y = y'z + xy + wy'
Signal yfirst, ysecond, ythird;
And (SD(sd, "2e"), (noty, z), yfirst);
And (SD(sd, "3e"), (x, y), ysecond);
And (SD(sd, "4e"), (w, noty), ythird);
Or (SD(sd, "5e"), (yfirst, ysecond, ythird), Y);
// Z = wx + w'z' + x'y'z
Signal zfirst, zsecond, zthird;
And (SD(sd, "2f"), (w, x), zfirst);
And (SD(sd, "3f"), (notw, notz), zsecond);
And (SD(sd, "4f"), (notx, noty, z), zthird);
Or (SD(sd, "5f"), (zfirst, zsecond, zthird), Z);
}
//膨胀
void Dilate(double *src,int s_width,int s_height,double *dst,int d_width,int d_height,double *se,int se_width,int se_height,Position *center){
if(center==NULL){
Position temp;
temp.x=se_width/2;
temp.y=se_height/2;
center=&temp;
}
MoveDirection m;
double *temp=(double *)malloc(sizeof(double)*d_width*d_height);
double *tempdst=(double *)malloc(sizeof(double)*d_width*d_height);
double *realdst=(double *)malloc(sizeof(double)*d_width*d_height);
Zero(realdst, d_width, d_height);
Zoom(src,s_width,s_height,temp,d_width,d_height);
for(int i=0;i<se_width;i++){
for(int j=0;j<se_height;j++){
if(se[j*se_width+i]>100.0){
m.x=i-center->x;
m.y=j-center->y;
Translation(temp,tempdst,d_width,d_height, &m);
Or(tempdst, realdst, realdst,d_width,d_height);
}
}
}
matrixCopy(realdst, dst, d_width, d_height);
free(temp);
free(realdst);
free(tempdst);
}
arithmtype EvalExpression(char * ExprString)
{
arithmtype Res;
Expr = ExprString;
// Res = AddSub();
ErrorDesc = NULL;
Res = Or();
return Res;
}
Expression *OrExp::optimize(int result)
{ Expression *e;
e1 = e1->optimize(result);
e2 = e2->optimize(result);
if (e1->isConst() == 1 && e2->isConst() == 1)
e = Or(type, e1, e2);
else
e = this;
return e;
}
/*
********************************************************************************
* *
* StorePV() is called by Iterate() to insert the PV moves so they will be *
* searched before any other moves. *
* *
********************************************************************************
*/
void StorePV(int ply, int wtm)
{
register BITBOARD temp_hash_key;
register HASH_ENTRY *htable;
/*
----------------------------------------------------------
| |
| make sure the move being stored is legal, so that a |
| bad move doesn't get into hash table. |
| |
----------------------------------------------------------
*/
if (!ValidMove(ply,wtm,pv[ply].path[ply])) {
printf("\ninstalling bogus move...ply=%d\n",ply);
printf("installing %s\n",OutputMove(&pv[ply].path[ply],ply,wtm));
return;
}
/*
----------------------------------------------------------
| |
| first, compute the initial hash address and choose |
| which hash table (based on color) to probe. |
| |
----------------------------------------------------------
*/
temp_hash_key=HashKey;
htable=((wtm) ? trans_ref_wb : trans_ref_bb)+(((int) temp_hash_key)&hash_maskb);
temp_hash_key=temp_hash_key>>16;
/*
----------------------------------------------------------
| |
| now "fill in the blank" and build a table entry from |
| current search information. |
| |
----------------------------------------------------------
*/
htable->word1=Shiftl((BITBOARD) 65536,21);
htable->word1=Or(htable->word1,Shiftl((BITBOARD) ((transposition_id<<2)+WORTHLESS),59));
htable->word1=Or(htable->word1,(BITBOARD) pv[ply].path[ply]);
htable->word2=temp_hash_key;
}
void control(SD(sd),
const Signals& OpCode,
const Signals& Out)
{
Signal bits(WORDSIZE, "ROM Output");
loadRom(controlRom, ROMSIZE * WORDSIZE, "controlUnitRom.txt");
Rom(SD(sd, "1a"), OpCode, bits, ROMSIZE, WORDSIZE, controlRom);
for (int ndx = 0; ndx < NUM_BITS; ++ndx)
Or(SD(sd, "1a"), (bits[ndx], Zero), Out[ndx]);
}
unsigned int Query::Clone(const Query *other)
{
// TRACE << "Cloning " << other->ToString() << "\n";
for (restrictions_t::const_iterator i = other->m_restrictions.begin();
i != other->m_restrictions.end();
++i)
{
if (i->is_string)
Restrict(i->which, i->rt, i->sval);
else
Restrict(i->which, i->rt, i->ival);
}
for (relations_t::const_iterator i = other->m_relations.begin();
i != other->m_relations.end();
++i)
{
if (i->anditive)
And(Subexpression((int)i->a), Subexpression((int)i->b));
else
Or(Subexpression((int)i->a), Subexpression((int)i->b));
}
unsigned int rc = Where(Subexpression(other->m_root));
if (rc)
return rc;
for (orderby_t::const_iterator i = other->m_orderby.begin();
i != other->m_orderby.end();
++i)
{
rc = OrderBy(*i);
if (rc)
return rc;
}
for (orderby_t::const_iterator i = other->m_collateby.begin();
i != other->m_collateby.end();
++i)
{
rc = CollateBy(*i);
if (rc)
return rc;
}
// TRACE << "Cloned: " << ToString() << "\n";
return 0;
}
void circuit( SD sd, Signal a, Signal b, Signal c, Signal d, Signal F )
{
Module( (sd, "circuit"), (a, b, c, d), (F) );
Signal notb, notc, notd;
Signal and1, and2; // Intermediate objects
Not ( SD(sd,"2a"), b, notb ); // NOT gates
Not ( SD(sd,"3a"), c, notc );
Not ( SD(sd,"4a"), d, notd );
And ( SD(sd,"2c"), (a, notb), and1 ); // AND gates
And ( SD(sd,"3c"), (b, notc, notd), and2 );
Or ( SD(sd,"2e"), (and1, and2), F ); // OR gate
}
BITBOARD ValidateComputeBishopAttacks(int square)
{
BITBOARD attacks, temp_attacks;
BITBOARD temp7, temp9;
attacks=bishop_attacks[square];
temp_attacks=And(attacks,Compl(Occupied));
temp_attacks=Compl(Or(temp_attacks,Compl(bishop_attacks[square])));
temp7=And(temp_attacks,plus7dir[square]);
temp9=And(temp_attacks,plus9dir[square]);
attacks=Xor(attacks,plus7dir[FirstOne(temp7)]);
attacks=Xor(attacks,plus9dir[FirstOne(temp9)]);
temp7=And(temp_attacks,minus7dir[square]);
temp9=And(temp_attacks,minus9dir[square]);
attacks=Xor(attacks,minus7dir[LastOne(temp7)]);
attacks=Xor(attacks,minus9dir[LastOne(temp9)]);
return(attacks);
}
BITBOARD ValidateComputeRookAttacks(int square)
{
BITBOARD attacks, temp_attacks;
BITBOARD temp1, temp8;
attacks=rook_attacks[square];
temp_attacks=And(attacks,Compl(Occupied));
temp_attacks=Compl(Or(temp_attacks,Compl(rook_attacks[square])));
temp1=And(temp_attacks,plus1dir[square]);
temp8=And(temp_attacks,plus8dir[square]);
attacks=Xor(attacks,plus1dir[FirstOne(temp1)]);
attacks=Xor(attacks,plus8dir[FirstOne(temp8)]);
temp1=And(temp_attacks,minus1dir[square]);
temp8=And(temp_attacks,minus8dir[square]);
attacks=Xor(attacks,minus1dir[LastOne(temp1)]);
attacks=Xor(attacks,minus8dir[LastOne(temp8)]);
return(attacks);
}
//骨架
void FrameWork(double *src,double *dst,int width,int height,double *se,int se_width,int se_height){
double *temp_dst=(double*)malloc(sizeof(double)*width*height);
Zero(temp_dst, width, height);
double *temp=(double *)malloc(sizeof(double)*width*height);
double *temp_open=(double *)malloc(sizeof(double)*width*height);
matrixCopy(src, temp, width, height);
while(!matrixisEmpty(temp,width,height)){
Erode(temp, width, height, temp, width, height, se, se_width, se_height, NULL);
matrixCopy(temp, temp_open, width, height);
Open(temp_open, width, height, temp_open, se, se_width, se_height, NULL);
matrixSub(temp, temp_open,temp_open, width, height);
Or(temp_open, temp_dst, temp_dst, width, height);
}
matrixCopy(temp_dst, dst, width, height);
free(temp);
free(temp_open);
free(temp_dst);
}
//孔洞填充
void FillHole(double *src,double *dst,int width,int height,Position *seed){
double *temp=(double *)malloc(sizeof(double)*width*height);
Zero(temp, width, height);
double *lasttemp=(double *)malloc(sizeof(double)*width*height);
double *nsrc=(double *)malloc(sizeof(double)*width*height);
Not(src, nsrc, width, height);
temp[seed->y*width+seed->x]=255.;
double se[9]={255.,255.,255.,255.,255.,255.,255.,255.,255.};
while(!matrixisEqu(lasttemp, temp, width, height)){
matrixCopy(temp, lasttemp, width, height);
Dilate(temp, width, height, temp, width, height, se, 3, 3, NULL);
And(temp, nsrc, temp, width, height);
}
Or(temp, src, dst, width, height);
free(temp);
free(lasttemp);
free(nsrc);
}
void circuits( SD sd, Signal w, Signal x, Signal y, Signal z,
Signal Present, Signal a, Signal b, Signal c, Signal d, Signal e,
Signal f, Signal g )
{
Module( (sd, "circuits"), (w, x, y, z), (Present, a, b, c, d, e, f, g) );
Signal notz, notw,notx, noty;
Signal and1, and2, and3, and4, and5, and6, and7, and8, and9, and10, and11,and12, and13,and14;
Not(SD(sd, "e1-f8"), z, notz);
Not(SD(sd, "g1-h8"), w, notw);
Not(SD(sd, "i1-j8"), x, notx);
Not(SD(sd, "k1-l8"), y, noty);
And(SD(sd,"ab-be"), (y, z, notw), and1);
And(SD(sd,"cb-de"), (noty, notz, x, notw), and2);
And(SD(sd,"eb-fe"), (w, notx, noty), and3);
And(SD(sd,"gb-he"), (notw, x), and4);
And(SD(sd,"ib-je"), (w,notx,noty), and5);
And(SD(sd,"kb-le"), (y,z,notw), and6);
And(SD(sd,"mb-ne"), (w,notx,noty), and7);
And(SD(sd,"ob-pe"), (noty,notz,notw,x), and8);
And(SD(sd,"qb-re"), (y,z,notw,x), and9);
And(SD(sd,"sb-te"), (noty,notz,w,notx), and10);
And(SD(sd,"ub-ve"), (notw, x,y,z), and11);
And(SD(sd,"wb-xe"), (w,notx,noty,z),and12);
Or(SD(sd,"bg-cl"), (and1, and2, and3), Present);
Or(SD(sd,"dg-el"), (and4,and5),a);
Or(SD(sd,"fg-gl"), (and6,and7),b);
Or(SD(sd,"hg-il"), (One, One),c );
Or(SD(sd,"jg-kl"), (and8,and9,and10),d);
Or(SD(sd,"lg-ml"), (and11,and12),e);
Or(SD(sd,"og-pl"), (One, One), f);
Or(SD(sd,"sg-tl"), (One, One), g);
}
int TestOR1() {
START_TEST_CASE;
DocumentNode *dn = (DocumentNode *)calloc(1, sizeof(DocumentNode));
dn->doc_id = 1467;
dn->freq = 2;
temp_list = dn;
final_list = NULL;
Or();
SHOULD_BE(temp_list == NULL);
SHOULD_BE(final_list->doc_id == 1467);
SHOULD_BE(final_list->freq == 2);
free(dn); // Cleanup.
END_TEST_CASE;
}
// [O]
const Type& TypeVar::Or(const Type& type) {
if (types_.Count() == 1 && types_[0] == Ty_Object) {
return *this;
}
if (type == *Ty_Object) {
types_.Clear();
types_.Add(Ty_Object);
}
if (auto const tyvar = type.DynamicCast<TypeVar>()) {
for (auto const ty: tyvar->types_) {
ASSERT(!ty->Is<TypeVar>());
Or(*ty);
}
return *this;
}
Type::List cur_types(types_);
types_.Clear();
Type::Set tyset;
for (auto const curty: cur_types) {
auto const orty = &TypeOr(*curty, type);
if (orty == Ty_Void) {
if (!tyset.Contains(&type)) {
tyset.Add(&type);
types_.Add(&type);
}
if (!tyset.Contains(curty)) {
tyset.Add(curty);
types_.Add(curty);
}
} else if (!tyset.Contains(orty)) {
tyset.Add(orty);
types_.Add(orty);
}
}
return *this;
}
arithmtype Term(void)
{
//if (UnderVerify)
//printf("Term_Expr=%s (%c)\n",Expr, *Expr);
if (*Expr=='(')
{
arithmtype Res;
Expr++;
// Res = AddSub();
Res = Or();
if (*Expr!=')')
{
ErrorDesc = "Missing parenthesis";
SyntaxError();
}
Expr++;
return Res;
}
else if ( (*Expr>='0' && *Expr<='9') || (*Expr=='$') || (*Expr=='-') )
return Constant();
else if (*Expr>='A' && *Expr<='Z')
return Function();
else if (*Expr=='@')
{
return Variable();
}
else if (*Expr=='!')
{
Expr++;
return Term()?0:1;
}
else
{
if (UnderVerify)
rtapi_print("TermERROR!_ExprHere=%s\n",Expr);
ErrorDesc = "Unknown term";
SyntaxError();
return 0;
}
return 0;
}
void circuits( SD sd, Signal w, Signal x, Signal y, Signal z,
Signal Present, Signal a, Signal b, Signal c, Signal d, Signal e,
Signal f, Signal g )
{
Module( (sd, "circuits"), (w, x, y, z), (Present, a, b, c, d, e, f, g) );
Signal notw, notx, noty, notz;
Signal and1, and2, and3, and4, and5, and6, and7, and8, and9, and10, and11, and12, and13, and14, and15;
Not (SD(sd,"1a"), w, notw);
Not (SD(sd,"1b"), x, notx);
Not (SD(sd,"1c"), y, noty);
Not (SD(sd,"1d"), z, notz);
And (SD(sd,"2a"), (notw, noty, notz), and1);
And (SD(sd,"2b"), (notw,noty,z), and2);
And (SD(sd,"2c"), (notw,x,y), and3);
And (SD(sd,"2d"), (w,notx,noty,z), and4);
And (SD(sd,"2e"), (w,notx,y,notz), and5);
And (SD(sd,"2f"), (notw,notx,noty), and6);
And (SD(sd,"2g"), (notw,y,z), and7);
And (SD(sd,"2h"), (w,noty), and8);
And (SD(sd,"2i"), (notw,notx), and9);
And (SD(sd,"2j"), (notw,y,notz), and10);
And (SD(sd,"2m"), (y,notz), and11);
And (SD(sd,"2n"), (notw,x,notz), and12);
And (SD(sd,"2o"), (notw,notx,y), and13);
And (SD(sd,"2p"), (One,One), and14);
Or (SD(sd,"3a"), (and1,and2,and3,and4,and5), Present);
Or (SD(sd,"3b"), (w,y,and6), a);
Or (SD(sd,"3c"), (w,noty,and7), b);
Or (SD(sd,"3d"), (and14), c);
Or (SD(sd,"3e"), (and8,and9,and10), d);
Or (SD(sd,"3f"), (and11,and6), e);
Or (SD(sd,"3g"), (noty,w,and12), f);
Or (SD(sd,"3h"), (w,and12,and13), g);
}
Array_T
getCharSet(NFA nfa)
{
int i;
ULL128 v;
ULL64 a = 1ULL;
Edge e;
wchar_t c;
Array_T charSet;
charSet = Array_new(0,sizeof(wchar_t));
setZero(&v);
for (i=0; i<Array_length(nfa->edgeArray); i++)
{
e = Array_get(nfa->edgeArray, i);
if (!isEpsilon(e))
{
v = Or(getMatchBitVector(e), v);
}
}
for (i=0; i<64; i++)
{
c = (wchar_t)i;
if ((a & v.L64) != 0)
Array_append (charSet, &c);
a <<= 1;
}
a = 1ULL;
for (i=0; i<64; i++)
{
c = (wchar_t)(i+64);
if ((a & v.H64) != 0)
Array_append (charSet, &c);
a <<= 1;
}
return charSet;
}
int TestOR2() {
START_TEST_CASE;
DocumentNode *dn = (DocumentNode *)calloc(1, sizeof(DocumentNode));
dn->doc_id = 1467;
dn->freq = 2;
temp_list = dn;
DocumentNode *dn2 = (DocumentNode *)calloc(1, sizeof(DocumentNode));
dn2->doc_id = 1467;
dn2->freq = 8;
final_list = dn2;
Or();
SHOULD_BE(temp_list == NULL);
SHOULD_BE(final_list->doc_id == 1467);
SHOULD_BE(final_list->freq == 8); // Frequency is the higher of the two.
free(dn2);
END_TEST_CASE;
}
//凸壳
void Convexhull(double *src,double *dst,int width,int height){
double * temp_dst=(double *)malloc(sizeof(double)*width*height);
matrixCopy(src, temp_dst, width, height);
double * se[4];
double * temp=(double *)malloc(sizeof(double)*width*height);
double * temp_last=(double *)malloc(sizeof(double)*width*height);
matrixCopy(src, temp, width,height);
for(int i=0;i<4;i++){
se[i]=CreateConvexhullSE(i);
while (!matrixisEqu(temp, temp_last, width, height)) {
matrixCopy(temp, temp_last, width, height);
Erode(temp, width,height, temp, width, height, se[i], 3, 3, NULL);
Or(temp, temp_dst, temp, width, height);
}
matrixCopy(temp, temp_dst, width, height);
free(se[i]);
}
matrixCopy(temp_dst, dst, width, height);
free(temp);
free(temp_last);
}
void fullAdder(SD(sd),
// Inputs:
const Signal& A,
const Signal& B,
const Signal& Cin,
// Outputs:
const Signal& Sum,
const Signal& Cout)
{
// This is a Module constructor.
// The first argument is the display name for the module.
// The second argument lists all of the input Signals.
// The third argument lists all of the output Signals.
// If fullAdder() is called directly by simnet(), this will put a "black box"
// named "Full Adder" with three input leads and two output leads in the
// simulation window.
Module((sd, "Full Adder"),
(A, B, Cin),
(Sum, Cout)
);
// Intermediate signals
Signal AxorB;
Signal AandB;
Signal CandAxorB;
// Because these components are inside a Module, they will not be visible in
// the simulation.
Xor(SD(sd, "1b"), (A, B), AxorB);
And(SD(sd, "1b"), (A, B), AandB);
And(SD(sd, "1b"), (AxorB, Cin), CandAxorB);
Or (SD(sd, "1b"), (AandB, CandAxorB), Cout);
Xor(SD(sd, "1b"), (Cin, AxorB), Sum);
}
Predicate Predicate::reduceToDependencies(const TemplateVarArray& array, const bool conservativeDefault) const {
switch (kind()) {
case TRUE:
case FALSE:
case SELFCONST:
{
return copy();
}
case AND:
{
return And(andLeft().reduceToDependencies(array, conservativeDefault), andRight().reduceToDependencies(array, conservativeDefault));
}
case OR:
{
return Or(orLeft().reduceToDependencies(array, conservativeDefault), orRight().reduceToDependencies(array, conservativeDefault));
}
case SATISFIES:
{
if (satisfiesType()->dependsOnOnly(array) && satisfiesRequirement()->dependsOnOnly(array)) {
return copy();
} else {
return Predicate::FromBool(conservativeDefault);
}
}
case VARIABLE:
{
if (array.contains(variableTemplateVar())) {
return copy();
} else {
return Predicate::FromBool(conservativeDefault);
}
}
}
locic_unreachable("Unknown predicate kind.");
}
iboolean operator|| (iboolean& x, iboolean& y) // OR
{ return Or(x,y); }