static void phy_index_power_on(int index) { struct ssusb_sif_port *phy = phy_ports + index; if (!index) { /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */ setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON); /* power domain iso disable */ clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN); } /* switch to USB function. (system register, force ip into usb mode) */ clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN); clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN); if (!index) clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK); /* (force_suspendm=0) (let suspendm=1, enable usb 480MHz pll) */ clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); /* DP/DM BC1.1 path Disable */ clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN); /* improve Rx sensitivity */ clrsetbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2)); /* OTG Enable */ setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN); clrsetbits_le32(&phy->u3phya_da.reg0, P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); clrsetbits_le32(&phy->u3phya.phya_reg9, P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); if (!index) { /* [mt8173]disable Change 100uA current from SSUSB */ clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN); } clrsetbits_le32(&phy->u3phya.phya_reg6, P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); clrsetbits_le32(&phy->u3phyd.phyd_cdr1, P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc)); clrsetbits_le32(&phy->u3phyd.phyd_cdr1, P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3)); clrsetbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID); /* USB 2.0 slew rate calibration */ clrsetbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); }
static void phy_index_power_on(int index) { struct ssusb_sif_port *phy = phy_ports + index; if (!index) { /* Set RG_SSUSB_VUSB10_ON as 1 after VUSB10 ready */ setbits_le32(&phy->u3phya.phya_reg0, P3A_RG_U3_VUSB10_ON); /* Disable power domain ISO */ clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_ISO_EN); } /* Switch system IP to USB mode */ clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_UART_EN); clrbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_UART_EN); if (!index) clrbits_le32(&phy->u2phy.u2phyacr4, P2C_U2_GPIO_CTR_MSK); /* Disable force settings */ clrbits_le32(&phy->u2phy.u2phydtm0, P2C_FORCE_SUSPENDM | P2C_RG_XCVRSEL | P2C_RG_DATAIN | P2C_DTM0_PART_MASK); clrbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_BC11_SW_EN); /* Improve Rx sensitivity */ clrsetbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_SQTH, PA6_RG_U2_SQTH_VAL(2)); setbits_le32(&phy->u2phy.usbphyacr6, PA6_RG_U2_OTG_VBUSCMP_EN); clrsetbits_le32(&phy->u3phya_da.reg0, P3A_RG_XTAL_EXT_EN_U3, P3A_RG_XTAL_EXT_EN_U3_VAL(2)); clrsetbits_le32(&phy->u3phya.phya_reg9, P3A_RG_RX_DAC_MUX, P3A_RG_RX_DAC_MUX_VAL(4)); if (!index) clrbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HS_100U_U3_EN); clrsetbits_le32(&phy->u3phya.phya_reg6, P3A_RG_TX_EIDLE_CM, P3A_RG_TX_EIDLE_CM_VAL(0xe)); clrsetbits_le32(&phy->u3phyd.phyd_cdr1, P3D_RG_CDR_BIR_LTD0, P3D_RG_CDR_BIR_LTD0_VAL(0xc)); clrsetbits_le32(&phy->u3phyd.phyd_cdr1, P3D_RG_CDR_BIR_LTD1, P3D_RG_CDR_BIR_LTD1_VAL(0x3)); clrsetbits_le32(&phy->u2phy.u2phydtm1, P2C_RG_SESSEND, P2C_RG_VBUSVALID | P2C_RG_AVALID); /* Set USB 2.0 slew rate value */ clrsetbits_le32(&phy->u2phy.usbphyacr5, PA5_RG_U2_HSTX_SRCTRL, PA5_RG_U2_HSTX_SRCTRL_VAL(4)); }