void intel_pch_finalize_smm(void) { /* Set SPI opcode menu */ RCBA16(0x3894) = SPI_OPPREFIX; RCBA16(0x3896) = SPI_OPTYPE; RCBA32(0x3898) = SPI_OPMENU_LOWER; RCBA32(0x389c) = SPI_OPMENU_UPPER; /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); #if CONFIG_SPI_FLASH_SMM /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif /* TCLOCKDN: TC Lockdown */ RCBA32_OR(0x0050, (1 << 31)); /* BIOS Interface Lockdown */ RCBA32_OR(0x3410, (1 << 0)); /* Function Disable SUS Well Lockdown */ RCBA_AND_OR(8, 0x3420, ~0U, (1 << 7)); /* Global SMI Lock */ pci_or_config16(PCH_LPC_DEV, 0xa0, 1 << 4); /* GEN_PMCON Lock */ pci_or_config8(PCH_LPC_DEV, 0xa6, (1 << 1) | (1 << 2)); /* R/WO registers */ RCBA32(0x21a4) = RCBA32(0x21a4); pci_write_config32(PCI_DEV(0, 27, 0), 0x74, pci_read_config32(PCI_DEV(0, 27, 0), 0x74)); /* Indicate finalize step with post code */ outb(POST_OS_BOOT, 0x80); }
static void sch_detect_chipset(void) { u16 reg16; u8 reg8; printk(BIOS_INFO, "\n"); reg16 = pci_read_config16(PCI_DEV(0, 0x00, 0), 0x2); switch (reg16) { case 0x8101: printk(BIOS_INFO, "UL11L/US15L"); break; case 0x8100: printk(BIOS_INFO, "US15W"); break; default: /* Others reserved. */ printk(BIOS_INFO, "Unknown (%02x)", reg16); } printk(BIOS_INFO, " Chipset\n"); reg8 = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0x8); switch (reg8) { case 3: printk(BIOS_INFO, "Qual. Sample ES1, Stepping B1"); break; case 4: printk(BIOS_INFO, "Qual. Sample ES2, Stepping C0"); break; case 5: printk(BIOS_INFO, "Qual. Sample ES2-Prime, Stepping D0"); break; case 6: printk(BIOS_INFO, "Qual. Sample QS, Stepping D1"); break; default: /* Others reserved. */ printk(BIOS_INFO, "Unknown (%02x)", reg8); } }
static void sdram_set_registers(const struct mem_controller *ctrl) { static const u32 register_values[] = { /* CKDIS 0x8c disable clocks */ PCI_ADDR(0, 0x00, 0, CKDIS), 0xffff0000, 0x0000ffff, /* 0x9c Device present and extended RAM control * DEVPRES is very touchy, hard code the initialization * of PCI-E ports here. */ PCI_ADDR(0, 0x00, 0, DEVPRES), 0x00000000, 0x07020801 | DEVPRES_CONFIG, /* 0xc8 Remap RAM base and limit off */ PCI_ADDR(0, 0x00, 0, REMAPLIMIT), 0x00000000, 0x03df0000, /* ??? */ PCI_ADDR(0, 0x00, 0, 0xd8), 0x00000000, 0xb5930000, PCI_ADDR(0, 0x00, 0, 0xe8), 0x00000000, 0x00004a2a, /* 0x50 scrub */ PCI_ADDR(0, 0x00, 0, MCHCFG0), 0xfce0ffff, 0x00006000, /* 6000 */ /* 0x58 0x5c PAM */ PCI_ADDR(0, 0x00, 0, PAM-1), 0xcccccc7f, 0x33333000, PCI_ADDR(0, 0x00, 0, PAM+3), 0xcccccccc, 0x33333333, /* 0xf4 */ PCI_ADDR(0, 0x00, 0, DEVPRES1), 0xffbffff, (1<<22)|(6<<2) | DEVPRES1_CONFIG, /* 0x14 */ PCI_ADDR(0, 0x00, 0, IURBASE), 0x00000fff, (uintptr_t)(MCBAR + 0), }; int i; int max; max = ARRAY_SIZE(register_values); for(i = 0; i < max; i += 3) { device_t dev; u32 where; u32 reg; dev = (register_values[i] & ~0xff) - PCI_DEV(0, 0x00, 0) + ctrl->f0; where = register_values[i] & 0xff; reg = pci_read_config32(dev, where); reg &= register_values[i+1]; reg |= register_values[i+2]; pci_write_config32(dev, where, reg); } printk(BIOS_SPEW, "done.\n"); }
static void ck804_enable_rom(void) { unsigned char byte; device_t addr; /* Enable 4MB ROM access at 0xFFC00000 - 0xFFFFFFFF. */ /* Locate the ck804 LPC. */ addr = PCI_DEV(0, (CK804_DEVN_BASE + 1), 0); /* Set the 4MB enable bit. */ byte = pci_read_config8(addr, 0x88); byte |= 0x80; pci_write_config8(addr, 0x88, byte); }
void gm45_late_init(const stepping_t stepping) { const device_t mch = PCI_DEV(0, 0, 0); const int peg_enabled = (pci_read_config8(mch, D0F0_DEVEN) >> 1) & 1; const int sdvo_enabled = (MCHBAR16(0x40) >> 8) & 1; const int peg_x16 = (peg_enabled && !sdvo_enabled); init_egress(); init_dmi(stepping >= STEPPING_B2); init_pcie(peg_enabled, sdvo_enabled, peg_x16); setup_aspm(stepping, peg_enabled); setup_rcrb(peg_enabled); }
static void i3100_halt_tco_timer(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x0); /* Temporarily enable the ACPI I/O range at 0x4000 */ pci_write_config32(dev, 0x40, 0x4000 | (1 << 0)); pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 << 7)); /* Halt the TCO timer, preventing SMI and automatic reboot */ outw(inw(0x4068) | (1 << 11), 0x4068); /* Disable the ACPI I/O range */ pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) & ~(1 << 7)); }
static void pciinfo(struct udevice *bus, bool short_listing) { struct udevice *dev; pciinfo_header(bus->seq, short_listing); for (device_find_first_child(bus, &dev); dev; device_find_next_child(&dev)) { struct pci_child_platdata *pplat; pplat = dev_get_parent_platdata(dev); if (short_listing) { printf("%02x.%02x.%02x ", bus->seq, PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn)); pci_header_show_brief(dev); } else { printf("\nFound PCI device %02x.%02x.%02x:\n", bus->seq, PCI_DEV(pplat->devfn), PCI_FUNC(pplat->devfn)); pci_header_show(dev); } } }
static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); printk(BIOS_SPEW, "SMBus controller enabled\n"); pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); pci_write_config8(dev, 0x40, 1); pci_write_config8(dev, 0x4, 1); /* SMBALERT_DIS */ outb(4, SMBUS_IO_BASE + SMBSLVCMD); /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); }
/* Functions for manipulating GPIO regs. */ static uint32_t pch_gpiobase(void) { static const uint32_t dev = PCI_DEV(0, 0x1f, 0); static const uint8_t pci_cfg_gpiobase = 0x48; static uint32_t base = ~(uint32_t)0; if (base != ~(uint32_t)0) return base; base = pci_read_config32(dev, pci_cfg_gpiobase); // Drop the IO space bit + baytrail EN bit (also safe on PantherPoint) base &= ~0x3; return base; }
static int tlp_cfg_dword_write(struct intel_fpga_pcie *pcie, pci_dev_t bdf, int offset, u8 byte_en, u32 value) { u32 headers[TLP_HDR_SIZE]; u8 busno = PCI_BUS(bdf); headers[0] = TLP_CFGWR_DW0(pcie, busno); headers[1] = TLP_CFG_DW1(pcie, TLP_WRITE_TAG, byte_en); headers[2] = TLP_CFG_DW2(busno, PCI_DEV(bdf), PCI_FUNC(bdf), offset); tlp_write_packet(pcie, headers, value); return tlp_read_packet(pcie, NULL); }
int mainboard_smi_apmc(u8 data) { u16 pmbase = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0x40) & 0xfffc; u8 tmp; printk(BIOS_DEBUG, "%s: pmbase %04X, data %02X\n", __func__, pmbase, data); if (!pmbase) return 0; switch(data) { case APM_CNT_ACPI_ENABLE: /* use 0x1600/0x1604 to prevent races with userspace */ ec_set_ports(0x1604, 0x1600); /* route H8SCI to SCI */ outw(inw(ALT_GP_SMI_EN) & ~0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x02; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); break; case APM_CNT_ACPI_DISABLE: /* we have to use port 0x62/0x66, as 0x1600/0x1604 doesn't provide a EC query function */ ec_set_ports(0x66, 0x62); /* route H8SCI# to SMI */ outw(inw(pmbase + ALT_GP_SMI_EN) | 0x1000, pmbase + ALT_GP_SMI_EN); tmp = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xbb); tmp &= ~0x03; tmp |= 0x01; pci_write_config8(PCI_DEV(0, 0x1f, 0), 0xbb, tmp); break; default: break; } return 0; }
/******************************************************* * Optimize k8 with UMA. * See BKDG_NPT_0F guide for details. * The processor node is addressed by its Node ID on the HT link and can be * accessed with a device number in the PCI configuration space on Bus0. * The Node ID 0 is mapped to Device 24 (0x18), the Node ID 1 is mapped * to Device 25, and so on. * The processor implements configuration registers in PCI configuration * space using the following four headers * Function0: HT technology configuration * Function1: Address map configuration * Function2: DRAM and HT technology Trace mode configuration * Function3: Miscellaneous configuration *******************************************************/ static void k8_optimization(void) { pci_devfn_t k8_f0, k8_f2, k8_f3; msr_t msr; printk(BIOS_INFO, "k8_optimization()\n"); k8_f0 = PCI_DEV(0, 0x18, 0); k8_f2 = PCI_DEV(0, 0x18, 2); k8_f3 = PCI_DEV(0, 0x18, 3); /* 8.6.6 K8 Buffer Allocation Settings */ pci_write_config32(k8_f0, 0x90, 0x01700169); /* CIM NPT_Optimization */ set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 28, 0 << 28); set_nbcfg_enable_bits(k8_f0, 0x68, 3 << 26, 3 << 26); set_nbcfg_enable_bits(k8_f0, 0x68, 1 << 11, 1 << 11); /* set_nbcfg_enable_bits(k8_f0, 0x84, 1 << 11 | 1 << 13 | 1 << 15, 1 << 11 | 1 << 13 | 1 << 15); */ /* TODO */ pci_write_config32(k8_f3, 0x70, 0x51220111); pci_write_config32(k8_f3, 0x74, 0x50404021); pci_write_config32(k8_f3, 0x78, 0x08002A00); if (pci_read_config32(k8_f3, 0xE8) & 0x3<<12) pci_write_config32(k8_f3, 0x7C, 0x0000211A); /* dual core */ else pci_write_config32(k8_f3, 0x7C, 0x0000212B); /* single core */ set_nbcfg_enable_bits_8(k8_f3, 0xDC, 0xFF, 0x25); set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); set_nbcfg_enable_bits(k8_f2, 0x94, 0xF << 24, 7 << 24); set_nbcfg_enable_bits(k8_f2, 0x90, 1 << 10, 0 << 10); set_nbcfg_enable_bits(k8_f2, 0xA0, 3 << 2, 3 << 2); set_nbcfg_enable_bits(k8_f2, 0xA0, 1 << 5, 1 << 5); msr = rdmsr(NB_CFG_MSR); msr.lo &= ~(1 << 9); msr.hi &= ~(1 << 4); wrmsr(NB_CFG_MSR, msr); }
static void southbridge_smi_tco(unsigned int node, smm_state_save_area_t *state_save) { u32 tco_sts; tco_sts = reset_tco_status(); /* Any TCO event? */ if (!tco_sts) return; if (tco_sts & (1 << 8)) { // BIOSWR u8 bios_cntl; bios_cntl = pci_read_config16(PCI_DEV(0, 0x1f, 0), 0xdc); if (bios_cntl & 1) { /* BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS */ /* This is the place where we notice someone * is trying to tinker with the BIOS. We are * trying to be nice and just ignore it. A more * resolute answer would be to power down the * box. */ printk(BIOS_DEBUG, "Switching back to RO\n"); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xdc, (bios_cntl & ~1)); } /* No else for now? */ } else if (tco_sts & (1 << 3)) { /* TIMEOUT */ /* Handle TCO timeout */ printk(BIOS_DEBUG, "TCO Timeout.\n"); } else { dump_tco_status(tco_sts); } }
static uintptr_t hudson_spibase(void) { /* Make sure the base address is predictable */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) & 0xfffffff0; if (!base){ base = SPI_BASE_ADDRESS; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base | SPI_ROM_ENABLE); /* PCI_COMMAND_MEMORY is read-only and enabled. */ } return (uintptr_t)base; }
static void enable_port80_on_lpc(void) { pci_devfn_t dev = PCI_DEV(0, 0x1f, 0); /* Enable port 80 POST on LPC */ pci_write_config32(dev, RCBA, (uintptr_t)DEFAULT_RCBA | 1); #if 0 RCBA32(GCS) &= (~0x04); #else volatile u32 *gcs = (volatile u32 *)(DEFAULT_RCBA + GCS); u32 reg32 = *gcs; reg32 = reg32 & ~0x04; *gcs = reg32; #endif }
static void ich7_enable_lpc(void) { // Enable Serial IRQ pci_write_config8(PCI_DEV(0, 0x1f, 0), 0x64, 0xd0); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0210); // decode range pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x1f0d); /* range 0x1600 - 0x167f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x84, 0x1601); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x86, 0x007c); /* range 0x15e0 - 0x10ef */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x88, 0x15e1); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8a, 0x000c); /* range 0x1680 - 0x169f */ pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8c, 0x1681); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x8e, 0x001c); }
void board_BeforeAgesa(struct sysinfo *cb) { /* For serial port option, plug-in card on LPC. */ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5); hudson_lpc_port80(); /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. * Otherwise the serial output is bad code. */ outb(0xD2, 0xcd6); outb(0x00, 0xcd7); }
static void mainboard_smi_save_cmos(void) { u8 val; u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); val = pci_read_config8(PCI_DEV(0, 2, 1), 0xf4); set_option("tft_brightness", &val); val = ec_read(H8_VOLUME_CONTROL); set_option("volume", &val); outb(tmp70, 0x70); outb(tmp72, 0x72); }
uintptr_t lpss_i2c_base_address(unsigned bus) { unsigned devfn; pci_devfn_t dev; /* Find device+function for this controller */ devfn = i2c_bus_to_devfn(bus); if (devfn < 0) return 0; /* Form a PCI address for this device */ dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); /* Read the first base address for this device */ return ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); }
static void enable_smbus(void) { device_t dev = PCI_DEV(0x0, 0x1f, 0x3); print_debug("SMBus controller enabled\n"); /* set smbus iobase */ pci_write_config32(dev, 0x20, SMBUS_IO_BASE | 1); /* Set smbus enable */ pci_write_config8(dev, 0x40, 0x01); /* Set smbus iospace enable */ pci_write_config16(dev, 0x4, 0x01); /* Disable interrupt generation */ outb(0, SMBUS_IO_BASE + SMBHSTCTL); /* clear any lingering errors, so the transaction will run */ outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT); }
static void mcp55_early_clear_port(unsigned mcp55_num, unsigned *busn, unsigned *devn, unsigned *io_base) { static const unsigned int ctrl_devport_conf_clear[] = { PCI_ADDR(0, 1, 1, ANACTRL_REG_POS), ~(0x0000ff00), 0, PCI_ADDR(0, 1, 1, SYSCTRL_REG_POS), ~(0x0000ff00), 0, PCI_ADDR(0, 1, 1, ACPICTRL_REG_POS), ~(0x0000ff00), 0, }; int j; for (j = 0; j < mcp55_num; j++ ) { setup_resource_map_offset(ctrl_devport_conf_clear, ARRAY_SIZE(ctrl_devport_conf_clear), PCI_DEV(busn[j], devn[j], 0) , io_base[j]); } }
/* * Note: The SB700 has two EHCI devices, D18:F2 and D19:F2. * This code currently only supports the first one, i.e., USB Debug devices * attached to physical USB ports belonging to the first EHCI device. */ void enable_usbdebug(unsigned int port) { device_t dev = PCI_DEV(0, 0x12, 2); /* USB EHCI, D18:F2 */ /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* * Select the requested physical USB port (1-15) as the Debug Port. * Must be called after the EHCI BAR has been set up (see above). */ set_debug_port(port); }
void sb800_lpc_port80(void) { u8 byte; device_t dev; /* Enable LPC controller */ byte = pmio_read(0xEC); byte |= 1 << 0; pmio_write(0xEC, byte); /* Enable port 80 LPC decode in pci function 3 configuration space. */ dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); }
/* * new_apl_i2s - Allocate new I2s data structures. * @settings: Apollolake codec settigns * @bps: Bits per sample * * Allocate new I2s data structures. */ AplI2s *new_apl_i2s(const AplI2sSettings *settings, int bps, GpioOps *sdmode) { AplI2s *bus = xzalloc(sizeof(*bus)); pcidev_t lpe_pcidev = PCI_DEV(0, AUDIO_DEV, 0); bus->lpe_bar0 = pci_read_config32(lpe_pcidev, REG_BAR0) & (~0xf); bus->lpe_bar4 = pci_read_config32(lpe_pcidev, REG_BAR4) & (~0xf); bus->ops.send = &apl_i2s_send; bus->regs = (AplI2sRegs *)(bus->lpe_bar4 + APL_SSP5_START_ADDRESS); bus->shim = (AplI2sRegs *)(bus->lpe_bar4 + APL_SSP5_SHIM_START_ADDRESS); bus->settings = settings; bus->bits_per_sample = bps; bus->sdmode_gpio = sdmode; return bus; }
static void sio_setup(void) { u8 byte; u32 dword; device_t dev = PCI_DEV(0, MCP55_DEVN_BASE + 1, 0); /* LPC */ /* Subject decoding */ byte = pci_read_config8(dev, 0x7b); byte |= (1 << 5); pci_write_config8(dev, 0x7b, byte); /* LPC Positive Decode 0 */ dword = pci_read_config32(dev, 0xa0); dword |= (1 << 0); /* COM1 */ pci_write_config32(dev, 0xa0, dword); }
void init_bootmode_straps(void) { u32 flags = 0; /* Write Protect: GPIO58 = GPIO_SPI_WP, active high */ if (get_gpio(GPIO_SPI_WP)) flags |= (1 << FLAG_SPI_WP); /* Recovery: GPIO12 = RECOVERY_L, active low */ if (!get_gpio(GPIO_REC_MODE)) flags |= (1 << FLAG_REC_MODE); /* Developer: Virtual */ pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags); }
static int lpss_i2c_early_init_bus(unsigned int bus) { const struct dw_i2c_bus_config *config; const struct device *tree_dev; pci_devfn_t dev; int devfn; uintptr_t base; /* Find the PCI device for this bus controller */ devfn = dw_i2c_soc_bus_to_devfn(bus); if (devfn < 0) { printk(BIOS_ERR, "I2C%u device not found\n", bus); return -1; } /* Look up the controller device in the devicetree */ dev = PCI_DEV(0, PCI_SLOT(devfn), PCI_FUNC(devfn)); tree_dev = dev_find_slot(0, devfn); if (!tree_dev || !tree_dev->enabled) { printk(BIOS_ERR, "I2C%u device not enabled\n", bus); return -1; } /* Skip if not enabled for early init */ config = dw_i2c_get_soc_cfg(bus); if (!config || !config->early_init) { printk(BIOS_DEBUG, "I2C%u not enabled for early init\n", bus); return -1; } /* Prepare early base address for access before memory */ base = dw_i2c_get_soc_early_base(bus); pci_write_config32(dev, PCI_BASE_ADDRESS_0, base); pci_write_config32(dev, PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); /* Take device out of reset */ lpss_reset_release(base); /* Initialize the controller */ if (dw_i2c_init(bus, config) < 0) { printk(BIOS_ERR, "I2C%u failed to initialize\n", bus); return -1; } return 0; }
static uintptr_t smm_region_start(void) { const pci_devfn_t dev = PCI_DEV(0, 0, 0); u32 tor; /* Top of Lower Usable DRAM */ tor = (pci_read_config16(dev, D0F0_TOLUD) & 0xfff0) << 16; /* Graphics memory comes next */ const u32 ggc = pci_read_config16(dev, D0F0_GGC); if (!(ggc & 2)) { /* Graphics memory */ tor -= decode_igd_memory_size((ggc >> 4) & 0xf) << 10; /* GTT Graphics Stolen Memory Size (GGMS) */ tor -= decode_igd_gtt_size((ggc >> 8) & 0xf) << 10; }
void enable_usbdebug(unsigned int port) { u32 dbgctl; device_t dev = PCI_DEV(0, 0x1d, 7); /* USB EHCI, D29:F7 */ /* Set the EHCI BAR address. */ pci_write_config32(dev, EHCI_BAR_INDEX, CONFIG_EHCI_BAR); /* Enable access to the EHCI memory space registers. */ pci_write_config8(dev, PCI_COMMAND, PCI_COMMAND_MEMORY); /* Force ownership of the Debug Port to the EHCI controller. */ printk(BIOS_DEBUG, "Enabling OWNER_CNT\n"); dbgctl = read32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET); dbgctl |= (1 << 30); write32(CONFIG_EHCI_BAR + CONFIG_EHCI_DEBUG_OFFSET, dbgctl); }
static ssize_t device_write(struct file *filp, const char __user * buff, size_t len, loff_t * off) { printk("=== %s:%d\n", __func__, __LINE__); copy_from_user(&g_pci_test , buff, len); #if 0 uint16_t pci_dev = PCI_DEV(0, 0xd, 0); uint8_t reg = 0xe0; uint16_t ret; #endif pci_write16(g_pci_test.pci_dev.u16, g_pci_test.reg, g_pci_test.val); printk("###pci_dev=%x, reg=%x\n", g_pci_test.pci_dev.u16, g_pci_test.reg); return 0; }