Example #1
0
void __pe_initialize_hardware(void)
{

  /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/

  /*** ### MK21FN1M0VMC12 "Cpu" init code ... ***/
  /*** PE initialization code after reset ***/

  /* Disable the WDOG module */
  /* WDOG_UNLOCK: WDOGUNLOCK=0xC520 */
  WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
  /* WDOG_UNLOCK: WDOGUNLOCK=0xD928 */
  WDOG_UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
  /* WDOG_STCTRLH: ??=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,??=0,??=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
  WDOG_STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
                 WDOG_STCTRLH_WAITEN_MASK |
                 WDOG_STCTRLH_STOPEN_MASK |
                 WDOG_STCTRLH_ALLOWUPDATE_MASK |
                 WDOG_STCTRLH_CLKSRC_MASK |
                 0x0100U;

#if MQX_ENABLE_LOW_POWER
    /* Reset from LLWU wake up source */
    if (_lpm_get_reset_source() == MQX_RESET_SOURCE_LLWU)
    {
        PMC_REGSC |= PMC_REGSC_ACKISO_MASK;
    }
#endif
  /* SIM_SCGC6: RTC=1 */
  SIM_SCGC6 |= SIM_SCGC6_RTC_MASK;
  if ((RTC_CR & RTC_CR_OSCE_MASK) == 0u) { /* Only if the OSCILLATOR is not already enabled */
    /* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
    RTC_CR &= (uint32_t)~(uint32_t)(
               RTC_CR_SC2P_MASK |
               RTC_CR_SC4P_MASK |
               RTC_CR_SC8P_MASK |
               RTC_CR_SC16P_MASK
              );
    /* RTC_CR: OSCE=1 */
    RTC_CR |= RTC_CR_OSCE_MASK;
    /* RTC_CR: CLKO=0 */
    RTC_CR &= (uint32_t)~(uint32_t)(RTC_CR_CLKO_MASK);
  }

  /* System clock initialization */
  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=3,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                SIM_CLKDIV1_OUTDIV2(0x01) |
                SIM_CLKDIV1_OUTDIV3(0x03) |
                SIM_CLKDIV1_OUTDIV4(0x03); /* Set the system prescalers to safe value */
  /* SIM_SCGC5: PORTD=1,PORTC=1,PORTA=1 */
  SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK |
               SIM_SCGC5_PORTC_MASK |
               SIM_SCGC5_PORTA_MASK;   /* Enable clock gate for ports to enable pin routing */
  /* SIM_CLKDIV1: OUTDIV1=0,OUTDIV2=1,OUTDIV3=2,OUTDIV4=4,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = SIM_CLKDIV1_OUTDIV1(0x00) |
                SIM_CLKDIV1_OUTDIV2(0x01) |
                SIM_CLKDIV1_OUTDIV3(0x02) |
                SIM_CLKDIV1_OUTDIV4(0x04); /* Update system prescalers */
  /* SIM_CLKDIV2: USBDIV=0,USBFRAC=0 */
  SIM_CLKDIV2 = (uint32_t)0x09UL; /* Update USB clock prescalers */
  /* SIM_SOPT2: PLLFLLSEL=1 */
  SIM_SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK; /* Select PLL as a clock source for various peripherals */
  /* SIM_SOPT1: OSC32KSEL=0 */
  SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
  /* PORTA_PCR18: ISF=0,MUX=0 */
  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
  /* PORTA_PCR19: ISF=0,MUX=0 */
  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
  /* Switch to FBE Mode */
  /* MCG_C2: LOCRE0=0,??=0,RANGE0=2,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
  MCG_C2 = (MCG_C2_RANGE0(0x02) | MCG_C2_EREFS0_MASK);
  /* OSC_CR: ERCLKEN=1,??=0,EREFSTEN=1,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC_CR = (OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK);

  /* MCG_C7: OSCSEL=0 */
  MCG_C7 &= (uint8_t)~(uint8_t)(MCG_C7_OSCSEL_MASK);
  /* MCG_C1: CLKS=2,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
  MCG_C1 = (MCG_C1_CLKS(0x02) | MCG_C1_FRDIV(0x03));
  /* MCG_C4: DMX32=0,DRST_DRS=0 */
  MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
  /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=1 */
  MCG_C5 = MCG_C5_PRDIV0(0x01);
  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=6 */
  MCG_C6 = MCG_C6_VDIV0(0x06);
  while((MCG_S & MCG_S_OSCINIT0_MASK) == 0x00U) { /* Check that the oscillator is running */
  }
  while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
  }
  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  }
  /* Switch to PBE Mode */
  /* MCG_C6: LOLIE0=0,PLLS=1,CME0=0,VDIV0=6 */
  MCG_C6 = (MCG_C6_PLLS_MASK | MCG_C6_VDIV0(0x06));
  while((MCG_S & 0x0CU) != 0x08U) {    /* Wait until external reference clock is selected as MCG output */
  }
  while((MCG_S & MCG_S_LOCK0_MASK) == 0x00U) { /* Wait until locked */
  }
  /* Switch to PEE Mode */
  /* MCG_C1: CLKS=0,FRDIV=3,IREFS=0,IRCLKEN=0,IREFSTEN=0 */
  MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x03));
  while((MCG_S & 0x0CU) != 0x0CU) {    /* Wait until output of the PLL is selected */
  }
  /*** End of PE initialization code after reset ***/

  /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/

}
Example #2
0
/***********************************************************************************************
 功能:SPI 初始化
 形参:SPI_InitStruct SPI 初始化结构
 返回:0
 详解:0
************************************************************************************************/
void SPI_Init(SPI_InitTypeDef* SPI_InitStruct)
{
	SPI_Type *SPIx = NULL;
	PORT_Type *SPI_PORT = NULL;
	SPI_DataMapTypeDef *pSPI_DataMap = (SPI_DataMapTypeDef*)&(SPI_InitStruct->SPIxDataMap);
	SPI_CSMapTypeDef *pSPI_CSMap = (SPI_CSMapTypeDef*)&(SPI_InitStruct->SPIxPCSMap);
	
	//参数检测
	assert_param(IS_SPI_DATA_CHL(SPI_InitStruct->SPIxDataMap));
	assert_param(IS_SPI_PCS_CHL(SPI_InitStruct->SPIxPCSMap));
	assert_param(IS_SPI_BAUDRATE(SPI_InitStruct->SPI_BaudRatePrescaler));
	assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
	assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
	assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
	assert_param(IS_SPI_FIRSTBIT(SPI_InitStruct->SPI_FirstBit));
	
	//找出SPI模块 开SPI模块时钟
	switch(pSPI_DataMap->SPI_Index)
	{
		case 0:
			SIM->SCGC6 |= SIM_SCGC6_SPI0_MASK;
			SPIx = SPI0;
			break;
		case 1:
			SIM->SCGC6 |= SIM_SCGC6_SPI1_MASK;
			SPIx = SPI1;
			break;
		case 2:
			SIM->SCGC3 |= SIM_SCGC3_SPI2_MASK;
		  SPIx = SPI2;
			break;
		default:break;     
	}
	//找出对应的PORT
	switch(pSPI_DataMap->SPI_GPIO_Index)
	{
		case 0:
			SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
			SPI_PORT = PORTA;
			break;
		case 1:
			SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
			SPI_PORT = PORTB;
			break;
		case 2:
			SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
			SPI_PORT = PORTC;
			break;
		case 3:
			SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
			SPI_PORT = PORTD;
			break;
		case 4:
			SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
			SPI_PORT = PORTE;
			break;
		default:break;
	}
	//开启对应的引脚 SCK SOUT SIN
	SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
	SPI_PORT->PCR[pSPI_DataMap->SPI_SIN_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
	SPI_PORT->PCR[pSPI_DataMap->SPI_SOUT_Pin_Index] |= PORT_PCR_MUX(pSPI_DataMap->SPI_Alt_Index);
	/*SCK配置开漏*/
	SPI_PORT->PCR[pSPI_DataMap->SPI_SCK_Pin_Index]|= PORT_PCR_ODE_MASK;
	//配置PCS
	//找出对应的PORT
	switch(pSPI_CSMap->SPI_GPIO_Index)
	{
		case 0:
			SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK;
			SPI_PORT = PORTA;
			break;
		case 1:
			SIM->SCGC5 |= SIM_SCGC5_PORTB_MASK;
			SPI_PORT = PORTB;
			break;
		case 2:
			SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK;
			SPI_PORT = PORTC;
			break;
		case 3:
			SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK;
			SPI_PORT = PORTD;
			break;
		case 4:
			SIM->SCGC5 |= SIM_SCGC5_PORTE_MASK;
			SPI_PORT = PORTE;
			break;
		default:break;
	}
	SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] &= ~PORT_PCR_MUX_MASK;
	SPI_PORT->PCR[pSPI_CSMap->SPI_PCS_Pin_Index] |= PORT_PCR_MUX(pSPI_CSMap->SPI_Alt_Index);
	//设置主从模式
	(SPI_InitStruct->SPI_Mode == SPI_Mode_Master)?(SPIx->MCR  |= SPI_MCR_MSTR_MASK):(SPIx->MCR  &= ~SPI_MCR_MSTR_MASK);
	//配置SPI主模式寄存器
	SPIx->MCR  = 0 & (~SPI_MCR_MDIS_MASK) 
									|SPI_MCR_HALT_MASK        //让SPI进入停止模式
									|SPI_MCR_MSTR_MASK        //配置SPI为主机模式
									|SPI_MCR_PCSIS_MASK       //PCS为高电平当在SPI不工作的时候
									|SPI_MCR_CLR_TXF_MASK     //首先要清除MDIS,清除TXF_MASK和RXF_MASK
									|SPI_MCR_CLR_RXF_MASK  
									|SPI_MCR_DIS_TXF_MASK     //然后再禁止TXD和RXD FIFO 模式 ,将SPI配置成正常模式
									|SPI_MCR_DIS_RXF_MASK
									|SPI_MCR_SMPL_PT(2);
	//配置分频及波特率
	SPIx->CTAR[1] = 0| SPI_CTAR_DBR_MASK	 //设置通信的
									| SPI_CTAR_PCSSCK(0)
									| SPI_CTAR_PASC(0)
									| SPI_CTAR_PBR(0)
									| SPI_CTAR_CSSCK(0)
									| SPI_CTAR_FMSZ(SPI_InitStruct->SPI_DataSize -1) //设置数据传输的位数
									| SPI_CTAR_PDT(0);                                //设置片选信号在数据完成后的延时值 
	//分频设置
	SPIx->CTAR[1] |=SPI_CTAR_BR(SPI_InitStruct->SPI_BaudRatePrescaler);							 
	//时钟相位设置
	(SPI_InitStruct->SPI_CPHA == SPI_CPHA_1Edge)?(SPIx->CTAR[1] &= ~SPI_CTAR_CPHA_MASK):(SPIx->CTAR[1] |= SPI_CTAR_CPHA_MASK);
	//时钟极性
	(SPI_InitStruct->SPI_CPOL == SPI_CPOL_Low)?(SPIx->CTAR[1] &= ~SPI_CTAR_CPOL_MASK):(SPIx->CTAR[1] |= SPI_CTAR_CPOL_MASK);
	//配置MSB或者LSD
	(SPI_InitStruct->SPI_FirstBit == SPI_FirstBit_MSB)?(SPIx->CTAR[1] &= ~SPI_CTAR_LSBFE_MASK):(SPIx->CTAR[1] |= SPI_CTAR_LSBFE_MASK);
	//清空状态
  SPIx->SR = SPI_SR_EOQF_MASK   //队列结束标志 w1c  (write 1 to clear)     
            | SPI_SR_TFUF_MASK    //TX FIFO underflow flag  w1c
            | SPI_SR_TFFF_MASK    //TX FIFO fill      flag  w1c
            | SPI_SR_RFOF_MASK    //RX FIFO overflow  flag  w1c
            | SPI_SR_RFDF_MASK    //RX FIFO fill      flasg w1c (0时为空)
					  | SPI_SR_TCF_MASK;
	//开始传输
	 SPIx->MCR &= ~SPI_MCR_HALT_MASK;    //开始传输,见参考手册1129页
}
Example #3
0
void TWRK40_flexbus_init(void){

/* Enable the FlexBus                                               */
/* Configure the FlexBus Registers for 8-bit port size              */
/*  with multiplexed address and data using chip select 0           */
/* These configurations are specific to communicating with          */ 
/*  the MRAM used in this example                                   */
/* For K40 tower module - use the byte lane shift because there     */  
/*  is a latch on the board which handles multiplexed address/data  */
  
  //Set Base address
	
  FB_CSAR0 = (uint32)&MRAM_START_ADDRESS;

  FB_CSCR0  =   FB_CSCR_BLS_MASK   // set byte lane shift for data on FB_AD[7:0] aka. right justified mode
              | FB_CSCR_PS(1)      // 8-bit port
              | FB_CSCR_AA_MASK    // auto-acknowledge
              | FB_CSCR_ASET(0x1)  // assert chip select on second clock edge after address is asserted
              | FB_CSCR_WS(0x1)    // 1 wait state - may need a wait state depending on the bus speed 
              ;

  FB_CSMR0  =   FB_CSMR_BAM(0x7)  //Set base address mask for 512K address space
              | FB_CSMR_V_MASK    //Enable cs signal
              ;
              
  //enable BE signals - note, not used in this example
  FB_CSPMCR = 0x02200000;

  //fb clock divider 3
   SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x3);
  
  /* Configure the pins needed to FlexBus Function (Alt 5) */
  /* this example uses low drive strength settings         */
  //address/Data
  PORTA_PCR7=PORT_PCR_MUX(5);          //fb_ad[18]
  PORTA_PCR8=PORT_PCR_MUX(5);          //fb_ad[17]
  PORTA_PCR9=PORT_PCR_MUX(5);          //fb_ad[16]
  PORTA_PCR10=PORT_PCR_MUX(5);          //fb_ad[15]
  PORTA_PCR24=PORT_PCR_MUX(5);          //fb_ad[14]
  PORTA_PCR25=PORT_PCR_MUX(5);          //fb_ad[13]
  PORTA_PCR26=PORT_PCR_MUX(5);          //fb_ad[12]
  PORTA_PCR27=PORT_PCR_MUX(5);          //fb_ad[11]
  PORTA_PCR28=PORT_PCR_MUX(5);          //fb_ad[10]
  PORTD_PCR10=PORT_PCR_MUX(5);          //fb_ad[9]
  PORTD_PCR11=PORT_PCR_MUX(5);          //fb_ad[8]
  PORTD_PCR12=PORT_PCR_MUX(5);          //fb_ad[7]
  PORTD_PCR13=PORT_PCR_MUX(5);          //fb_ad[6]
  PORTD_PCR14=PORT_PCR_MUX(5);          //fb_ad[5]
  PORTE_PCR8=PORT_PCR_MUX(5);          //fb_ad[4]
  PORTE_PCR9=PORT_PCR_MUX(5);          //fb_ad[3]
  PORTE_PCR10=PORT_PCR_MUX(5);          //fb_ad[2]
  PORTE_PCR11=PORT_PCR_MUX(5);          //fb_ad[1]
  PORTE_PCR12=PORT_PCR_MUX(5);          //fb_ad[0]
  //control signals
  PORTA_PCR11=PORT_PCR_MUX(5);          //fb_oe_b
  PORTD_PCR15=PORT_PCR_MUX(5);          //fb_rw_b
  PORTE_PCR7=PORT_PCR_MUX(5);          //fb_cs0_b
  PORTE_PCR6=PORT_PCR_MUX(5);          //fb_ale  
}
Example #4
0
// Setup
inline void LCD_setup()
{
	// Register Scan CLI dictionary
	CLI_registerDictionary( lcdCLIDict, lcdCLIDictName );

	// Initialize SPI
	SPI_setup();

	// Setup Register Control Signal (A0)
	// Start in display register mode (1)
	GPIOC_PDDR |= (1<<7);
	PORTC_PCR7 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
	GPIOC_PSOR |= (1<<7);

	// Setup LCD Reset pin (RST)
	// 0 - Reset, 1 - Normal Operation
	// Start in normal mode (1)
	GPIOC_PDDR |= (1<<8);
	PORTC_PCR8 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(1);
	GPIOC_PSOR |= (1<<8);

	// Run LCD intialization sequence
	LCD_initialize();

	// Write default image to LCD
	for ( uint8_t page = 0; page < LCD_TOTAL_VISIBLE_PAGES; page++ )
		LCD_writeDisplayReg( page, (uint8_t*)&STLcdDefaultImage[page * LCD_PAGE_LEN], LCD_PAGE_LEN );

	// Setup Backlight
	SIM_SCGC6 |= SIM_SCGC6_FTM0;
	FTM0_CNT = 0; // Reset counter

	// PWM Period
	// 16-bit maximum
	FTM0_MOD = 0xFFFF;

	// Set FTM to PWM output - Edge Aligned, Low-true pulses
	FTM0_C0SC = 0x24; // MSnB:MSnA = 10, ELSnB:ELSnA = 01
	FTM0_C1SC = 0x24;
	FTM0_C2SC = 0x24;

	// Base FTM clock selection (72 MHz system clock)
	// @ 0xFFFF period, 72 MHz / (0xFFFF * 2) = Actual period
	// Higher pre-scalar will use the most power (also look the best)
	// Pre-scalar calculations
	// 0 -      72 MHz -> 549 Hz
	// 1 -      36 MHz -> 275 Hz
	// 2 -      18 MHz -> 137 Hz
	// 3 -       9 MHz ->  69 Hz (Slightly visible flicker)
	// 4 -   4 500 kHz ->  34 Hz (Visible flickering)
	// 5 -   2 250 kHz ->  17 Hz
	// 6 -   1 125 kHz ->   9 Hz
	// 7 - 562 500  Hz ->   4 Hz
	// Using a higher pre-scalar without flicker is possible but FTM0_MOD will need to be reduced
	// Which will reduce the brightness range

	// System clock, /w prescalar setting
	FTM0_SC = FTM_SC_CLKS(1) | FTM_SC_PS( STLcdBacklightPrescalar_define );

	// Red
	FTM0_C0V = STLcdBacklightRed_define;
	PORTC_PCR1 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(4);

	// Green
	FTM0_C1V = STLcdBacklightGreen_define;
	PORTC_PCR2 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(4);

	// Blue
	FTM0_C2V = STLcdBacklightBlue_define;
	PORTC_PCR3 = PORT_PCR_SRE | PORT_PCR_DSE | PORT_PCR_MUX(4);
}
Example #5
0
File: Cpu.c Project: arulle/CC3501
/*
** ===================================================================
**     Method      :  PE_low_level_init (component MK20DX128EX5)
**
**     Description :
**         Initializes beans and provides common register initialization. 
**         The method is called automatically as a part of the 
**         application initialization code.
**         This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
  #ifdef PEX_RTOS_INIT
    PEX_RTOS_INIT();                   /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */
  #endif
      /* Initialization of the SIM module */
  /* PORTA_PCR4: ISF=0,MUX=7 */
  PORTA_PCR4 = (uint32_t)((PORTA_PCR4 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_MUX(0x07)
               ));
        /* Initialization of the RCM module */
  /* RCM_RPFW: RSTFLTSEL=0 */
  RCM_RPFW &= (uint8_t)~(uint8_t)(RCM_RPFW_RSTFLTSEL(0x1F));
  /* RCM_RPFC: RSTFLTSS=0,RSTFLTSRW=0 */
  RCM_RPFC &= (uint8_t)~(uint8_t)(
               RCM_RPFC_RSTFLTSS_MASK |
               RCM_RPFC_RSTFLTSRW(0x03)
              );
        /* Initialization of the FTFL_FlashConfig module */
      /* Initialization of the PMC module */
  /* PMC_REGSC: ACKISO=0,BGBE=0 */
  PMC_REGSC &= (uint8_t)~(uint8_t)(
                PMC_REGSC_ACKISO_MASK |
                PMC_REGSC_BGBE_MASK
               );
  /* PMC_LVDSC1: LVDACK=1,LVDIE=0,LVDRE=1,LVDV=0 */
  PMC_LVDSC1 = (uint8_t)((PMC_LVDSC1 & (uint8_t)~(uint8_t)(
                PMC_LVDSC1_LVDIE_MASK |
                PMC_LVDSC1_LVDV(0x03)
               )) | (uint8_t)(
                PMC_LVDSC1_LVDACK_MASK |
                PMC_LVDSC1_LVDRE_MASK
               ));
  /* PMC_LVDSC2: LVWACK=1,LVWIE=0,LVWV=0 */
  PMC_LVDSC2 = (uint8_t)((PMC_LVDSC2 & (uint8_t)~(uint8_t)(
                PMC_LVDSC2_LVWIE_MASK |
                PMC_LVDSC2_LVWV(0x03)
               )) | (uint8_t)(
                PMC_LVDSC2_LVWACK_MASK
               ));
  /* SMC_PMPROT: ??=0,??=0,AVLP=0,??=0,ALLS=0,??=0,AVLLS=0,??=0 */
  SMC_PMPROT = 0x00U;                  /* Setup Power mode protection register */
  /* Common initialization of the CPU registers */
  /* NVICIP8: PRI8=0 */
  NVICIP8 = NVIC_IP_PRI8(0x00);
  /* ### InternalI2C "I2C" init code ... */
  I2C_Init();
  /* ### Serial_LDD "IO1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)IO1_Init(NULL);
  /* ### PWM_LDD "PwmLdd1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)PwmLdd1_Init(NULL);
  /* ### PWM_LDD "PwmLdd2" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)PwmLdd2_Init(NULL);
  /* ### PWM_LDD "PwmLdd3" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)PwmLdd3_Init(NULL);
  /* ### RealTime_LDD "RealTimeLdd1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)RealTimeLdd1_Init(NULL);
  /* ### Asynchro serial "Inhr1" init code ... */
  Inhr1_Init();
  /* ###  "AS1" init code ... */
  /* Enable interrupts of the given priority level */
  Cpu_SetBASEPRI(0U);
}
Example #6
0
//============================================================================
//函数名称:CANInit
//函数返回:0:成功;1:失败
//参数说明:
//         CANChannel:模块号
//		   baudrateKHz: 波特率
//         selfLoop: 模式选择(1=回环模式;0=正常模式)
//         idMask: ID过滤(1=ID过滤;0=ID不过滤)
//功能概要:CAN初始化
//============================================================================
uint8 CANInit(uint8 CANChannel,uint32 baudrateKHz,uint8 selfLoop,uint8 idMask)
{
    int8 i;
    CAN_MemMapPtr CANBaseAdd;
  
    //使能FlexCAN外部时钟
    OSC_CR |= OSC_CR_ERCLKEN_MASK | OSC_CR_EREFSTEN_MASK;
    
    //通过模块号选择模块基地址
    if(CANChannel == 0)
        CANBaseAdd = CAN0_BASE_PTR;
    else if(CANChannel == 1)
        CANBaseAdd = CAN1_BASE_PTR;
    
    //使能CAN模块时钟
    if(CANBaseAdd == CAN0_BASE_PTR)
        SIM_SCGC6 |=  SIM_SCGC6_FLEXCAN0_MASK;//使能CAN0的时钟模块
    else
        SIM_SCGC3 |= SIM_SCGC3_FLEXCAN1_MASK;//使能CAN1的时钟模块
    
    //使能CAN中断
    if(CANChannel == 0)//使能CAN0的中断                                              
    {  
        NVICICPR0 = (NVICICPR0 & ~(0x07<<29)) | (0x07<<29);//清除挂载在FlexCAN0的中断  
        NVICISER0 = (NVICISER0 & ~(0x07<<29)) | (0x07<<29);//使能FlexCAN0中断 
        
        NVICICPR1 = (NVICICPR1 & ~(0x1F<<0)) | (0x1F);//清除挂载在FlexCAN0的中断                 
        NVICISER1 = (NVICISER1 & ~(0x1F<<0)) | (0x1F);//使能FlexCAN0中断                      
    }  
    else  //使能CAN1的中断
    {
        NVICICPR1 = (NVICICPR1 & ~(0xFF<<5)) | (0xFF<<5);//清除挂载在FlexCAN1的中断  
        NVICISER1 = (NVICISER1 & ~(0xFF<<5)) | (0xFF<<5);//使能FlexCAN1中断                       
    }

    //配置CAN_RX/TX复用引脚功能
    if(CANChannel == 0)
    {
		PORTA_PCR12 = PORT_PCR_MUX(2) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; //上拉
		PORTA_PCR13 = PORT_PCR_MUX(2) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; //上拉
    }
    else
    {
    	PORTE_PCR24 = PORT_PCR_MUX(2) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; //Tx上拉
    	PORTE_PCR25 = PORT_PCR_MUX(2) | PORT_PCR_PE_MASK | PORT_PCR_PS_MASK; //Rx上拉
    } 
    
    //选择时钟源,外设时钟48MHz,内部时钟:12MHz
    CAN_CTRL1_REG(CANBaseAdd) |= CAN_CTRL1_CLKSRC_MASK;//选择内部时钟    
    
    CAN_MCR_REG(CANBaseAdd) |= CAN_MCR_FRZ_MASK;  //使能冻结模式   
    CAN_MCR_REG(CANBaseAdd) &= ~CAN_MCR_MDIS_MASK;//使能CAN模块
    //确认已退出冻结模式
    while((CAN_MCR_LPMACK_MASK & CAN_MCR_REG(CANBaseAdd)));

    //软件复位
    CAN_MCR_REG(CANBaseAdd) ^= CAN_MCR_SOFTRST_MASK; 
    //等待复位完成
    while(CAN_MCR_SOFTRST_MASK & CAN_MCR_REG(CANBaseAdd));   
    //等待进入冻结模式 
    while(!(CAN_MCR_FRZACK_MASK & CAN_MCR_REG(CANBaseAdd)));
    
    //将16个邮箱缓冲区内容清0
    for(i=0;i<16;i++)
    {
          CANBaseAdd->MB[i].CS = 0x00000000;
          CANBaseAdd->MB[i].ID = 0x00000000;
          CANBaseAdd->MB[i].WORD0 = 0x00000000;
          CANBaseAdd->MB[i].WORD1 = 0x00000000;
    }
    
    //接收邮箱过滤IDE比较,RTR不比较
    CAN_CTRL2_REG(CANBaseAdd) &= ~CAN_CTRL2_EACEN_MASK;
    //远程请求帧产生
    CAN_CTRL2_REG(CANBaseAdd) &= ~CAN_CTRL2_RRS_MASK;
    //邮箱首先从接收FIFO队列匹配然后再在邮箱中匹配
    CAN_CTRL2_REG(CANBaseAdd) &= ~CAN_CTRL2_MRP_MASK;
 
    //使用一个32位过滤器
    CAN_MCR_REG(CANBaseAdd) |= (CAN_MCR_REG(CANBaseAdd) & ~CAN_MCR_IDAM_MASK) | CAN_MCR_IDAM(0);
    //设置波特率
    if(SetCANBand(CANChannel,baudrateKHz) == 1)//若设置错误
        return 1;
    
    //模式选择:回环模式或正常模式
    if(1==selfLoop)
        CAN_CTRL1_REG(CANBaseAdd) |= CAN_CTRL1_LPB_MASK;//使用回环模式

    //初始化掩码寄存器
    if(1==idMask)//屏蔽ID
    {
    	CAN_RXMGMASK_REG(CANBaseAdd) = 0x1FFFFFFF;
		CAN_RX14MASK_REG(CANBaseAdd) = 0x1FFFFFFF;
		CAN_RX15MASK_REG(CANBaseAdd) = 0x1FFFFFFF;
    }
    else//不屏蔽ID
    {
    	CAN_RXMGMASK_REG(CANBaseAdd) = 0x0;
		CAN_RX14MASK_REG(CANBaseAdd) = 0x0;
		CAN_RX15MASK_REG(CANBaseAdd) = 0x0;
    }

    //如果单独掩码功能使能,为每个队列初始化单独的掩码寄存器
    if(CAN_MCR_REG(CANBaseAdd) & CAN_MCR_IRMQ_MASK)
    {
        for(i = 0; i < NUMBER_OF_MB ; i++)
        {        
            CANBaseAdd->RXIMR[i] = 0x1FFFFFFFL;
        }
    }
    
    //只有在冻结模式下才能配置,配置完推出冻结模式
	CAN_MCR_REG(CANBaseAdd) &= ~(CAN_MCR_HALT_MASK);
	//等待直到退出冻结模式
	while( CAN_MCR_REG(CANBaseAdd) & CAN_MCR_FRZACK_MASK);    
	//等到不在冻结模式,休眠模式或者停止模式
	while((CAN_MCR_REG(CANBaseAdd) & CAN_MCR_NOTRDY_MASK));
    
    return 0;
}
Example #7
0
File: spi.c Project: aarzho/k60
/**
 *    @brief  SPI初始化
 * 
 *    @param   spino   SPI通道号
 *    @param   master  是否是主机  
 *    
 *    @return  E_ID    输入序号错误
 *    @return  E_OK    初始化正常
 */
ER spi_init(uint8_t spino, uint8_t master)
{
    if((spino < 0) || (spino > SPI_NO_GET(SPI2)))
    {
        return (E_ID);
    }
    
    SPI_MemMapPtr base_addr = spi_get_base_address(spino);
    
    /* 使能SPI模块时钟,配置SPI引脚功能 */
    if(SPI_MOD_SET(spino) == SPI0)
    {
        SIM_SCGC6 |= SIM_SCGC6_DSPI0_MASK;
        
        /* PORT_PCR_MUX(0x2) : SPI功能
         * PORT_PCR_DSE_MASK : Drive Strength Enable */
        gpio_init(PORT_NO_GET(SD_CS), PIN_NO_GET(SD_CS), OUT_PUT, HIGH_POWER);   /* PCS0 */
        PORTA_PCR15 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SCK */
        PORTA_PCR16 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SOUT */
        PORTA_PCR17 = 0 | PORT_PCR_MUX(0x2);                     /* SIN */
    }
    else if(SPI_MOD_SET(spino) == SPI1)
    {
        SIM_SCGC6 |= SIM_SCGC6_SPI1_MASK;
        PORTE_PCR4 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* PCS0 */
        PORTE_PCR2 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SCK */
        PORTE_PCR1 = 0 | PORT_PCR_MUX(0x2) | PORT_PCR_DSE_MASK; /* SOUT */
        PORTE_PCR3 = 0 | PORT_PCR_MUX(0x2);                     /* SIN */
    }
    else 
    {
        SIM_SCGC3 |= SIM_SCGC3_SPI2_MASK;
    }
    
    SPI_MCR_REG(base_addr) = 0 
                 | SPI_MCR_CLR_TXF_MASK     /* Clear the Tx FIFO counter. */
                 | SPI_MCR_CLR_RXF_MASK     /* Clear the Rx FIFO counter. */
                 | SPI_MCR_HALT_MASK;       /* Starts and stops DSPI transfers */

    /* 根据主从机模式设置工作模式 */
    if(master == MASTER)
    {
        SPI_MCR_REG(base_addr) |= SPI_MCR_MSTR_MASK;   /* Master/Slave Mode Select */
     
        SPI_CTAR_REG(base_addr,0) = 0
                       | SPI_CTAR_DBR_MASK         /* Double Baud Rate */
                       | SPI_CTAR_FMSZ(0x07)       /* Frame Size: 8bit */
                       | SPI_CTAR_PDT_MASK         /* 延时因子为7 */
                       | SPI_CTAR_BR(0x8);         /* Selects the scaler value for the baud rate.  */
                       //| SPI_CTAR_CPOL_MASK;     /* Clock Polarity */
                       //| SPI_CTAR_CPHA_MASK;     /* Clock Phase */
    }
    else
    {
        SPI_CTAR_SLAVE_REG(base_addr,0) = 0 
                            | SPI_CTAR_SLAVE_FMSZ(0x07)
                            | SPI_CTAR_SLAVE_CPOL_MASK 
                            | SPI_CTAR_SLAVE_CPHA_MASK; 
   }
 
   SPI_SR_REG(base_addr) = SPI_SR_EOQF_MASK    /* End of Queue Flag */
                         | SPI_SR_TFUF_MASK      /* Transmit FIFO Underflow Flag */
                         | SPI_SR_TFFF_MASK      /* Transmit FIFO Fill Flag */
                         | SPI_SR_RFOF_MASK      /* Receive FIFO Overflow Flag */
                         | SPI_SR_RFDF_MASK;    /* Receive FIFO Drain Flag */
    
    SPI_MCR_REG(base_addr) &= ~SPI_MCR_HALT_MASK;   /* start */
    
    return (E_OK);
}
void gpio_enable_button_flag(OS_TID task, U16 flags)
{
    // When the "reset" button is pressed the ISR will set the
    // event flags "flags" for task "task"

    // Keep a local copy of task & flags
    //isr_notify=task;
    //isr_flags=flags;

    PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK;
    //sw2 - interrupt on falling edge
    PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK|PORT_PCR_PE_MASK|PORT_PCR_PFE_MASK|PORT_PCR_IRQC(10)|PORT_PCR_MUX(1);

    NVIC_ClearPendingIRQ(PORTB_IRQn);
    NVIC_EnableIRQ(PORTB_IRQn);
}
void PORTB_IRQHandler(void)
{
    if (PIN_nRESET_PORT->ISFR == (1<<PIN_nRESET_BIT))
    {
        PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] |= PORT_PCR_ISF_MASK;
        // Notify a task that the button has been pressed
        // disable interrupt
        PIN_nRESET_PORT->PCR[PIN_nRESET_BIT] = PORT_PCR_PS_MASK|PORT_PCR_PE_MASK|PORT_PCR_PFE_MASK|PORT_PCR_IRQC(00)|PORT_PCR_MUX(1); // IRQ Falling edge

        //isr_evt_set(isr_flags, isr_notify);
    }
}
/* ===================================================================*/
LDD_TDeviceData* AS1_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate device structure */
  AS1_TDeviceDataPtr DeviceDataPrv;
  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;

  /* Clear the receive counters and pointer */
  DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
  DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
  DeviceDataPrv->InpDataPtr = NULL;    /* Clear the buffer pointer for received characters */
  /* Clear the transmit counters and pointer */
  DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
  DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
  DeviceDataPrv->OutDataPtr = NULL;    /* Clear the buffer pointer for data to be transmitted */
  DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
  /* Allocate interrupt vectors */
  /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
  INT_UART0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
  /* SIM_SCGC4: UART0=1 */
  SIM_SCGC4 |= SIM_SCGC4_UART0_MASK;                                   
  /* PORTA_PCR1: ISF=0,MUX=2 */
  PORTA_PCR1 = (uint32_t)((PORTA_PCR1 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x05)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x02)
               ));                                  
  /* PORTE_PCR20: ISF=0,MUX=4 */
  PORTE_PCR20 = (uint32_t)((PORTE_PCR20 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x03)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x04)
                ));                                  
  /* NVIC_IPR3: PRI_12=0x80 */
  NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)(
               NVIC_IP_PRI_12(0x7F)
              )) | (uint32_t)(
               NVIC_IP_PRI_12(0x80)
              ));                                  
  /* NVIC_ISER: SETENA|=0x1000 */
  NVIC_ISER |= NVIC_ISER_SETENA(0x1000);                                   
  UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
  UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
  DeviceDataPrv->SerFlag = 0x00U;      /* Reset flags */
  /* UART0_C1: LOOPS=0,DOZEEN=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
  UART0_C1 = 0x00U;                    /*  Set the C1 register */
  /* UART0_C3: R8T9=0,R9T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
  UART0_C3 = 0x00U;                    /*  Set the C3 register */
  /* UART0_C4: MAEN1=0,MAEN2=0,M10=0,OSR=0 */
  UART0_C4 = UART0_C4_OSR(0x00);       /*  Set the C4 register */
  /* UART0_S2: LBKDIF=0,RXEDGIF=0,MSBF=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
  UART0_S2 = 0x00U;                    /*  Set the S2 register */
  UART0_PDD_SetClockSource(UART0_BASE_PTR, UART0_PDD_PLL_FLL_CLOCK);
  UART0_PDD_SetBaudRate(UART0_BASE_PTR, 137U); /* Set the baud rate register. */
  UART0_PDD_SetOversamplingRatio(UART0_BASE_PTR, 3U);
  UART0_PDD_EnableSamplingOnBothEdges(UART0_BASE_PTR, PDD_ENABLE);
  UART0_PDD_EnableTransmitter(UART0_BASE_PTR, PDD_ENABLE); /* Enable transmitter */
  UART0_PDD_EnableReceiver(UART0_BASE_PTR, PDD_ENABLE); /* Enable receiver */
  UART0_PDD_EnableInterrupt(UART0_BASE_PTR, ( UART0_PDD_INTERRUPT_RECEIVER )); /* Enable interrupts */
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_AS1_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv);
}
Example #11
0
void board_init() {
	uint16_t i,j;
	//enable all port clocks.
	SIM_SCGC5 |= (SIM_SCGC5_PORTA_MASK
			| SIM_SCGC5_PORTB_MASK
			| SIM_SCGC5_PORTC_MASK
			| SIM_SCGC5_PORTD_MASK
			| SIM_SCGC5_PORTE_MASK );


	//init all pins for the radio
	//SLPTR
#ifdef TOWER_K20
	PORTB_PCR3 = PORT_PCR_MUX(1);// -- PTB3 used as gpio for slptr
	GPIOB_PDDR |= RADIO_SLPTR_MASK; //set as output

	//RADIO RST -- TODO in the TWR change it to another pin! this is one of the leds.
	PORTC_PCR9 = PORT_PCR_MUX(1);// -- PTC9 used as gpio for radio rst
	GPIOC_PDDR |= RADIO_RST_MASK; //set as output


#elif OPENMOTE_K20
	PORTD_PCR4 = PORT_PCR_MUX(1);// -- PTD4 used as gpio for slptr
	GPIOD_PDDR |= RADIO_SLPTR_MASK; //set as output

	//RADIO RST 
	PORTD_PCR5 = PORT_PCR_MUX(1);// -- PTD5 used as gpio for radio rst
	GPIOD_PDDR |= RADIO_RST_MASK; //set as output

#endif	

	PORT_PIN_RADIO_RESET_LOW();//activate the radio.

	
	PORT_PIN_RADIO_SLP_TR_CNTL_LOW();
	
	//ptc5 .. ptc5 is pin 62, irq A
	enable_irq(RADIO_EXTERNAL_PORT_IRQ_NUM);//enable the irq. The function is mapped to the vector at position 105 (see manual page 69). The vector is in isr.h

	//external port radio_isr.
	PORTC_PCR5 = PORT_PCR_MUX(1);// -- PTC5 used as gpio for radio isr through llwu
	GPIOC_PDDR &= ~1<<RADIO_ISR_PIN; //set as input ==0
	PORTC_PCR5 |= PORT_PCR_IRQC(0x09); //9 interrupt on raising edge. page 249 of the manual.	
	PORTC_PCR5 |= PORT_PCR_ISF_MASK; //clear any pending interrupt.

	llwu_init();//low leakage unit init - to recover from deep sleep

	debugpins_init();
	leds_init();
	bsp_timer_init();
	uart_init();
	radiotimer_init();
	spi_init();	
	radio_init();
	leds_all_off();
	leds_sync_on();
	leds_radio_on();
	leds_debug_on();
	leds_error_on();
	leds_all_off();
	debugpins_fsm_clr();
}
Example #12
0
 //--------------------------------------------------------------
void cfgPorts(void)
{
    //Turn on clock for portb and portd
    SIM_SCGC5 = SIM_SCGC5_PORTB_MASK;
    SIM_SCGC5 |= SIM_SCGC5_PORTC_MASK;
    SIM_SCGC5 |= SIM_SCGC5_PORTD_MASK;   
      
    /* Set pins of PORTB as GPIO */
    //Connected to LCD
    PORTC_PCR0  = PORT_PCR_MUX(1);
    PORTC_PCR1  = PORT_PCR_MUX(1);
    PORTC_PCR2  = PORT_PCR_MUX(1);
    PORTC_PCR3  = PORT_PCR_MUX(1);
    PORTC_PCR4  = PORT_PCR_MUX(1);
    PORTC_PCR5  = PORT_PCR_MUX(1);
    PORTC_PCR6  = PORT_PCR_MUX(1);
    PORTC_PCR7  = PORT_PCR_MUX(1);
     
    //LCD: RS and Enable
    PORTB_PCR0  = PORT_PCR_MUX(1);
    PORTB_PCR1  = PORT_PCR_MUX(1);
     
    //Leds on board
    PORTB_PCR18 = PORT_PCR_MUX(1);
    PORTB_PCR19 = PORT_PCR_MUX(1);
    PORTD_PCR1  = PORT_PCR_MUX(1);
      
    //Configure all PortB as outputs
    GPIOB_PDDR = 0xFFFFFFFF; //1111 1111 1111 1111 1111 1111 1111 0111
      
    //Configure all PortD as outputs
    GPIOC_PDDR = 0xFFFFFFFF;
     
    //Configure all PortD as outputs
    GPIOD_PDDR = 0xFFFFFFFF;
}
Example #13
0
/******************************************************************************
 *
 *   @name        _pwm_init
 *
 *   @brief       This function initialyzes PWM.
 *
 *   @param       None
 *
 *   @return      None
 *****************************************************************************/
void _pwm_init()
{
#if (defined BSP_M52259DEMO) || (defined BSP_M52259EVB) || (defined BSP_TWRMCF52259)
   VMCF5225_PWM_STRUCT_PTR pwm = &(((VMCF5225_STRUCT_PTR)_PSP_GET_IPSBAR())->PWM);
   VMCF5225_GPIO_STRUCT_PTR gpio = &(((VMCF5225_STRUCT_PTR)_PSP_GET_IPSBAR())->GPIO);
#endif
#if (defined BSP_M52223EVB)
   VMCF5222_PWM_STRUCT_PTR pwm = &(((VMCF5222_STRUCT_PTR)_PSP_GET_IPSBAR())->PWM);
   VMCF5222_GPIO_STRUCT_PTR gpio = &(((VMCF5222_STRUCT_PTR)_PSP_GET_IPSBAR())->GPIO);
#endif
#if(defined BSP_TWRMCF52259)
   duty = &(pwm->PWMDTY[0]);

   /* Init IO for PWM */
   gpio->PTCPAR |= 0x03;

   pwm->PWME = 0;
   /* PCKA = 1: clock A rate = bus clk / 1 = 40MHz*/
   pwm->PWMPRCLK = 0x00;
      
   pwm->PWMPER[0] = 0xFF;
   pwm->PWMDTY[0] = 0x00;

   /* High at begin of period */
   pwm->PWMPOL = 0x2;
   /* chose clock source is A */
   pwm->PWMCLK = 0x00;
   /* No Concatenates */
   pwm->PWMCTL = 0x00;

   /* Enable PWM */
   pwm->PWME = 0x01;
#endif
#if(defined BSP_M52259DEMO)||(defined BSP_M52259EVB)||(defined BSP_M52223EVB)||(defined BSP_M52277EVB)
   /* update duty (channel 1) */
   duty = &(pwm->PWMDTY[1]);
#if(defined BSP_M52277EVB)
   /* Init IO for PWM */
   gpio->PAR_LCDL = 0x200;
#else
   /* Init IO for PWM */
   gpio->PTAPAR |= 0x03;
#endif
   /* Disable PWM */
   pwm->PWME = 0;
   
   /* PCKA = 1: clock A rate = bus clk / 1 = 40MHz*/
   pwm->PWMPRCLK = 0x00;

   pwm->PWMPER[1] = 0xFF;
   pwm->PWMDTY[1] = 0x00;
   
   /* High at begin of period */
   pwm->PWMPOL = 0x02;
   
   /* chose clock source is A */
   pwm->PWMCLK = 0x00;
   
   /* No Concatenates */
   pwm->PWMCTL = 0x00;

   /* Enable PWM */
   pwm->PWME = 0x02;
#endif

/* Initialize PWM module for CFV1 families */
#if (defined BSP_TWRMCF51JE)||(defined BSP_TWRMCF51MM)||(defined BSP_MCF51JMEVB)
#if (defined BSP_TWRMCF51JE)
   VMCF51JE_TPM_STRUCT_PTR tpm = &(((MCF51JE_STRUCT_PTR)_PSP_GET_MBAR())->TPM2);
   VMCF51JE_STRUCT_PTR reg_ptr = _PSP_GET_MBAR();
#endif
#if (defined BSP_TWRMCF51MM)
   VMCF51MM_TPM_STRUCT_PTR tpm = &(((MCF51MM_STRUCT_PTR)_PSP_GET_MBAR())->TPM2);
   VMCF51MM_STRUCT_PTR reg_ptr = _PSP_GET_MBAR();
#endif

#if (defined BSP_MCF51JMEVB)
   VMCF51JM_TPM2_STRUCT_PTR tpm = &(((MCF51JM_STRUCT_PTR)_PSP_GET_MBAR())->TPM2);
   VMCF51JM_STRUCT_PTR reg_ptr = _PSP_GET_MBAR();
   reg_ptr->SIMX.SCGC1 |= MCF51XX_SCGC1_TPM2_MASK;
#else
   reg_ptr->SIM.SCGC1 |= MCF51XX_SCGC1_TPM2_MASK;
#endif

   /* update duty */
   duty = (uint_16*)(&(tpm->TPMxC[0].TPMxCyV));
   tpm->TPMxSC = 0;
   tpm->TPMxMOD = 0xFF;
   tpm->TPMxC[0].TPMxCySC = 0x24;
   tpm->TPMxSC = 0x08;
#endif

/* Initialize PWM module for kinetis families */
#if (defined BSP_TWR_K40X256) || (defined BSP_TWR_K60N512) || (defined BSP_TWR_K53N512)
   duty = (uint_8 *)&(FTM0_C0V);
   /* FTM0_CH0 enable on PTA3 ****/
   PORTC_PCR1 = PORT_PCR_MUX(0x4); 

   /* Enable clock for FTM */
   SIM_SCGC6 |= SIM_SCGC6_FTM0_MASK;

   /* Set FTM mode */
   FTM0_MODE = (FTM_MODE_WPDIS_MASK | FTM_MODE_FTMEN_MASK);
   FTM0_MODE &= ~FTM_MODE_FTMEN_MASK;
   FTM0_SC = 0;
   FTM0_CNTIN = 0x00;

   /* Set FTM modular */
   FTM0_MOD = 0xFF;
   FTM0_QDCTRL &= ~(FTM_QDCTRL_QUADEN_MASK);
   FTM0_COMBINE &= ~(FTM_COMBINE_DECAPEN0_MASK \
      |FTM_COMBINE_DECAPEN1_MASK \
      |FTM_COMBINE_DECAPEN2_MASK \
      |FTM_COMBINE_DECAPEN3_MASK \
      |FTM_COMBINE_COMBINE0_MASK \
      |FTM_COMBINE_COMBINE1_MASK \
      |FTM_COMBINE_COMBINE2_MASK \
      |FTM_COMBINE_COMBINE3_MASK);
   FTM0_C0SC = 0x28;   

   /* Enable FTM */
   FTM0_SC = 0x08;  
#endif
#if (defined BSP_TWRMCF51JF)
   volatile MXC_MemMapPtr mxc;
   volatile FTM_MemMapPtr ftm1;
   
   mxc = MXC_BASE_PTR;
   ftm1 = FTM1_BASE_PTR;
   
   duty = (uint_16_ptr)&(ftm1->CHANNEL[0].CVH);
   
   mxc->PTAPF4 &= ~MXC_PTAPF4_A0(0xF);
   mxc->PTAPF4 |= MXC_PTAPF4_A0(0x4);
   
   /* Init counter value*/
   ftm1->CNTH = 0x00;
   ftm1->CNTL = 0x00;
   /* Set Modulo -> free run mode*/
   ftm1->MODH = 0x00;
   ftm1->MODL = 0xFF;
   
   /* Disable dual capture mode and combine channels */
   ftm1->COMBINE[0] &= ~(FTM_COMBINE_DECAPEN_MASK | FTM_COMBINE_COMBINE_MASK);
   
   /* Select channel 0 to generate PWM signal */
   ftm1->CHANNEL[0].CSC |= FTM_CSC_MSB_MASK;
   ftm1->CHANNEL[0].CSC  |= FTM_CSC_ELSB_MASK;
   ftm1->CHANNEL[0].CSC  &= ~FTM_CSC_ELSA_MASK;
   
   /* Start timer */
   ftm1->SC  = 0x08;
#endif
}
//This should any pin I/O setup
void InitSSD1325_Interface()
{
    PORTD_PCR4 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTC_PCR8 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTA_PCR1 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTB_PCR3 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTB_PCR2 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTC_PCR3 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTC_PCR4 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTA_PCR12 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTA_PCR2 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTC_PCR2 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTD_PCR2 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTD_PCR3 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    PORTD_PCR1 = PORT_PCR_MUX(1) | PORT_PCR_DSE_MASK;
    GPIOD_PDDR |= 1<<4;	//DC Signal
    GPIOC_PDDR |= 1<<8; //RW Signal
    GPIOA_PDDR |= 1<<1;	//E Signal
    GPIOB_PDDR |= (1<<3) | (1<<2);	//Reset and CS signal
    SSD1325_SET_RESET;
    SSD1325_SET_CS;
    SSD1325_CLEAR_DC;
    SSD1325_CLEAR_RW;
    SSD1325_CLEAR_E;
    SetSSD1325_DataBusAsInputs();
}
Example #15
0
void FTM2_CH1_PWM_Start(unsigned long u16DutyCycle)
{
 FTM2_C1V = u16DutyCycle;
 FTM2_PWMCH1_PORT = PORT_PCR_MUX(3); //Enables PWM Output
 FTM2_SC |= FTM_SC_CLKS(1); //System clock on FTM2, start generating PWM
}
void gpio_init(void)
{
    // enable clock to ports
    SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK | SIM_SCGC5_PORTB_MASK;
    
    // configure pin as GPIO
    LED_CONNECTED_PORT->PCR[LED_CONNECTED_BIT] = PORT_PCR_MUX(1);

    // led off - enable output
    LED_CONNECTED_GPIO->PDOR = 1UL << LED_CONNECTED_BIT;
    LED_CONNECTED_GPIO->PDDR = 1UL << LED_CONNECTED_BIT;

    // led on
    LED_CONNECTED_GPIO->PCOR  |= 1UL << LED_CONNECTED_BIT;

#if defined(INTERFACE_GEN_32KHZ)
    // we use PTD6 to generate 32kHz clk
    // ftm0_ch6 (alternate function 4)
    PORTD->PCR[CLK_32K_PIN] = PORT_PCR_MUX(4) | PORT_PCR_DSE_MASK;
    // enable clk for ftm0
    SIM->SCGC6 |= SIM_SCGC6_FTM0_MASK;

    // configure PWM to generate a 32kHz clock used
    // by the RTC module of the target.
    // Choose EDGE-Aligned PWM:  selected when QUADEN=0, DECAPEN=0, COMBINE=0, CPWMS=0, and MSnB=1  (page 964)

    //disable write protection
    FTM0->MODE |= FTM_MODE_WPDIS_MASK;

    //FTMEN is bit 0, need to set to zero so DECAPEN can be set to 0
    FTM0->MODE &= ~FTM_MODE_FTMEN_MASK;

    //QUADEN = 0; DECAPEN = 0; COMBINE = 0; CPWMS = 0; MSnB = 1
    FTM0->QDCTRL &= ~FTM_QDCTRL_QUADEN_MASK;
    FTM0->COMBINE &= ~FTM_COMBINE_DECAPEN3_MASK;
    FTM0->COMBINE &= ~FTM_COMBINE_COMBINE3_MASK;
    FTM0->SC &= ~FTM_SC_CPWMS_MASK;
    FTM0->CONTROLS[6].CnSC |= FTM_CnSC_MSB_MASK;

    // ELSnB:ELSnA = 1:0
    FTM0->CONTROLS[6].CnSC |= FTM_CnSC_ELSB_MASK;
    FTM0->CONTROLS[6].CnSC &= ~FTM_CnSC_ELSA_MASK;

    // set CNT, MOD (period) and CNTIN
    FTM0->CNT = 0x0;
    FTM0->MOD = FTM0_MOD_VALUE;
    FTM0->CNTIN = 0;

    // set pulsewidth to period/2
    FTM0->CONTROLS[6].CnV = FTM0_MOD_VALUE/2;

    // select clock (system core clock)
    FTM0->SC = FTM_SC_PS(0) | FTM_SC_CLKS(1);

    //enable write protection
    FTM0->MODE &= ~FTM_MODE_WPDIS_MASK;
	
#elif defined(INTERFACE_POWER_EN)
    // POWER_EN (PTD5) and VTRG_FAULT_B (PTD7)
    //	VTRG_FAULT_B not currently implemented. Just power the target ;)
	
    // configure pin as GPIO
    PORTD->PCR[POWER_EN_PIN] = PORT_PCR_MUX(1);
	// force always on logic 1
    PTD->PDOR |= 1UL << POWER_EN_PIN;
    PTD->PDDR |= 1UL << POWER_EN_PIN;

#endif
}
Example #17
0
/* ===================================================================*/
LDD_TDeviceData* SM1_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate LDD device structure */
  SM1_TDeviceDataPtr DeviceDataPrv;

  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;
  DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */
  /* Interrupt vector(s) allocation */
  /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
  INT_SPI0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
  DeviceDataPrv->ErrFlag = 0x00U;      /* Clear error flags */
  /* Clear the receive counters and pointer */
  DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
  DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
  DeviceDataPrv->InpDataPtr = NULL;    /* Clear the buffer pointer for received characters */
  /* Clear the transmit counters and pointer */
  DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
  DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
  DeviceDataPrv->OutDataPtr = NULL;    /* Clear the buffer pointer for data to be transmitted */
  DeviceDataPrv->SerFlag = 0x00U;      /* Reset flags */
  /* SIM_SCGC4: SPI0=1 */
  SIM_SCGC4 |= SIM_SCGC4_SPI0_MASK;                                   
  /* Interrupt vector(s) priority setting */
  /* NVIC_IPR2: PRI_10=0x80 */
  NVIC_IPR2 = (uint32_t)((NVIC_IPR2 & (uint32_t)~(uint32_t)(
               NVIC_IP_PRI_10(0x7F)
              )) | (uint32_t)(
               NVIC_IP_PRI_10(0x80)
              ));                                  
  /* NVIC_ISER: SETENA|=0x0400 */
  NVIC_ISER |= NVIC_ISER_SETENA(0x0400);                                   
  /* PORTD_PCR3: ISF=0,MUX=2 */
  PORTD_PCR3 = (uint32_t)((PORTD_PCR3 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x05)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x02)
               ));                                  
  /* PORTD_PCR2: ISF=0,MUX=2 */
  PORTD_PCR2 = (uint32_t)((PORTD_PCR2 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x05)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x02)
               ));                                  
  /* PORTD_PCR1: ISF=0,MUX=2 */
  PORTD_PCR1 = (uint32_t)((PORTD_PCR1 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x05)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x02)
               ));                                  
  /* PORTD_PCR0: ISF=0,MUX=2 */
  PORTD_PCR0 = (uint32_t)((PORTD_PCR0 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x05)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x02)
               ));                                  
  /* SPI0_C1: SPIE=0,SPE=0,SPTIE=0,MSTR=1,CPOL=0,CPHA=0,SSOE=1,LSBFE=0 */
  SPI0_C1 = (SPI_C1_MSTR_MASK | SPI_C1_SSOE_MASK); /* Set configuration register */
  /* SPI0_C2: SPMIE=0,??=0,TXDMAE=0,MODFEN=1,BIDIROE=0,RXDMAE=0,SPISWAI=0,SPC0=0 */
  SPI0_C2 = SPI_C2_MODFEN_MASK;        /* Set configuration register */
  /* SPI0_BR: ??=0,SPPR=4,SPR=6 */
  SPI0_BR = (SPI_BR_SPPR(0x04) | SPI_BR_SPR(0x06)); /* Set baud rate register */
  /* SPI0_C1: SPE=1 */
  SPI0_C1 |= SPI_C1_SPE_MASK;          /* Enable SPI module */
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_SM1_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
/*
 * LPLD_ENET_Init
 * ENET模块初始化,包括PHY收发器初始化,MAC初始化,BD初始化
 * 
 * 参数:
 *    *MACAddress--MAC地址指针
 *
 * 输出:
 *    无
 */
void LPLD_ENET_Init(const uint8* MACAddress)
{
 
  uint16 usData;
 
  //使能ENET时钟
  SIM_SCGC2 |= SIM_SCGC2_ENET_MASK;

  //允许并发访问MPU控制器
  MPU_CESR = 0;         
        
  //缓冲区描述符初始化
  LPLD_ENET_BDInit();
  
  //复位ENET
  ENET_ECR = ENET_ECR_RESET_MASK;

  //等待至少8个时钟周期
  for( usData = 0; usData < 10; usData++ )
  {
    asm( "NOP" );
  }
    
  //初始化MII接口
  LPLD_ENET_MiiInit(periph_clk_khz/1000/*MHz*/);       
        
  //使能中断并设置优先级
  set_irq_priority (76, 6);
  enable_irq(76);           //ENET发送中断
  set_irq_priority (77, 6);
  enable_irq(77);           //ENET接收中断
  //set_irq_priority (78, 6);
  //enable_irq(78);           //ENET错误及其他中断

  //使能GPIO引脚复用功能
  PORTB_PCR0  = PORT_PCR_MUX(4);  //GPIO;//RMII0_MDIO/MII0_MDIO
  PORTB_PCR1  = PORT_PCR_MUX(4);  //GPIO;//RMII0_MDC/MII0_MDC    
  PORTA_PCR14 = PORT_PCR_MUX(4);  //RMII0_CRS_DV/MII0_RXDV
  PORTA_PCR12 = PORT_PCR_MUX(4);  //RMII0_RXD1/MII0_RXD1
  PORTA_PCR13 = PORT_PCR_MUX(4);  //RMII0_RXD0/MII0_RXD0
  PORTA_PCR15 = PORT_PCR_MUX(4);  //RMII0_TXEN/MII0_TXEN
  PORTA_PCR16 = PORT_PCR_MUX(4);  //RMII0_TXD0/MII0_TXD0
  PORTA_PCR17 = PORT_PCR_MUX(4);  //RMII0_TXD1/MII0_TXD1
  
    
  //等待PHY收发器复位完成
  do
  {
    LPLD_ENET_Delay( ENET_LINK_DELAY );
    usData = 0xffff;
    LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_PHYIDR1, &usData );
        
  } while( usData == 0xffff );

#ifdef PHY_PRINT_REG
  printf("PHY_PHYIDR1=0x%X\r\n",usData);
  LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_PHYIDR2, &usData );
  printf("PHY_PHYIDR2=0x%X\r\n",usData); 
  LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_ANLPAR, &usData );
  printf("PHY_ANLPAR=0x%X\r\n",usData);
  LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_ANLPARNP, &usData );
  printf("PHY_ANLPARNP=0x%X\r\n",usData);
  LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_PHYSTS, &usData );
  printf("PHY_PHYSTS=0x%X\r\n",usData);
  LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_MICR, &usData );
  printf("PHY_MICR=0x%X\r\n",usData);
  LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_MISR, &usData );
  printf("PHY_MISR=0x%X\r\n",usData);
#endif 
  
  //开始自动协商
  LPLD_ENET_MiiWrite(CFG_PHY_ADDRESS, PHY_BMCR, ( PHY_BMCR_AN_RESTART | PHY_BMCR_AN_ENABLE ) );

#ifdef PHY_PRINT_REG
  LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_BMCR, &usData );
  printf("PHY_BMCR=0x%X\r\n",usData);
#endif 
  
  //等待自动协商完成
  do
  {
    LPLD_ENET_Delay( ENET_LINK_DELAY );
    LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_BMSR, &usData );

  } while( !( usData & PHY_BMSR_AN_COMPLETE ) );

#ifdef PHY_PRINT_REG
    printf("PHY_BMSR=0x%X\r\n",usData);
#endif 
    
  //根据协商结果设置ENET模块
  LPLD_ENET_MiiRead(CFG_PHY_ADDRESS, PHY_STATUS, &usData );  

#ifdef PHY_PRINT_REG
  printf("PHY_STATUS=0x%X\r\n",usData);
#endif 
  
  //清除单独和组地址哈希寄存器
  ENET_IALR = 0;
  ENET_IAUR = 0;
  ENET_GALR = 0;
  ENET_GAUR = 0;
  
  //设置ENET模块MAC地址
  LPLD_ENET_SetAddress(MACAddress);
    
  //设置接收控制寄存器,最大长度、RMII模式、接收CRC校验等
  ENET_RCR = ENET_RCR_MAX_FL(CFG_ENET_MAX_PACKET_SIZE) | ENET_RCR_MII_MODE_MASK | ENET_RCR_CRCFWD_MASK | ENET_RCR_RMII_MODE_MASK;

  //清除发送接收控制
  ENET_TCR = 0;
        
  //通讯方式设置
  if( usData & PHY_DUPLEX_STATUS )
  {
    //全双工
    ENET_RCR &= (unsigned long)~ENET_RCR_DRT_MASK;
    ENET_TCR |= ENET_TCR_FDEN_MASK;
  }
  else
  {
    //半双工
    ENET_RCR |= ENET_RCR_DRT_MASK;
    ENET_TCR &= (unsigned long)~ENET_TCR_FDEN_MASK;
  }
  
  //通信速率设置
  if( usData & PHY_SPEED_STATUS )
  {
    //10Mbps
    ENET_RCR |= ENET_RCR_RMII_10T_MASK;
  }

  //使用非增强型缓冲区描述符
  ENET_ECR = 0;
  
  
  //设置接收缓冲区长度
  ENET_MRBR = (unsigned short) CFG_ENET_RX_BUFFER_SIZE;

  //指向环形接收缓冲区描述符序列的头地址
  ENET_RDSR = ( unsigned long ) &( xENETRxDescriptors[ 0 ] );

  //指向环形发送缓冲区描述符序列的头地址
  ENET_TDSR = ( unsigned long ) xENETTxDescriptors;

  //清除ENET中断事件
  ENET_EIR = ( unsigned long ) -1;

  //使能中断
  ENET_EIMR = 0 
            | ENET_EIMR_RXF_MASK  //接收中断
            | ENET_EIMR_TXF_MASK  //发送中断
            //ENET中断
            | ENET_EIMR_UN_MASK | ENET_EIMR_RL_MASK | ENET_EIMR_LC_MASK | ENET_EIMR_BABT_MASK | ENET_EIMR_BABR_MASK | ENET_EIMR_EBERR_MASK
            | ENET_EIMR_RXB_MASK
            ;

  //使能ENET模块
  ENET_ECR |= ENET_ECR_ETHEREN_MASK;

  //表明接收缓冲区为空
  ENET_RDAR = ENET_RDAR_RDAR_MASK;
}
Example #19
0
/* ===================================================================*/
LDD_TDeviceData* ASerialLdd3_Init(LDD_TUserData *UserDataPtr)
{
  /* Allocate device structure */
  ASerialLdd3_TDeviceDataPtr DeviceDataPrv;
  /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;

  /* Clear the receive counters and pointer */
  DeviceDataPrv->InpRecvDataNum = 0x00U; /* Clear the counter of received characters */
  DeviceDataPrv->InpDataNumReq = 0x00U; /* Clear the counter of characters to receive by ReceiveBlock() */
  DeviceDataPrv->InpDataPtr = NULL;    /* Clear the buffer pointer for received characters */
  /* Clear the transmit counters and pointer */
  DeviceDataPrv->OutSentDataNum = 0x00U; /* Clear the counter of sent characters */
  DeviceDataPrv->OutDataNumReq = 0x00U; /* Clear the counter of characters to be send by SendBlock() */
  DeviceDataPrv->OutDataPtr = NULL;    /* Clear the buffer pointer for data to be transmitted */
  DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
  /* Allocate interrupt vectors */
  /* {Bareboard RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
  INT_UART1__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv;
  /* SIM_SCGC4: UART1=1 */
  SIM_SCGC4 |= SIM_SCGC4_UART1_MASK;
  /* PORTC_PCR3: ISF=0,MUX=3 */
  PORTC_PCR3 = (uint32_t)((PORTC_PCR3 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x04)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x03)
               ));
  /* PORTE_PCR0: ISF=0,MUX=3 */
  PORTE_PCR0 = (uint32_t)((PORTE_PCR0 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x04)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x03)
               ));
  /* NVIC_IPR3: PRI_13=0x80 */
  NVIC_IPR3 = (uint32_t)((NVIC_IPR3 & (uint32_t)~(uint32_t)(
               NVIC_IP_PRI_13(0x7F)
              )) | (uint32_t)(
               NVIC_IP_PRI_13(0x80)
              ));
  /* NVIC_ISER: SETENA|=0x2000 */
  NVIC_ISER |= NVIC_ISER_SETENA(0x2000);
  UART_PDD_EnableTransmitter(UART1_BASE_PTR, PDD_DISABLE); /* Disable transmitter. */
  UART_PDD_EnableReceiver(UART1_BASE_PTR, PDD_DISABLE); /* Disable receiver. */
  DeviceDataPrv->SerFlag = 0x00U;      /* Reset flags */
  DeviceDataPrv->ErrFlag = 0x00U;      /* Reset error flags */
  /* UART1_C1: LOOPS=0,UARTSWAI=0,RSRC=0,M=0,WAKE=0,ILT=0,PE=0,PT=0 */
  UART1_C1 = 0x00U;                    /*  Set the C1 register */
  /* UART1_C3: R8=0,T8=0,TXDIR=0,TXINV=0,ORIE=0,NEIE=0,FEIE=0,PEIE=0 */
  UART1_C3 = 0x00U;                    /*  Set the C3 register */
  /* UART1_S2: LBKDIF=0,RXEDGIF=0,??=0,RXINV=0,RWUID=0,BRK13=0,LBKDE=0,RAF=0 */
  UART1_S2 = 0x00U;                    /*  Set the S2 register */
  UART_PDD_SetBaudRate(UART1_BASE_PTR, 48U); /* Set the baud rate register. */
  UART_PDD_EnableTransmitter(UART1_BASE_PTR, PDD_ENABLE); /* Enable transmitter */
  UART_PDD_EnableReceiver(UART1_BASE_PTR, PDD_ENABLE); /* Enable receiver */
  UART_PDD_EnableInterrupt(UART1_BASE_PTR, ( UART_PDD_INTERRUPT_RECEIVER | UART_PDD_INTERRUPT_PARITY_ERROR | UART_PDD_INTERRUPT_FRAMING_ERROR | UART_PDD_INTERRUPT_NOISE_ERROR | UART_PDD_INTERRUPT_OVERRUN_ERROR )); /* Enable interrupts */
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ASerialLdd3_ID,DeviceDataPrv);
  return ((LDD_TDeviceData *)DeviceDataPrv);
}
Example #20
0
/*lint -esym(765,Cpu_Interrupt) Disable MISRA rule (8.10) checking for symbols (Cpu_Interrupt). */
void __init_hardware(void)
{

  /*** !!! Here you can place your own code before PE initialization using property "User code before PE initialization" on the build options tab. !!! ***/

  /*** ### MKL26Z128VFT4 "Cpu" init code ... ***/
  /*** PE initialization code after reset ***/
  SCB_VTOR = (uint32_t)(&__vect_table); /* Set the interrupt vector table position */
  /* Disable the WDOG module */
  /* SIM_COPC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,COPT=0,COPCLKS=0,COPW=0 */
  SIM_COPC = SIM_COPC_COPT(0x00);

  /* System clock initialization */
  /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=3,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x03)); /* Set the system prescalers to safe value */
  /* SIM_SCGC5: PORTE=1,PORTD=1,PORTC=1,PORTB=1,PORTA=1 */
  SIM_SCGC5 |= SIM_SCGC5_PORTE_MASK |
               SIM_SCGC5_PORTD_MASK |
               SIM_SCGC5_PORTC_MASK |
               SIM_SCGC5_PORTB_MASK |
               SIM_SCGC5_PORTA_MASK;   /* Enable clock gate for ports to enable pin routing */
  if ((PMC_REGSC & PMC_REGSC_ACKISO_MASK) != 0x0U) {
    /* PMC_REGSC: ACKISO=1 */
    PMC_REGSC |= PMC_REGSC_ACKISO_MASK; /* Release IO pads after wakeup from VLLS mode. */
  }
  /* SIM_CLKDIV1: OUTDIV1=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,OUTDIV4=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  SIM_CLKDIV1 = (SIM_CLKDIV1_OUTDIV1(0x00) | SIM_CLKDIV1_OUTDIV4(0x00)); /* Update system prescalers */
  /* SIM_SOPT2: PLLFLLSEL=0 */
  SIM_SOPT2 &= (uint32_t)~(uint32_t)(SIM_SOPT2_PLLFLLSEL_MASK); /* Select FLL as a clock source for various peripherals */
  /* SIM_SOPT1: OSC32KSEL=0 */
  SIM_SOPT1 &= (uint32_t)~(uint32_t)(SIM_SOPT1_OSC32KSEL(0x03)); /* System oscillator drives 32 kHz clock for various peripherals */
  /* SIM_SOPT2: TPMSRC=1 */
  SIM_SOPT2 = (uint32_t)((SIM_SOPT2 & (uint32_t)~(uint32_t)(
               SIM_SOPT2_TPMSRC(0x02)
              )) | (uint32_t)(
               SIM_SOPT2_TPMSRC(0x01)
              ));                      /* Set the TPM clock */
  /* PORTA_PCR18: ISF=0,MUX=0 */
  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
  /* PORTA_PCR19: ISF=0,MUX=0 */
  PORTA_PCR19 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
  /* Switch to FEE Mode */
  /* MCG_C2: LOCRE0=0,RANGE0=0,HGO0=0,EREFS0=1,LP=0,IRCS=0 */
  MCG_C2 = (uint8_t)((MCG_C2 & (uint8_t)~(uint8_t)(
            MCG_C2_LOCRE0_MASK |
            MCG_C2_RANGE0(0x03) |
            MCG_C2_HGO0_MASK |
            MCG_C2_LP_MASK |
            MCG_C2_IRCS_MASK
           )) | (uint8_t)(
            MCG_C2_EREFS0_MASK
           ));
  /* OSC0_CR: ERCLKEN=1,??=0,EREFSTEN=0,??=0,SC2P=0,SC4P=0,SC8P=0,SC16P=0 */
  OSC0_CR = OSC_CR_ERCLKEN_MASK;
  /* MCG_C1: CLKS=0,FRDIV=0,IREFS=0,IRCLKEN=1,IREFSTEN=0 */
  MCG_C1 = (MCG_C1_CLKS(0x00) | MCG_C1_FRDIV(0x00) | MCG_C1_IRCLKEN_MASK);
  /* MCG_C4: DMX32=0,DRST_DRS=0 */
  MCG_C4 &= (uint8_t)~(uint8_t)((MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS(0x03)));
  /* MCG_C5: ??=0,PLLCLKEN0=0,PLLSTEN0=0,PRDIV0=0 */
  MCG_C5 = MCG_C5_PRDIV0(0x00);
  /* MCG_C6: LOLIE0=0,PLLS=0,CME0=0,VDIV0=0 */
  MCG_C6 = MCG_C6_VDIV0(0x00);
  while((MCG_S & MCG_S_IREFST_MASK) != 0x00U) { /* Check that the source of the FLL reference clock is the external reference clock. */
  }
  while((MCG_S & 0x0CU) != 0x00U) {    /* Wait until output of the FLL is selected */
  }
  /*** End of PE initialization code after reset ***/

  /*** !!! Here you can place your own code after PE initialization using property "User code after PE initialization" on the build options tab. !!! ***/

}
/*
 * LPLD_I2C_Init
 * I2C通用初始化函数
 * 
 * 参数:
 *    i2cx--选择I2C模块号
 *      |__I2C0           --I2C0号模块
 *      |__I2C1           --I2C1号模块
 *    port--通道端口位选择
 *      |__0              --I2C0(PTB2-I2C0_SCL PTB3-I2C0_SDA)
 *      |                 --I2C1(PTE0-I2C1_SDA PTE1-I2C1_SCL)
 *      |__1              --I2C0(PTD8-I2C0_SCL PTD9-I2C0_SDA)
 *      |                 --I2C1(PTC10-I2C1_SCL PTC11-I2C1_SDA)
 *    scl_frq--选择IIC SCL频率
 *      |__I2C_SCL_50KHZ  --50khz
 *      |__I2C_SCL_100KHZ --100khz
 *      |__I2C_SCL_150KHZ --150khz
 *      |__I2C_SCL_200KHZ --200khz
 *      |__I2C_SCL_250KHZ --250khz
 *      |__I2C_SCL_300KHZ --300khz
 * 输出:
 *    0--配置错误
 *    1--配置成功
 */
uint8 LPLD_I2C_Init(I2Cx i2cx, uint8 port, uint8 scl_frq)
{
  uint8 ps; 
  
  //参数检查
  ASSERT( i2cx <= I2C1);                            //判断I2Cx模块号
  ASSERT( scl_frq <= I2C_SCL_300KHZ);               //判断SCL频率
  ASSERT( port <= 1);                               //判断端口选择
  
  //总线频率50mhz
  //scl_frq=50mhz/(mul * scl div)
  if(scl_frq == I2C_SCL_50KHZ)
  {
    ps=0x33;
  }
  else if(scl_frq == I2C_SCL_100KHZ)
  {
    ps=0x2B;
  }
  else if(scl_frq == I2C_SCL_150KHZ)
  {
    ps=0x28;
  }
  else if(scl_frq == I2C_SCL_200KHZ)
  {
    ps=0x23;
  }
  else if(scl_frq == I2C_SCL_250KHZ)
  {
    ps=0x21;
  }
  else if(scl_frq == I2C_SCL_300KHZ)
  {
    ps=0x20;
  }
  else
    return 0;

  if(i2cx==I2C0)
  {
    if(!port)
    {
      /* configure GPIO for I2C0 function */
      PORTB_PCR2 = PORT_PCR_MUX(2);
      PORTB_PCR3 = PORT_PCR_MUX(2);   
    }
    else if(port==1)
    {
      /* configure GPIO for I2C0 function */
      PORTD_PCR8 = PORT_PCR_MUX(2);
      PORTD_PCR9 = PORT_PCR_MUX(2);   
    }
    else
      return 0;
    
    SIM_SCGC4 |= SIM_SCGC4_I2C0_MASK; //开启I2C0时钟
  }
  else if(i2cx==I2C1)
  {
    if(!port)
    {
      /* configure GPIO for I2C0 function */
      PORTE_PCR0 = PORT_PCR_MUX(6);
      PORTE_PCR1 = PORT_PCR_MUX(6);   
    }
    else if(port==1)
    {
      /* configure GPIO for I2C0 function */
      PORTC_PCR10 = PORT_PCR_MUX(2);
      PORTC_PCR11 = PORT_PCR_MUX(2);   
    }
    else
      return 0;
    
    SIM_SCGC4 |= SIM_SCGC4_I2C1_MASK; //开启IIC1时钟
  }
  else
    return 0;
  
  I2C_F_REG(I2Cx_Ptr[i2cx]) = ps;
  I2C_C1_REG(I2Cx_Ptr[i2cx]) = I2C_C1_IICEN_MASK;      //使能I2Cx
  
  return 1;
}
Example #22
0
/*
** ===================================================================
**     Method      :  PE_low_level_init (component MKL26Z128FT4)
**
**     Description :
**         Initializes beans and provides common register initialization. 
**         The method is called automatically as a part of the 
**         application initialization code.
**         This method is internal. It is used by Processor Expert only.
** ===================================================================
*/
void PE_low_level_init(void)
{
  #ifdef PEX_RTOS_INIT
    PEX_RTOS_INIT();                   /* Initialization of the selected RTOS. Macro is defined by the RTOS component. */
  #endif
      /* Initialization of the SIM module */
  /* PORTA_PCR4: ISF=0,MUX=7 */
  PORTA_PCR4 = (uint32_t)((PORTA_PCR4 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_MUX(0x07)
               ));
        /* Initialization of the FTFL_FlashConfig module */
      /* Initialization of the PMC module */
  /* PMC_LVDSC1: LVDACK=1,LVDIE=0,LVDRE=1,LVDV=0 */
  PMC_LVDSC1 = (uint8_t)((PMC_LVDSC1 & (uint8_t)~(uint8_t)(
                PMC_LVDSC1_LVDIE_MASK |
                PMC_LVDSC1_LVDV(0x03)
               )) | (uint8_t)(
                PMC_LVDSC1_LVDACK_MASK |
                PMC_LVDSC1_LVDRE_MASK
               ));
  /* PMC_LVDSC2: LVWACK=1,LVWIE=0,LVWV=0 */
  PMC_LVDSC2 = (uint8_t)((PMC_LVDSC2 & (uint8_t)~(uint8_t)(
                PMC_LVDSC2_LVWIE_MASK |
                PMC_LVDSC2_LVWV(0x03)
               )) | (uint8_t)(
                PMC_LVDSC2_LVWACK_MASK
               ));
  /* PMC_REGSC: BGEN=0,ACKISO=0,BGBE=0 */
  PMC_REGSC &= (uint8_t)~(uint8_t)(
                PMC_REGSC_BGEN_MASK |
                PMC_REGSC_ACKISO_MASK |
                PMC_REGSC_BGBE_MASK
               );
  /* SMC_PMPROT: ??=0,??=0,AVLP=0,??=0,ALLS=0,??=0,AVLLS=0,??=0 */
  SMC_PMPROT = 0x00U;                  /* Setup Power mode protection register */
  /* Common initialization of the CPU registers */
  /* PORTD_ISFR: ISF=0xD2 */
  PORTD_ISFR = PORT_ISFR_ISF(0xD2);
  /* Common initialization of the CPU registers */
  /* PORTD_PCR1: ISF=0,IRQC=0x0B,PE=1 */
  PORTD_PCR1 = (uint32_t)((PORTD_PCR1 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_IRQC(0x04)
               )) | (uint32_t)(
                PORT_PCR_IRQC(0x0B) |
                PORT_PCR_PE_MASK
               ));
  /* PORTD_PCR2: ISF=0,PE=1,PS=1 */
  PORTD_PCR2 = (uint32_t)((PORTD_PCR2 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_PE_MASK |
                PORT_PCR_PS_MASK
               ));
  /* PORTD_PCR4: ISF=0,IRQC=0x0B,PE=1 */
  PORTD_PCR4 = (uint32_t)((PORTD_PCR4 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_IRQC(0x04)
               )) | (uint32_t)(
                PORT_PCR_IRQC(0x0B) |
                PORT_PCR_PE_MASK
               ));
  /* PORTD_PCR5: ISF=0,PE=1 */
  PORTD_PCR5 = (uint32_t)((PORTD_PCR5 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_PE_MASK
               ));
  /* PORTD_PCR6: ISF=0,IRQC=0x0B,DSE=0,PE=1 */
  PORTD_PCR6 = (uint32_t)((PORTD_PCR6 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_IRQC(0x04) |
                PORT_PCR_DSE_MASK
               )) | (uint32_t)(
                PORT_PCR_IRQC(0x0B) |
                PORT_PCR_PE_MASK
               ));
  /* PORTD_PCR7: ISF=0,IRQC=0x0B,DSE=0,PE=1 */
  PORTD_PCR7 = (uint32_t)((PORTD_PCR7 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_IRQC(0x04) |
                PORT_PCR_DSE_MASK
               )) | (uint32_t)(
                PORT_PCR_IRQC(0x0B) |
                PORT_PCR_PE_MASK
               ));
  /* NVIC_ISER: SETENA|=0x80000040 */
  NVIC_ISER |= NVIC_ISER_SETENA(0x80000040);
  /* NVIC_IPR7: PRI_31=0 */
  NVIC_IPR7 &= (uint32_t)~(uint32_t)(NVIC_IP_PRI_31(0xFF));
  /* PORTC_PCR3: ISF=0,PE=1 */
  PORTC_PCR3 = (uint32_t)((PORTC_PCR3 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_PE_MASK
               ));
  /* PORTC_PCR5: ISF=0,PE=1,PS=1 */
  PORTC_PCR5 = (uint32_t)((PORTC_PCR5 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_PE_MASK |
                PORT_PCR_PS_MASK
               ));
  /* NVIC_IPR5: PRI_21=0,PRI_20=0 */
  NVIC_IPR5 &= (uint32_t)~(uint32_t)(
                NVIC_IP_PRI_21(0xFF) |
                NVIC_IP_PRI_20(0xFF)
               );
  /* PORTB_PCR0: ISF=0,PE=1,PS=1 */
  PORTB_PCR0 = (uint32_t)((PORTB_PCR0 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_PE_MASK |
                PORT_PCR_PS_MASK
               ));
  /* PORTB_PCR1: ISF=0,PE=1,PS=1 */
  PORTB_PCR1 = (uint32_t)((PORTB_PCR1 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK
               )) | (uint32_t)(
                PORT_PCR_PE_MASK |
                PORT_PCR_PS_MASK
               ));
  /* NVIC_IPR1: PRI_6=0 */
  NVIC_IPR1 &= (uint32_t)~(uint32_t)(NVIC_IP_PRI_6(0xFF));
  /* ### FreeRTOS "FRTOS1" init code ... */

#if configSYSTICK_USE_LOW_POWER_TIMER
  /* enable clocking for low power timer, otherwise vPortStopTickTimer() will crash */
  SIM_SCGC5 |= SIM_SCGC5_LPTMR_MASK; /* SIM_SCGC5: LPTMR=1 */
#endif
  vPortStopTickTimer(); /* tick timer shall not run until the RTOS scheduler is started */
  /* ### Serial_LDD "IO1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)IO1_Init(NULL);
  /* ### Init_GPIO "PTD" init code ... */
  PTD_Init();
  /* ### BitIO_LDD "StartStopButton" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)StartStopButton_Init(NULL);
  /* ### BitIO_LDD "BitIoLdd1" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)BitIoLdd1_Init(NULL);
  /* ### BitIO_LDD "BitIoLdd2" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)BitIoLdd2_Init(NULL);
  /* ### BitIO_LDD "BitIoLdd3" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)BitIoLdd3_Init(NULL);
  /* ### BitIO_LDD "BitIoLdd4" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)BitIoLdd4_Init(NULL);
  /* ### BitIO_LDD "BitIoLdd5" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)BitIoLdd5_Init(NULL);
  /* ### BitIO_LDD "ModeButton" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)ModeButton_Init(NULL);
  /* ### Init_GPIO "PTC" init code ... */
  PTC_Init();
  /* ### BitIO_LDD "BitIoLdd6" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)BitIoLdd6_Init(NULL);
  /* ### BitIO_LDD "EncoderA" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)EncoderA_Init(NULL);
  /* ### BitIO_LDD "EncoderB" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)EncoderB_Init(NULL);
  /* ### BitIO_LDD "PreampEnable" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)PreampEnable_Init(NULL);
  /* ### Init_SRTC "RTC" init code ... */
  RTC_Init();
  /* ### Init_GPIO "PTB" init code ... */
  PTB_Init();
  /* ### DMATransfer_LDD "SSI1_TxDMA" component auto initialization. Auto initialization feature can be disabled by component's property "Auto initialization". */
  (void)SSI1_TxDMA_Init(NULL);
  /* ### BitIO_LDD "BitIoLdd7" component auto initialization. Auto initialization feature can be disabled by component property "Auto initialization". */
  (void)BitIoLdd7_Init(NULL);
}
Example #23
0
/*
 * LPLD_UART_Init
 * 初始化UART通道、波特率、发送接收引脚
 * 
 * 参数:
 *    uart_init_structure--UART初始化结构体,
 *                        具体定义见UART_InitTypeDef
 *
 * 输出:
 *    无
 *
 */
void LPLD_UART_Init(UART_InitTypeDef uart_init_structure)
{
  register uint16 sbr, brfa;
  uint32 sysclk;
  uint8 temp, x;
  UART_Type *uartx = uart_init_structure.UART_Uartx;
  uint32 baud = uart_init_structure.UART_BaudRate;
  PortPinsEnum_Type tx_pin = uart_init_structure.UART_TxPin;
  PortPinsEnum_Type rx_pin = uart_init_structure.UART_RxPin;
  UART_ISR_CALLBACK rx_isr = uart_init_structure.UART_RxIsr;
  UART_ISR_CALLBACK tx_isr = uart_init_structure.UART_TxIsr;
  
  if(baud == NULL)
  {
    baud = 9600;
  }
  
  //使能选中的UART串口通道时钟,相应GPIO的UART复用功能   
  if(uartx == UART0)
  {
    x = 0;
    sysclk = g_core_clock;
    SIM->SCGC4 |= SIM_SCGC4_UART0_MASK;
    
    if(tx_pin == PTA2)
      PORTA->PCR[2] = PORT_PCR_MUX(2); 
    else if(tx_pin == PTA14)
      PORTA->PCR[14] = PORT_PCR_MUX(3); 
    else
      PORTB->PCR[17] = PORT_PCR_MUX(3); 
    
    if(rx_pin == PTA1)
      PORTA->PCR[1] = PORT_PCR_MUX(2); 
    else if(rx_pin == PTA15)
      PORTA->PCR[15] = PORT_PCR_MUX(3); 
    else
      PORTB->PCR[16] = PORT_PCR_MUX(3); 
  }
  else
  {
    if (uartx == UART1)
    {
      x = 1;
      sysclk = g_core_clock;
      SIM->SCGC4 |= SIM_SCGC4_UART1_MASK;
      
      if(tx_pin == PTE0)   
        PORTE->PCR[0] = PORT_PCR_MUX(3); 
      else
        PORTC->PCR[4] = PORT_PCR_MUX(3); 
      
      if(rx_pin == PTE1)
        PORTE->PCR[1] = PORT_PCR_MUX(3); 
      else
        PORTC->PCR[3] = PORT_PCR_MUX(3); 
    }
    else
    {
      sysclk = g_bus_clock;
      if (uartx == UART2)
      {
        x = 2;
        SIM->SCGC4 |= SIM_SCGC4_UART2_MASK;
        
        PORTD->PCR[3] = PORT_PCR_MUX(3); 
        PORTD->PCR[2] = PORT_PCR_MUX(3);
      }
      else
      {
        if(uartx == UART3)
        {
          x = 3;
          SIM->SCGC4 |= SIM_SCGC4_UART3_MASK;
          
          if(tx_pin == PTE4)
            PORTE->PCR[4] = PORT_PCR_MUX(3); 
          else if(tx_pin == PTB11)
            PORTB->PCR[11] = PORT_PCR_MUX(3); 
          else 
            PORTC->PCR[17] = PORT_PCR_MUX(3); 
          
          if(rx_pin == PTE5)
            PORTE->PCR[5] = PORT_PCR_MUX(3); 
          else if(rx_pin == PTB10)
            PORTB->PCR[10] = PORT_PCR_MUX(3); 
          else
            PORTC->PCR[16] = PORT_PCR_MUX(3);
        }
        else
        {
          if(uartx == UART4)
          {
            x = 4;
            SIM->SCGC1 |= SIM_SCGC1_UART4_MASK;
            
            if(tx_pin == PTE24)
              PORTE->PCR[24] = PORT_PCR_MUX(3); 
            else
              PORTC->PCR[15] = PORT_PCR_MUX(3); 
            
            if(rx_pin == PTE25)
              PORTE->PCR[25] = PORT_PCR_MUX(3); 
            else
              PORTC->PCR[14] = PORT_PCR_MUX(3);
          }
          else
          {
            x = 5;
            uartx = UART5;
            SIM->SCGC1 |= SIM_SCGC1_UART5_MASK;
            
            if(tx_pin == PTD9)
              PORTD->PCR[9] = PORT_PCR_MUX(3); 
            else
              PORTE->PCR[8] = PORT_PCR_MUX(3); 
            
            if(rx_pin == PTD8)
              PORTD->PCR[8] = PORT_PCR_MUX(3); 
            else
              PORTE->PCR[9] = PORT_PCR_MUX(3); 
          }
        }
      }
    }
  }
  
  //在配置好其他寄存器前,先关闭发送器和接收器
  uartx->C2 &= ~(UART_C2_TE_MASK | UART_C2_RE_MASK );
  
  //配置UART为 8位, 无奇偶校验 */
  uartx->C1 = 0;	
  
  //计算波特率
  sbr = (uint16)((sysclk)/(baud * 16));
  
  //保存UARTx_BDH寄存器中除了SBR的值
  temp = uartx->BDH & ~(UART_BDH_SBR(0x1F));
  
  uartx->BDH = temp |  UART_BDH_SBR(((sbr & 0x1F00) >> 8));
  uartx->BDL = (uint8)(sbr & UART_BDL_SBR_MASK);
  
  //配置波特率的微调分数
  brfa = (((sysclk*32)/(baud * 16)) - (sbr * 32));
  
  //保存UARTx_C4寄存器中除了BRFA的值
  temp = uartx->C4 & ~(UART_C4_BRFA(0x1F));
  
  uartx->C4 = temp |  UART_C4_BRFA(brfa);    
  
  //配置发送接收中断
  if(uart_init_structure.UART_RxIntEnable == TRUE && rx_isr != NULL)
  {
    uartx->C2 |= UART_C2_RIE_MASK; 
    UART_R_ISR[x] = rx_isr;
  } 
  else
  {
    uartx->C2 &= ~(UART_C2_RIE_MASK); 
  }
  if(uart_init_structure.UART_TxIntEnable == TRUE && tx_isr != NULL)
  {
    uartx->C2 |= UART_C2_TIE_MASK; 
    UART_T_ISR[x] = tx_isr;
  } 
  else
  {
    uartx->C2 &= ~(UART_C2_TIE_MASK); 
  }
  
  //使能发送器和接收器
  uartx->C2 |= (UART_C2_TE_MASK | UART_C2_RE_MASK );    
}
Example #24
0
void DistSensConfig (){
	PORTD_PCR5 = PORT_PCR_MUX(0);
	PORTD_PCR6 = PORT_PCR_MUX(0);
	
	
}
Example #25
0
/* ===================================================================*/
LDD_TDeviceData* ETH1_Init(LDD_TUserData *UserDataPtr)
{
  ETH1_TDeviceData *DeviceDataPrv;
  ETH1_TTxQueueItem *TxQueueItemPtr;
  ETH1_TRxQueueItem *RxQueueItemPtr;
  uint8_t* MemPtr;
  /* Allocate internal device data structure */
  /* {FreeRTOS RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
  DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;

  DeviceDataPrv->DuplexMode = LDD_ETH_FULL_DUPLEX; /* Store duplex mode configuration */
  DeviceDataPrv->FilterMode = LDD_ETH_ACCEPT_BC; /* Store filter mode configuration */
  DeviceDataPrv->SleepMode = LDD_ETH_DISABLED; /* Store sleep mode configuration */
  DeviceDataPrv->UserDataPtr = UserDataPtr; /* Store the RTOS device structure */
  DeviceDataPrv->Index = 0U;           /* Set the component instance index */
  DeviceDataPrv->EventMask =           /* Initialize the event mask */
    LDD_ETH_ON_FRAME_TRANSMITTED |
    LDD_ETH_ON_FRAME_RECEIVED |
    LDD_ETH_ON_FATAL_ERROR |0U;
  DeviceDataPrv->EnabledMode = TRUE;   /* Enable the device clock configuration */
  /* SIM_SCGC2: ENET=1 */
  SIM_SCGC2 |= SIM_SCGC2_ENET_MASK;
  ENET_PDD_DisableDevice(ENET_BASE_PTR);
  DeviceDataPrv->Enabled = FALSE;
  ENET_PDD_EnableMIBCounters(ENET_BASE_PTR, FALSE); /* Disable statistic counters */
  ENET_PDD_ClearMIBCounters(ENET_BASE_PTR); /* Clear statistic  counters */
  ENET_PDD_EnableMIBCounters(ENET_BASE_PTR, TRUE); /* Enable statistic counters */
  /* Set pin assignments */
  /* PORTB_PCR1: ISF=0,MUX=4 */
  PORTB_PCR1 = (uint32_t)((PORTB_PCR1 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x03)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x04)
               ));
  /* PORTB_PCR0: ISF=0,MUX=4 */
  PORTB_PCR0 = (uint32_t)((PORTB_PCR0 & (uint32_t)~(uint32_t)(
                PORT_PCR_ISF_MASK |
                PORT_PCR_MUX(0x03)
               )) | (uint32_t)(
                PORT_PCR_MUX(0x04)
               ));
  /* PORTA_PCR18: ISF=0,MUX=0 */
  PORTA_PCR18 &= (uint32_t)~(uint32_t)((PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x07)));
  /* PORTA_PCR16: ISF=0,MUX=4 */
  PORTA_PCR16 = (uint32_t)((PORTA_PCR16 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x03)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x04)
                ));
  /* PORTA_PCR17: ISF=0,MUX=4 */
  PORTA_PCR17 = (uint32_t)((PORTA_PCR17 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x03)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x04)
                ));
  /* PORTA_PCR15: ISF=0,MUX=4 */
  PORTA_PCR15 = (uint32_t)((PORTA_PCR15 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x03)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x04)
                ));
  /* PORTA_PCR14: ISF=0,MUX=4 */
  PORTA_PCR14 = (uint32_t)((PORTA_PCR14 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x03)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x04)
                ));
  /* PORTA_PCR13: ISF=0,MUX=4 */
  PORTA_PCR13 = (uint32_t)((PORTA_PCR13 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x03)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x04)
                ));
  /* PORTA_PCR12: ISF=0,MUX=4 */
  PORTA_PCR12 = (uint32_t)((PORTA_PCR12 & (uint32_t)~(uint32_t)(
                 PORT_PCR_ISF_MASK |
                 PORT_PCR_MUX(0x03)
                )) | (uint32_t)(
                 PORT_PCR_MUX(0x04)
                ));
  /* Set interrupt priorities */
  /* NVICIP76: PRI76=0x80 */
  NVICIP76 = NVIC_IP_PRI76(0x80);
  /* NVICISER2: SETENA|=0x1000 */
  NVICISER2 |= NVIC_ISER_SETENA(0x1000);
  /* NVICIP77: PRI77=0x80 */
  NVICIP77 = NVIC_IP_PRI77(0x80);
  /* NVICISER2: SETENA|=0x2000 */
  NVICISER2 |= NVIC_ISER_SETENA(0x2000);
  /* NVICIP78: PRI78=0x80 */
  NVICIP78 = NVIC_IP_PRI78(0x80);
  /* NVICISER2: SETENA|=0x4000 */
  NVICISER2 |= NVIC_ISER_SETENA(0x4000);
  /* Set interrupt mask */
  /* ENET_EIMR: ??=0,BABR=0,BABT=0,GRA=0,TXF=1,TXB=0,RXF=1,RXB=0,MII=0,EBERR=1,LC=0,RL=0,UN=0,PLR=0,WAKEUP=0,TS_AVAIL=0,TS_TIMER=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  ENET_EIMR = (ENET_EIMR_TXF_MASK | ENET_EIMR_RXF_MASK | ENET_EIMR_EBERR_MASK);
  /* Clear interrupt flags */
  /* ENET_EIR: ??=1,BABR=1,BABT=1,GRA=1,TXF=1,TXB=1,RXF=1,RXB=1,MII=1,EBERR=1,LC=1,RL=1,UN=1,PLR=0,WAKEUP=0,TS_AVAIL=0,TS_TIMER=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0 */
  ENET_EIR = ENET_EIR_BABR_MASK |
             ENET_EIR_BABT_MASK |
             ENET_EIR_GRA_MASK |
             ENET_EIR_TXF_MASK |
             ENET_EIR_TXB_MASK |
             ENET_EIR_RXF_MASK |
             ENET_EIR_RXB_MASK |
             ENET_EIR_MII_MASK |
             ENET_EIR_EBERR_MASK |
             ENET_EIR_LC_MASK |
             ENET_EIR_RL_MASK |
             ENET_EIR_UN_MASK |
             0x80000000U;
  /* Allocate the transmit frame interrupt vector */
  /* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
  INT_ENET_Transmit__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv;
  /* Allocate the receive frame interrupt vector */
  /* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
  INT_ENET_Receive__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv;
  /* Allocate the shared interrupt vector */
  /* {FreeRTOS RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
  INT_ENET_Error__BAREBOARD_RTOS_ISRPARAM = DeviceDataPrv;
  /* Set MAC address */
  /* ENET_PALR: PADDR1=0x43EF783A */
  ENET_PALR = ENET_PALR_PADDR1(0x43EF783A);
  /* ENET_PAUR: PADDR2=0x2E19,TYPE=0 */
  ENET_PAUR = (ENET_PAUR_PADDR2(0x2E19) | ENET_PAUR_TYPE(0x00));
  /* Set unicast address hash table */
  /* ENET_IAUR: IADDR1=0 */
  ENET_IAUR = ENET_IAUR_IADDR1(0x00);
  /* ENET_IALR: IADDR2=0 */
  ENET_IALR = ENET_IALR_IADDR2(0x00);
  /* Set multicast address hash table */
  /* ENET_GAUR: GADDR1=0 */
  ENET_GAUR = ENET_GAUR_GADDR1(0x00);
  /* ENET_GALR: GADDR2=0 */
  ENET_GALR = ENET_GALR_GADDR2(0x00);
  /* Set PAUSE frame duration */
  /* ENET_OPD: OPCODE=0,PAUSE_DUR=0 */
  ENET_OPD = (ENET_OPD_OPCODE(0x00) | ENET_OPD_PAUSE_DUR(0x00));
  /* Set transmit control register */
  /* ENET_TCR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,CRCFWD=0,ADDINS=0,ADDSEL=0,RFC_PAUSE=0,TFC_PAUSE=0,FDEN=1,??=0,GTS=0 */
  ENET_TCR = (ENET_TCR_ADDSEL(0x00) | ENET_TCR_FDEN_MASK);
  /* Set transmit accelerator function configuration register */
  /* ENET_TACC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,PROCHK=0,IPCHK=0,??=0,??=0,SHIFT16=0 */
  ENET_TACC = 0x00U;
  /* Set receive control register */
  /* ENET_RCR: GRS=0,NLC=0,MAX_FL=0x05EE,CFEN=0,CRCFWD=0,PAUFWD=1,PADEN=0,??=0,??=0,RMII_10T=0,RMII_MODE=1,??=0,??=0,FCE=1,BC_REJ=0,PROM=0,MII_MODE=1,DRT=0,LOOP=0 */
  ENET_RCR = ENET_RCR_MAX_FL(0x05EE) |
             ENET_RCR_PAUFWD_MASK |
             ENET_RCR_RMII_MODE_MASK |
             ENET_RCR_FCE_MASK |
             ENET_RCR_MII_MODE_MASK;
  /* Set receive accelerator function configuration register */
  /* ENET_RACC: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,SHIFT16=0,LINEDIS=0,??=0,??=0,??=0,PRODIS=0,IPDIS=0,PADREM=0 */
  ENET_RACC = 0x00U;
  /* Set transmit inter-packet gap */
  /* ENET_TIPG: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,IPG=8 */
  ENET_TIPG = ENET_TIPG_IPG(0x08);
  /* Set frame truncation length */
  /* ENET_FTRL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TRUNC_FL=0x0800 */
  ENET_FTRL = ENET_FTRL_TRUNC_FL(0x0800);
  /* Set transmit FIFO watermark */
  /* ENET_TFWR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,STRFWD=1,??=0,??=0,TFWR=0 */
  ENET_TFWR = (ENET_TFWR_STRFWD_MASK | ENET_TFWR_TFWR(0x00));
  /* Set transmit FIFO section empty threshold */
  /* ENET_TSEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TX_SECTION_EMPTY=0 */
  ENET_TSEM = ENET_TSEM_TX_SECTION_EMPTY(0x00);
  /* Set transmit FIFO almost empty threshold */
  /* ENET_TAEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TX_ALMOST_EMPTY=8 */
  ENET_TAEM = ENET_TAEM_TX_ALMOST_EMPTY(0x08);
  /* Set transmit FIFO almost full threshold */
  /* ENET_TAFL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,TX_ALMOST_FULL=8 */
  ENET_TAFL = ENET_TAFL_TX_ALMOST_FULL(0x08);
  /* Set receive FIFO section full threshold */
  /* ENET_RSFL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_SECTION_FULL=0 */
  ENET_RSFL = ENET_RSFL_RX_SECTION_FULL(0x00);
  /* Set receive FIFO section empty threshold */
  /* ENET_RSEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_SECTION_EMPTY=0 */
  ENET_RSEM = ENET_RSEM_RX_SECTION_EMPTY(0x00);
  /* Set receive FIFO almost empty threshold */
  /* ENET_RAEM: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_ALMOST_EMPTY=8 */
  ENET_RAEM = ENET_RAEM_RX_ALMOST_EMPTY(0x08);
  /* Set receive FIFO almost full threshold */
  /* ENET_RAFL: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,RX_ALMOST_FULL=8 */
  ENET_RAFL = ENET_RAFL_RX_ALMOST_FULL(0x08);
  /* Set MII speed control register */
  /* ENET_MSCR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,HOLDTIME=7,DIS_PRE=1,MII_SPEED=3,??=0 */
  ENET_MSCR = ENET_MSCR_HOLDTIME(0x07) |
              ENET_MSCR_DIS_PRE_MASK |
              ENET_MSCR_MII_SPEED(0x03);
  /* Set receive buffer size */
  /* ENET_MRBR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,R_BUF_SIZE=0,??=0,??=0,??=0,??=0 */
  ENET_MRBR = ENET_MRBR_R_BUF_SIZE(0x00);
  /* Initialize the transmit frame buffer queue */
  LDD_QUEUE_INIT(ETH1_TTxQueueItem, DeviceDataPrv->TxQueue, ETH1_QUEUE_MEM_ALIGN); /* Initialize the queue data structure */
  TxQueueItemPtr = LDD_QUEUE_GET_DATA_START(DeviceDataPrv->TxQueue);
  while (TxQueueItemPtr != (LDD_QUEUE_GET_DATA_END(DeviceDataPrv->TxQueue) + 1)) {
    /* Clear queue item */
    for (MemPtr = (uint8_t*)(uint32_t)TxQueueItemPtr; MemPtr != (uint8_t*)(uint32_t)(TxQueueItemPtr + 1); MemPtr++) {
      *MemPtr = 0U;
    }
    TxQueueItemPtr++;                  /* Move to the next queue item */
  }
  setReg32(ENET_TDSR, LDD_QUEUE_GET_DATA_START(DeviceDataPrv->TxQueue));
  /* Initialize the receive frame buffer queue */
  LDD_QUEUE_INIT(ETH1_TRxQueueItem, DeviceDataPrv->RxQueue, ETH1_QUEUE_MEM_ALIGN); /* Initialize the queue data structure */
  RxQueueItemPtr = LDD_QUEUE_GET_DATA_START(DeviceDataPrv->RxQueue);
  while (RxQueueItemPtr != (LDD_QUEUE_GET_DATA_END(DeviceDataPrv->RxQueue) + 1)) {
    /* Clear queue item */
    for (MemPtr = (uint8_t*)(uint32_t)RxQueueItemPtr; MemPtr != (uint8_t*)(uint32_t)(RxQueueItemPtr + 1); MemPtr++) {
      *MemPtr = 0U;
    }
    RxQueueItemPtr++;                  /* Move to the next queue item */
  }
  setReg32(ENET_RDSR, LDD_QUEUE_GET_DATA_START(DeviceDataPrv->RxQueue));
  /* ENET_ECR: ??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,??=0,DBSWP=0,STOPEN=0,DBGEN=0,??=0,EN1588=0,SLEEP=0,MAGICEN=0,ETHEREN=0,RESET=0 */
  ENET_ECR = 0x00U;
  /* Enable the device */
  ENET_PDD_EnableDevice(ENET_BASE_PTR);
  DeviceDataPrv->Enabled = TRUE;
  /* Registration of the device structure */
  PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_ETH1_ID,DeviceDataPrv);
  return (LDD_TDeviceData*)DeviceDataPrv;
}
Example #26
0
/* ===================================================================*/
LDD_TDeviceData* I2CAccel_Init(LDD_TUserData *UserDataPtr)
{
    /* Allocate HAL device structure */
    I2CAccel_TDeviceData *DeviceDataPrv;
    /* {Default RTOS Adapter} Driver memory allocation: Dynamic allocation is simulated by a pointer to the static object */
    DeviceDataPrv = &DeviceDataPrv__DEFAULT_RTOS_ALLOC;

    DeviceDataPrv->UserData = UserDataPtr; /* Store the RTOS device structure */

    /* Allocate interrupt vector */
    /* {Default RTOS Adapter} Set interrupt vector: IVT is static, ISR parameter is passed by the global variable */
    INT_I2C0__DEFAULT_RTOS_ISRPARAM = DeviceDataPrv;
    DeviceDataPrv->SerFlag = ADDR_7;     /* Reset all flags start with 7-bit address mode */
    DeviceDataPrv->SlaveAddr = 0x3AU;    /* Set variable for slave address */
    DeviceDataPrv->SendStop = LDD_I2C_SEND_STOP; /* Set variable for sending stop condition (for master mode) */
    DeviceDataPrv->InpLenM = 0x00U;      /* Set zero counter of data of reception */
    DeviceDataPrv->OutLenM = 0x00U;      /* Set zero counter of data of transmission */
    /* SIM_SCGC4: I2C0=1 */
    SIM_SCGC4 |= SIM_SCGC4_I2C0_MASK;
    /* I2C0_C1: IICEN=0,IICIE=0,MST=0,TX=0,TXAK=0,RSTA=0,WUEN=0,DMAEN=0 */
    I2C0_C1 = 0x00U;                     /* Clear control register */
    /* I2C0_FLT: SHEN=0,STOPF=1,STOPIE=0,FLT=0 */
    I2C0_FLT = (I2C_FLT_STOPF_MASK | I2C_FLT_FLT(0x00)); /* Clear bus status interrupt flags */
    /* I2C0_S: TCF=0,IAAS=0,BUSY=0,ARBL=0,RAM=0,SRW=0,IICIF=1,RXAK=0 */
    I2C0_S = I2C_S_IICIF_MASK;           /* Clear interrupt flag */
    /* PORTE_PCR25: ISF=0,MUX=5 */
    PORTE_PCR25 = (uint32_t)((PORTE_PCR25 & (uint32_t)~(uint32_t)(
                                  PORT_PCR_ISF_MASK |
                                  PORT_PCR_MUX(0x02)
                              )) | (uint32_t)(
                                 PORT_PCR_MUX(0x05)
                             ));
    /* PORTE_PCR24: ISF=0,MUX=5 */
    PORTE_PCR24 = (uint32_t)((PORTE_PCR24 & (uint32_t)~(uint32_t)(
                                  PORT_PCR_ISF_MASK |
                                  PORT_PCR_MUX(0x02)
                              )) | (uint32_t)(
                                 PORT_PCR_MUX(0x05)
                             ));
    /* NVIC_IPR2: PRI_8=0x80 */
    NVIC_IPR2 = (uint32_t)((NVIC_IPR2 & (uint32_t)~(uint32_t)(
                                NVIC_IP_PRI_8(0x7F)
                            )) | (uint32_t)(
                               NVIC_IP_PRI_8(0x80)
                           ));
    /* NVIC_ISER: SETENA|=0x0100 */
    NVIC_ISER |= NVIC_ISER_SETENA(0x0100);
    /* I2C0_C2: GCAEN=0,ADEXT=0,HDRS=0,SBRC=0,RMEN=0,AD=0 */
    I2C0_C2 = I2C_C2_AD(0x00);
    /* I2C0_FLT: SHEN=0,STOPF=0,STOPIE=0,FLT=0 */
    I2C0_FLT = I2C_FLT_FLT(0x00);        /* Set glitch filter register */
    /* I2C0_SMB: FACK=0,ALERTEN=0,SIICAEN=0,TCKSEL=0,SLTF=1,SHTF1=0,SHTF2=0,SHTF2IE=0 */
    I2C0_SMB = I2C_SMB_SLTF_MASK;
    /* I2C0_F: MULT=0,ICR=0 */
    I2C0_F = (I2C_F_MULT(0x00) | I2C_F_ICR(0x00)); /* Set prescaler bits */
    I2C_PDD_EnableDevice(I2C0_BASE_PTR, PDD_ENABLE); /* Enable device */
    I2C_PDD_EnableInterrupt(I2C0_BASE_PTR); /* Enable interrupt */
    /* Registration of the device structure */
    PE_LDD_RegisterDeviceStructure(PE_LDD_COMPONENT_I2CAccel_ID,DeviceDataPrv);
    return ((LDD_TDeviceData *)DeviceDataPrv); /* Return pointer to the data data structure */
}
Example #27
0
void TWRK60_flexbus_init(void){

/* Enable the FlexBus                                               */
/* Configure the FlexBus Registers for 8-bit port size              */
/*  with separate address and data using chip select 0              */
/* These configurations are specific to communicating with          */ 
/*  the MRAM used in this example                                   */
/* For K60 tower module - do not set byte lane shift so that data   */
/*  comes out on AD[31:24]                                          */
  
  //Set Base address
  FB_CSAR0 = (uint32)&MRAM_START_ADDRESS;

  FB_CSCR0  =   FB_CSCR_PS(1)      // 8-bit port
              | FB_CSCR_AA_MASK    // auto-acknowledge
              | FB_CSCR_ASET(0x1)  // assert chip select on second clock edge after address is asserted
              | FB_CSCR_WS(0x1)    // 1 wait state - may need a wait state depending on the bus speed 
              ;

  FB_CSMR0  =   FB_CSMR_BAM(0x7)  //Set base address mask for 512K address space
              | FB_CSMR_V_MASK    //Enable cs signal
              ;
              
   //enable BE signals - note, not used in this example
  FB_CSPMCR = 0x02200000;

  //fb clock divider 3
  SIM_CLKDIV1 |= SIM_CLKDIV1_OUTDIV3(0x3);
   
   
  /* Configure the pins needed to FlexBus Function (Alt 5) */
  /* this example uses low drive strength settings         */

  //address
  PORTB_PCR11 = PORT_PCR_MUX(5);           //  fb_ad[18]
  PORTB_PCR16 = PORT_PCR_MUX(5);           //  fb_ad[17]
  PORTB_PCR17 = PORT_PCR_MUX(5);           //  fb_ad[16]
  PORTB_PCR18 = PORT_PCR_MUX(5);           //  fb_ad[15]
  PORTC_PCR0  = PORT_PCR_MUX(5);           //  fb_ad[14]
  PORTC_PCR1  = PORT_PCR_MUX(5);           //  fb_ad[13]
  PORTC_PCR2  = PORT_PCR_MUX(5);           //  fb_ad[12]
  PORTC_PCR4  = PORT_PCR_MUX(5);           //  fb_ad[11]
  PORTC_PCR5  = PORT_PCR_MUX(5);           //  fb_ad[10]
  PORTC_PCR6  = PORT_PCR_MUX(5);           //  fb_ad[9]
  PORTC_PCR7  = PORT_PCR_MUX(5);           //  fb_ad[8]
  PORTC_PCR8  = PORT_PCR_MUX(5);           //  fb_ad[7]
  PORTC_PCR9  = PORT_PCR_MUX(5);           //  fb_ad[6]
  PORTC_PCR10 = PORT_PCR_MUX(5);           //  fb_ad[5]
  PORTD_PCR2  = PORT_PCR_MUX(5);           //  fb_ad[4]
  PORTD_PCR3  = PORT_PCR_MUX(5);           //  fb_ad[3]
  PORTD_PCR4  = PORT_PCR_MUX(5);           //  fb_ad[2]
  PORTD_PCR5  = PORT_PCR_MUX(5);           //  fb_ad[1]
  PORTD_PCR6  = PORT_PCR_MUX(5);           //  fb_ad[0]
  
  //data
  PORTB_PCR20 = PORT_PCR_MUX(5);           //  fb_ad[31] used as d[7]
  PORTB_PCR21 = PORT_PCR_MUX(5);           //  fb_ad[30] used as d[6]
  PORTB_PCR22 = PORT_PCR_MUX(5);           //  fb_ad[29] used as d[5]
  PORTB_PCR23 = PORT_PCR_MUX(5);           //  fb_ad[28] used as d[4]
  PORTC_PCR12 = PORT_PCR_MUX(5);           //  fb_ad[27] used as d[3]
  PORTC_PCR13 = PORT_PCR_MUX(5);           //  fb_ad[26] used as d[2]
  PORTC_PCR14 = PORT_PCR_MUX(5);           //  fb_ad[25] used as d[1]
  PORTC_PCR15 = PORT_PCR_MUX(5);           //  fb_ad[24] used as d[0]

  //control signals
  PORTB_PCR19 = PORT_PCR_MUX(5);          // fb_oe_b
  PORTC_PCR11 = PORT_PCR_MUX(5);          // fb_rw_b  
  PORTD_PCR1  = PORT_PCR_MUX(5);          // fb_cs0_b
  PORTD_PCR0  = PORT_PCR_MUX(5);          // fb_ale

}
Example #28
0
void FTM2_CH1_Init (void)
{
  FTM2_C1SC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); //High True Pulses Edge Aligned PWM
  FTM2_C1V = (unsigned long)(FTM2_MODULO/2); //50% PWM
  FTM2_PWMCH1_PORT = PORT_PCR_MUX(3); //Go to PWM mode
}
Example #29
0
void display_7segments_initDisplays()
{
	// Gate clock to PORTC
	SIM_SCGC5 |= (SIM_SCGC5_PORTC_MASK);

	// Setting pin muxes to ALT1 (GPIO)
	PORTC_PCR0 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR1 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR2 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR3 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR4 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR5 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR6 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR7 = PORT_PCR_MUX(D7S_ALT);

	PORTC_PCR10 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR11 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR12 = PORT_PCR_MUX(D7S_ALT);
	PORTC_PCR13 = PORT_PCR_MUX(D7S_ALT);

	// Ungating port clock to preserve power if defined
	#ifdef D7S_UNGATE_CLOCK
		SIM_SCGC5 &= ~SIM_SCGC5_PORTC_MASK;
	#endif

	// Setting GPIO direction to output
	GPIOC_PDDR |= GPIO_PDDR_PDD(D7S_DIR);

}
Example #30
0
#include "uart.h"

/*----- Macros -------------------------------------------------------------*/

/*----- Data types ---------------------------------------------------------*/
typedef struct _PORT_PIN_t {
	PORT_Type *PORTx;
	uint8_t Bit;
	uint32_t Alt;
} PORT_PIN_t;

/*----- Function prototypes ------------------------------------------------*/

/*----- Data ---------------------------------------------------------------*/
PORT_PIN_t UART_Port_Pin[] = {
        { PORTA, 1, PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x2) },
        { PORTA, 2, PORT_PCR_ISF_MASK | PORT_PCR_MUX(0x2) }
};

/*----- Implementation -----------------------------------------------------*/
/**
 *****************************************************************************
 * \fn			UART_init
 * \brief		Configure a UART to the specific baud rate and 8n1.
 *
 * \param [in]	UARTx	The UART port which will be used. Possible values are
 *						UART0, UART1 and UART2.
 * \param [in]	Baud	Selected baud rate in Hz.
 * \return		None
 *****************************************************************************
 */