static int32_t isp_k_brightness_block(struct isp_io_param *param)
{
int32_t ret = 0;
struct isp_dev_brightness_info brightness_info;
memset(&brightness_info, 0x00, sizeof(brightness_info));
ret = copy_from_user((void *)&brightness_info, param->property_param, sizeof(brightness_info));
if (0 != ret) {
printk("isp_k_brightness_block: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_BRIGHT_PARAM, 0x1FE, ((brightness_info.factor & 0xFF) << 1));
if (brightness_info.bypass) {
REG_OWR(ISP_BRIGHT_PARAM, BIT_0);
} else {
REG_MWR(ISP_BRIGHT_PARAM, BIT_0, 0);
}
return ret;
}
static int32_t isp_k_fcs_block(struct isp_io_param *param)
{
int32_t ret = 0;
struct isp_dev_fcs_info fcs_info;
memset(&fcs_info, 0x00, sizeof(fcs_info));
ret = copy_from_user((void *)&fcs_info, param->property_param, sizeof(fcs_info));
if (0 != ret) {
printk("isp_k_fcs_bypass: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_FCS_PARAM, BIT_16, (fcs_info.mode << 16));
if (fcs_info.bypass) {
REG_OWR(ISP_FCS_PARAM, BIT_0);
} else {
REG_MWR(ISP_FCS_PARAM, BIT_0, 0);
}
return ret;
}
int32_t dcam_module_init(enum dcam_cap_if_mode if_mode,
enum dcam_cap_sensor_mode sn_mode)
{
enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS;
struct dcam_cap_desc *cap_desc = &s_dcam_mod.dcam_cap;
int ret = 0;
if (if_mode >= DCAM_CAP_IF_MODE_MAX) {
rtn = -DCAM_RTN_CAP_IF_MODE_ERR;
} else {
if (sn_mode >= DCAM_CAP_MODE_MAX) {
rtn = -DCAM_RTN_CAP_SENSOR_MODE_ERR;
} else {
DCAM_CLEAR(&s_dcam_mod);
_dcam_link_frm(0); /* set default base frame index as 0 */
cap_desc->interface = if_mode;
cap_desc->input_format = sn_mode;
/*REG_OWR(DCAM_EB, BIT_13);//MM_EB*/
/*REG_OWR(DCAM_MATRIX_EB, BIT_10|BIT_5);*/
if (DCAM_CAP_IF_CSI2 == if_mode) {
/* REG_OWR(CSI2_DPHY_EB, MIPI_EB_BIT);*/
ret = _dcam_mipi_clk_en();
REG_OWR(DCAM_CFG, BIT_9);
REG_MWR(CAP_MIPI_CTRL, BIT_2 | BIT_1, sn_mode << 1);
} else {
/*REG_OWR(DCAM_EB, CCIR_IN_EB_BIT);
REG_OWR(DCAM_EB, CCIR_EB_BIT);*/
ret = _dcam_ccir_clk_en();
REG_MWR(DCAM_CFG, BIT_9, 0 << 9);
REG_MWR(CAP_CCIR_CTRL, BIT_2 | BIT_1, sn_mode << 1);
}
rtn = DCAM_RTN_SUCCESS;
}
}
return -rtn;
}
static int32_t isp_k_yiq_block_ygamma(struct isp_io_param *param)
{
int32_t ret = 0;
uint32_t val = 0;
struct isp_dev_yiq_ygamma_info ygamma_info;
memset(&ygamma_info, 0x00, sizeof(ygamma_info));
ret = copy_from_user((void *)&ygamma_info, param->property_param, sizeof(ygamma_info));
if (0 != ret) {
printk("isp_k_yiq_block_ygamma: copy error, ret=0x%x\n", (uint32_t)ret);
return -1;
}
val = (ygamma_info.x_node[0] << 24)
| (ygamma_info.x_node[1] << 16)
| (ygamma_info.x_node[2] << 8)
| ygamma_info.x_node[3];
REG_WR(ISP_YGAMMA_X0, val);
val = (ygamma_info.x_node[4] << 24)
| (ygamma_info.x_node[5] << 16)
| (ygamma_info.x_node[6] << 8)
| ygamma_info.x_node[7];
REG_WR(ISP_YGAMMA_X1, val);
val = (ygamma_info.y_node[0] << 24)
| (ygamma_info.y_node[1] << 16)
| (ygamma_info.y_node[2] << 8)
| ygamma_info.y_node[3];
REG_WR(ISP_YGAMMA_Y0, val);
val = (ygamma_info.y_node[4] << 24)
| (ygamma_info.y_node[5] << 16)
| (ygamma_info.y_node[6] << 8)
| ygamma_info.y_node[7];
REG_WR(ISP_YGAMMA_Y1, val);
val = (ygamma_info.y_node[8] << 24)
| (ygamma_info.y_node[9] << 16);
REG_WR(ISP_YGAMMA_Y2, val);
val = ((ygamma_info.node_index[0] & 0x07) << 24)
| ((ygamma_info.node_index[1] & 0x07) << 21)
| ((ygamma_info.node_index[2] & 0x07) << 18)
| ((ygamma_info.node_index[3] & 0x07) << 15)
| ((ygamma_info.node_index[4] & 0x07) << 12)
| ((ygamma_info.node_index[5] & 0x07) << 9)
| ((ygamma_info.node_index[6] & 0x07) << 6)
| ((ygamma_info.node_index[7] & 0x07) << 3)
| (ygamma_info.node_index[8] & 0x07);
REG_WR(ISP_YGAMMA_NODE_IDX, val);
if (ygamma_info.bypass) {
REG_OWR(ISP_YIQ_PARAM, BIT_0);
} else {
REG_MWR(ISP_YIQ_PARAM, BIT_0, 0);
}
return ret;
}
int32_t dcam_start(void)
{
enum dcam_drv_rtn rtn = DCAM_RTN_SUCCESS;
int ret = 0;
DCAM_TRACE("DCAM DRV: dcam_start %x \n", s_dcam_mod.dcam_mode);
#ifdef DCAM_DEBUG
REG_MWR(CAP_CCIR_FRM_CTRL, BIT_5 | BIT_4, 1 << 4);
REG_MWR(CAP_MIPI_FRM_CTRL, BIT_5 | BIT_4, 1 << 4);
#endif
REG_WR(DCAM_INT_CLR, DCAM_IRQ_LINE_MASK);
REG_WR(DCAM_INT_MASK, DCAM_IRQ_LINE_MASK);
ret = request_irq(DCAM_IRQ,
dcam_isr_root,
IRQF_SHARED,
"DCAM",
&g_dcam_irq);
if (ret) {
DCAM_TRACE("dcam_start, error %d \n", ret);
return -DCAM_RTN_MAX;
}
if (s_dcam_mod.dcam_path1.valide) {
rtn = _dcam_path_trim(DCAM_PATH1);
DCAM_RTN_IF_ERR;
rtn = _dcam_path_scaler(DCAM_PATH1);
DCAM_RTN_IF_ERR;
rtn = _dcam_path_set_next_frm(DCAM_PATH1, true);
DCAM_RTN_IF_ERR;
REG_OWR(DCAM_CFG, BIT_0);
}
if (s_dcam_mod.dcam_path2.valide) {
rtn = _dcam_path_trim(DCAM_PATH2);
DCAM_RTN_IF_ERR;
rtn = _dcam_path_scaler(DCAM_PATH2);
DCAM_RTN_IF_ERR;
rtn = _dcam_path_set_next_frm(DCAM_PATH2, true);
DCAM_RTN_IF_ERR;
REG_OWR(DCAM_CFG, BIT_1);
REG_OWR(DCAM_BURST_GAP, BIT_20);
}
_dcam_force_copy();
_dcam_reg_trace();
printk("DCAM S \n");
REG_MWR(DCAM_PATH_CFG, BIT_0, 1);
if (s_dcam_mod.dcam_path1.valide) {
rtn = _dcam_path_set_next_frm(DCAM_PATH1, false);
DCAM_RTN_IF_ERR;
}
if (s_dcam_mod.dcam_path2.valide) {
rtn = _dcam_path_set_next_frm(DCAM_PATH2, false);
DCAM_RTN_IF_ERR;
}
_dcam_auto_copy();
return -rtn;
}
static int32_t isp_k_edge_block(struct isp_io_param *param)
{
int32_t ret = 0;
struct isp_dev_edge_info_v1 edge_info;
uint32_t val = 0;
memset(&edge_info, 0x00, sizeof(edge_info));
ret = copy_from_user((void *)&edge_info, param->property_param, sizeof(edge_info));
if (0 != ret) {
printk("isp_k_edge_block: copy_from_user error, ret = 0x%x\n", (uint32_t)ret);
return -1;
}
REG_MWR(ISP_EE_CFG0, BIT_29 | BIT_28, edge_info.mode << 28);
val = (edge_info.ee_str_m_n & 0x7F) | ((edge_info.ee_str_m_p & 0x7F) << 7)
| ((edge_info.ee_str_d_n & 0x7F) << 14) | ((edge_info.ee_str_d_p & 0x7F) << 21);
REG_MWR(ISP_EE_CFG0, 0xFFFFFFF, val);
val = ((edge_info.ee_incr_d_p & 0xFF) << 8) | (edge_info.ee_incr_d_n & 0xFF);
REG_MWR(ISP_EE_CFG1, 0xFFFF, val);
val = ((edge_info.ee_thr_d_n & 0xFF) << 16) | ((edge_info.ee_thr_d_p & 0xFF) << 24);
REG_MWR(ISP_EE_CFG1, 0xFFFF0000, val);
val = (edge_info.ee_flat_thr_1 & 0xFF) | ((edge_info.ee_flat_thr_2 & 0xFF) << 8);
REG_MWR(ISP_EE_CFG2, 0xFFFF, val);
val = ((edge_info.ee_incr_m_n & 0xFF) << 16) | ((edge_info.ee_incr_m_p & 0xFF) << 24);
REG_MWR(ISP_EE_CFG2, 0xFFFF0000, val);
val = (edge_info.ee_txt_thr_1 & 0xFF) | ((edge_info.ee_txt_thr_2 & 0xFF) << 8)
| ((edge_info.ee_txt_thr_3 & 0xFF) << 16);
REG_WR(ISP_EE_CFG3, val);
val = ((edge_info.ee_corner_cor & 0x1) << 28) | ((edge_info.ee_corner_th_p & 0x1F) << 23)
| ((edge_info.ee_corner_th_n & 0x1F) << 18) | ((edge_info.ee_corner_gain_p & 0x7F) << 11)
| ((edge_info.ee_corner_gain_n & 0x7F) << 4) | ((edge_info.ee_corner_sm_p & 0x3) << 2)
| (edge_info.ee_corner_sm_n & 0x3);
REG_WR(ISP_EE_CFG4, val);
val = ((edge_info.ee_edge_smooth_mode & 0x3) << 26) | ((edge_info.ee_flat_smooth_mode & 0x3) << 24)
| ((edge_info.ee_smooth_thr & 0xFF) << 8) | (edge_info.ee_smooth_strength & 0xFF);
REG_MWR(ISP_EE_CFG5, 0xF00FFFF, val);
val = (edge_info.sigma & 0xFF) << 16;
REG_MWR(ISP_EE_CFG5, 0xFF0000, val);
val = ((edge_info.ee_str_b_p & 0xFF) << 24) | ((edge_info.ee_str_b_n & 0xFF) << 16)
| ((edge_info.ee_incr_b_p & 0xFF) << 8) | (edge_info.ee_incr_b_n & 0xFF);
REG_WR(ISP_EE_CFG6, val);
val = ((edge_info.ratio[1] & 0xFF) << 8) | (edge_info.ratio[0] & 0xFF);
REG_MWR(ISP_EE_CFG7, 0xFFFF, val);
val = (edge_info.ee_clip_after_smooth_en & 0x1) << 25;
REG_MWR(ISP_EE_CFG7, BIT_25, val);
val = ((edge_info.ipd_bypass & 0x1) << 24) | ((edge_info.ipd_flat_thr & 0xFF) << 16);
REG_MWR(ISP_EE_CFG7, 0x1FF0000, val);
val = (edge_info.ee_t1_cfg & 0x3FF) | ((edge_info.ee_t2_cfg & 0x3FF) << 10)
| ((edge_info.ee_t3_cfg & 0x3FF) << 20);
REG_WR(ISP_EE_ADP_CFG0, val);
val = (edge_info.ee_t4_cfg & 0x3FF) | ((edge_info.ee_cv_clip_n & 0xFF) << 16)
| ((edge_info.ee_cv_clip_p & 0xFF) << 24);
REG_WR(ISP_EE_ADP_CFG1, val);
val = (edge_info.ee_r1_cfg & 0xFF) | ((edge_info.ee_r2_cfg & 0xFF) << 8)
| ((edge_info.ee_r3_cfg & 0xFF) << 16);
REG_WR(ISP_EE_ADP_CFG2, val);
if (edge_info.bypass) {
REG_OWR(ISP_EE_PARAM, BIT_0);
} else {
REG_MWR(ISP_EE_PARAM, BIT_0, 0);
}
return ret;
}
static int32_t isp_k_yuv_cdn_block(struct isp_io_param *param)
{
int32_t ret = 0;
struct isp_dev_yuv_cdn_info cdn_info;
uint32_t val = 0;
uint32_t i = 0;
memset(&cdn_info, 0x00, sizeof(cdn_info));
ret = copy_from_user((void *)&cdn_info, param->property_param, sizeof(cdn_info));
if (0 != ret) {
printk("isp_k_yuv_cdn_block: copy_from_user error, ret = 0x%x\n", (uint32_t)ret);
return -1;
}
if (cdn_info.median_writeback_en) {
REG_OWR(ISP_CDN_PARAM, BIT_2);
} else {
REG_MWR(ISP_CDN_PARAM, BIT_2, 0);
}
REG_MWR(ISP_CDN_PARAM, 0x38, cdn_info.median_mode << 3);
REG_MWR(ISP_CDN_PARAM, BIT_7 | BIT_6, cdn_info.gaussian_mode << 6);
REG_MWR(ISP_CDN_PARAM, 0x3FFF00, cdn_info.median_thr << 8);
val = (cdn_info.median_thru0 & 0x7F) | ((cdn_info.median_thru1 & 0xFF) << 8)
| ((cdn_info.median_thrv0 & 0x7F) << 16) | ((cdn_info.median_thrv1 & 0xFF) << 24);
REG_WR(ISP_CDN_THRUV, val);
for (i = 0; i < 7; i++) {
val = (cdn_info.rangewu[i*4] & 0x3F) | ((cdn_info.rangewu[i*4+1] & 0x3F) << 8)
| ((cdn_info.rangewu[i*4+2] & 0x3F) << 16) | ((cdn_info.rangewu[i*4+3] & 0x3F) << 24);
REG_WR(ISP_CDN_U_RANWEI_0 + i * 4, val);
}
val = (cdn_info.rangewu[28] & 0x3F) | ((cdn_info.rangewu[29] & 0x3F) << 8)
| ((cdn_info.rangewu[30] & 0x3F) << 16);
REG_WR(ISP_CDN_U_RANWEI_7, val);
for (i = 0; i < 7; i++) {
val = (cdn_info.rangewv[i*4] & 0x3F) | ((cdn_info.rangewv[i*4+1] & 0x3F) << 8)
| ((cdn_info.rangewv[i*4+2] & 0x3F) << 16) | ((cdn_info.rangewv[i*4+3] & 0x3F) << 24);
REG_WR(ISP_CDN_V_RANWEI_0 + i * 4, val);
}
val = (cdn_info.rangewv[28] & 0x3F) | ((cdn_info.rangewv[29] & 0x3F) << 8)
| ((cdn_info.rangewv[30] & 0x3F) << 16);
REG_WR(ISP_CDN_V_RANWEI_7, val);
if (cdn_info.filter_bypass) {
REG_OWR(ISP_CDN_PARAM, BIT_1);
} else {
REG_MWR(ISP_CDN_PARAM, BIT_1, 0);
}
if (cdn_info.bypass) {
REG_OWR(ISP_CDN_PARAM, BIT_0);
} else {
REG_MWR(ISP_CDN_PARAM, BIT_0, 0);
}
return ret;
}
static int32_t _scale_set_sc_coeff(void)
{
uint32_t i = 0;
uint32_t h_coeff_addr = SCALE_BASE;
uint32_t v_coeff_addr = SCALE_BASE;
uint32_t *tmp_buf = NULL;
uint32_t *h_coeff = NULL;
uint32_t *v_coeff = NULL;
h_coeff_addr += SC_COEFF_H_TAB_OFFSET;
v_coeff_addr += SC_COEFF_V_TAB_OFFSET;
tmp_buf = (uint32_t *)kmalloc(SC_COEFF_BUF_SIZE, GFP_KERNEL);
if (NULL == tmp_buf) {
printk("SCALE DRV: No mem to alloc coeff buffer! \n");
return SCALE_RTN_NO_MEM;
}
h_coeff = tmp_buf;
v_coeff = tmp_buf + (SC_COEFF_COEF_SIZE/4);
if (!(GenScaleCoeff((int16_t)g_path->sc_input_size.w,
(int16_t)g_path->sc_input_size.h,
(int16_t)g_path->output_size.w,
(int16_t)g_path->output_size.h,
h_coeff,
v_coeff,
tmp_buf + (SC_COEFF_COEF_SIZE/2),
SC_COEFF_TMP_SIZE))) {
kfree(tmp_buf);
printk("SCALE DRV: _scale_set_sc_coeff error! \n");
return SCALE_RTN_GEN_COEFF_ERR;
}
do {
REG_OWR(SCALE_BASE, 1 << 4);
} while ((1 << 6) != ((1 << 6) & REG_RD(SCALE_BASE)));
for (i = 0; i < SC_COEFF_H_NUM; i++) {
REG_WR(h_coeff_addr, *h_coeff);
h_coeff_addr += 4;
h_coeff++;
}
for (i = 0; i < SC_COEFF_V_NUM; i++) {
REG_WR(v_coeff_addr, *v_coeff);
v_coeff_addr += 4;
v_coeff++;
}
REG_MWR(SCALE_CFG, (0xF << 16), ((*v_coeff) & 0x0F) << 16);
SCALE_TRACE("SCALE DRV: _scale_set_sc_coeff V[%d] = 0x%x \n", i, (*v_coeff) & 0x0F);
do {
REG_MWR(SCALE_BASE, 1 << 4, 0 << 4);
} while (0 != ((1 << 6) & REG_RD(SCALE_BASE)));
kfree(tmp_buf);
return SCALE_RTN_SUCCESS;
}
int32_t scale_cfg(enum scale_cfg_id id, void *param)
{
enum scale_drv_rtn rtn = SCALE_RTN_SUCCESS;
switch (id) {
case SCALE_INPUT_SIZE:
{
struct scale_size *size = (struct scale_size*)param;
uint32_t reg_val = 0;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
SCALE_TRACE("SCALE DRV: SCALE_INPUT_SIZE {%d %d} \n", size->w, size->h);
if (size->w > SCALE_FRAME_WIDTH_MAX ||
size->h > SCALE_FRAME_HEIGHT_MAX) {
rtn = SCALE_RTN_SRC_SIZE_ERR;
} else {
reg_val = size->w | (size->h << 16);
REG_WR(SCALE_SRC_SIZE, reg_val);
g_path->input_size.w = size->w;
g_path->input_size.h = size->h;
}
break;
}
case SCALE_INPUT_RECT:
{
struct scale_rect *rect = (struct scale_rect*)param;
uint32_t reg_val = 0;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
SCALE_TRACE("SCALE DRV: SCALE_PATH_INPUT_RECT {%d %d %d %d} \n",
rect->x,
rect->y,
rect->w,
rect->h);
if (rect->x > SCALE_FRAME_WIDTH_MAX ||
rect->y > SCALE_FRAME_HEIGHT_MAX ||
rect->w > SCALE_FRAME_WIDTH_MAX ||
rect->h > SCALE_FRAME_HEIGHT_MAX) {
rtn = SCALE_RTN_TRIM_SIZE_ERR;
} else {
reg_val = rect->x | (rect->y << 16);
REG_WR(SCALE_TRIM_START, reg_val);
reg_val = rect->w | (rect->h << 16);
REG_WR(SCALE_TRIM_SIZE, reg_val);
memcpy((void*)&g_path->input_rect,
(void*)rect,
sizeof(struct scale_rect));
}
break;
}
case SCALE_INPUT_FORMAT:
{
enum scale_fmt format = *(enum scale_fmt*)param;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
g_path->input_format = format;
if (SCALE_YUV422 == format ||
SCALE_YUV420 == format ||
SCALE_YUV420_3FRAME == format ||
SCALE_YUV400 == format) {
REG_MWR(SCALE_CFG, (3 << 11), g_path->input_format << 11);
REG_MWR(SCALE_CFG, (1 << 5), 0 << 5);
} else if (SCALE_RGB565 == format) {
REG_OWR(SCALE_CFG, (1 << 13));
REG_OWR(SCALE_CFG, (1 << 5));
} else if (SCALE_RGB888 == format) {
REG_MWR(SCALE_CFG, (1 << 13), (0 << 13));
REG_OWR(SCALE_CFG, (1 << 5));
} else {
rtn = SCALE_RTN_IN_FMT_ERR;
g_path->input_format = SCALE_FTM_MAX;
}
break;
}
case SCALE_INPUT_ADDR:
{
struct scale_addr *p_addr = (struct scale_addr*)param;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
if (SCALE_YUV_ADDR_INVALIDE(p_addr->yaddr, p_addr->uaddr, p_addr->vaddr)) {
rtn = SCALE_RTN_ADDR_ERR;
} else {
g_path->input_addr.yaddr = p_addr->yaddr;
g_path->input_addr.uaddr = p_addr->uaddr;
g_path->input_addr.vaddr = p_addr->vaddr;
REG_WR(SCALE_FRM_IN_Y, p_addr->yaddr);
REG_WR(SCALE_FRM_IN_U, p_addr->uaddr);
REG_WR(SCALE_FRM_IN_V, p_addr->vaddr);
}
break;
}
case SCALE_INPUT_ENDIAN:
{
struct scale_endian_sel *endian = (struct scale_endian_sel*)param;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
if (endian->y_endian >= SCALE_ENDIAN_MAX ||
endian->uv_endian >= SCALE_ENDIAN_MAX) {
rtn = SCALE_RTN_ENDIAN_ERR;
} else {
REG_MWR(SCALE_ENDIAN_SEL, 3, endian->y_endian);
REG_MWR(SCALE_ENDIAN_SEL, 3 << 2, endian->uv_endian << 2);
}
break;
}
case SCALE_OUTPUT_SIZE:
{
struct scale_size *size = (struct scale_size*)param;
uint32_t reg_val = 0;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
SCALE_TRACE("SCALE DRV: SCALE_OUTPUT_SIZE {%d %d} \n", size->w, size->h);
if (size->w > SCALE_FRAME_WIDTH_MAX ||
size->h > SCALE_FRAME_HEIGHT_MAX) {
rtn = SCALE_RTN_SRC_SIZE_ERR;
} else {
reg_val = size->w | (size->h << 16);
REG_WR(SCALE_DST_SIZE, reg_val);
g_path->output_size.w = size->w;
g_path->output_size.h = size->h;
}
break;
}
case SCALE_OUTPUT_FORMAT:
{
enum scale_fmt format = *(enum scale_fmt*)param;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
g_path->output_format = format;
if (SCALE_YUV422 == format) {
REG_MWR(SCALE_CFG, (3 << 6), 0 << 6);
} else if (SCALE_YUV420 == format) {
REG_MWR(SCALE_CFG, (3 << 6), 1 << 6);
} else if (SCALE_RGB565 == format) {
REG_MWR(SCALE_CFG, (3 << 6), 2 << 6);
} else {
rtn = SCALE_RTN_OUT_FMT_ERR;
g_path->output_format = SCALE_FTM_MAX;
}
break;
}
case SCALE_OUTPUT_ADDR:
{
struct scale_addr *p_addr = (struct scale_addr*)param;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
if (SCALE_YUV_ADDR_INVALIDE(p_addr->yaddr, p_addr->uaddr, p_addr->vaddr)) {
rtn = SCALE_RTN_ADDR_ERR;
} else {
g_path->output_addr.yaddr = p_addr->yaddr;
g_path->output_addr.uaddr = p_addr->uaddr;
REG_WR(SCALE_FRM_OUT_Y, p_addr->yaddr);
REG_WR(SCALE_FRM_OUT_U, p_addr->uaddr);
}
break;
}
case SCALE_OUTPUT_ENDIAN:
{
struct scale_endian_sel *endian = (struct scale_endian_sel*)param;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
if (endian->y_endian >= SCALE_ENDIAN_MAX ||
endian->uv_endian >= SCALE_ENDIAN_MAX) {
rtn = SCALE_RTN_ENDIAN_ERR;
} else {
REG_MWR(SCALE_ENDIAN_SEL, (3 << 4), endian->y_endian << 4);
REG_MWR(SCALE_ENDIAN_SEL, (3 << 6), endian->uv_endian << 6);
}
break;
}
case SCALE_TEMP_BUFF:
{
struct scale_addr *p_addr = (struct scale_addr*)param;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
if (SCALE_YUV_ADDR_INVALIDE(p_addr->yaddr, p_addr->uaddr, p_addr->vaddr)) {
rtn = SCALE_RTN_ADDR_ERR;
} else {
g_path->temp_buf_src = 1;
g_path->temp_buf_addr.yaddr = p_addr->yaddr;
g_path->temp_buf_addr.uaddr = p_addr->uaddr;
g_path->temp_buf_addr.vaddr = p_addr->vaddr;
REG_WR(SCALE_FRM_SWAP_Y, p_addr->yaddr);
REG_WR(SCALE_FRM_SWAP_U, p_addr->uaddr);
REG_WR(SCALE_FRM_LINE, p_addr->vaddr);
}
break;
}
case SCALE_SCALE_MODE:
{
enum scle_mode mode = *(enum scle_mode*)param;
if (mode >= SCALE_MODE_MAX) {
rtn = SCALE_RTN_MODE_ERR;
} else {
g_path->scale_mode = mode;
if (SCALE_MODE_NORMAL == mode) {
REG_MWR(SCALE_CFG, (1 << 4), (0 << 4));
} else {
REG_OWR(SCALE_CFG, (1 << 4));
}
}
break;
}
case SCALE_SLICE_SCALE_HEIGHT:
{
uint32_t height = *(uint32_t*)param;
SCALE_CHECK_PARAM_ZERO_POINTER(param);
if (height > SCALE_FRAME_HEIGHT_MAX || (height % SCALE_SLICE_HEIGHT_ALIGNED)) {
rtn = SCALE_RTN_PARA_ERR;
} else {
g_path->slice_height = height;
REG_MWR(SCALE_SLICE_VER, 0x3FF, height);
}
break;
}
case SCALE_START:
{
rtn = scale_start();
break;
}
case SCALE_CONTINUE:
{
rtn = scale_continue();
break;
}
case SCALE_STOP:
{
rtn = scale_stop();
break;
}
default:
rtn = SCALE_RTN_IO_ID_ERR;
break;
}
return -rtn;
}
static void rot_k_enable(void)
{
REG_OWR(REG_ROTATION_CTRL, BIT(3));
return;
}
static void rot_k_set_UV_mode(ROT_UV_MODE_E uv_mode)
{
REG_AWR(REG_ROTATION_CTRL, (~BIT(0)));
REG_OWR(REG_ROTATION_CTRL, (uv_mode & 0x1));
return;
}
static void rot_k_set_dir(ROT_ANGLE_E angle)
{
REG_AWR(REG_ROTATION_CTRL, ~(0x3 << 1));
REG_OWR(REG_ROTATION_CTRL, (angle & 0x3) << 1);
return;
}
static void rot_k_set_pixel_mode(ROT_PIXEL_FORMAT_E pixel_format)
{
REG_AWR(REG_ROTATION_IMG_SIZE, ~(0x3 << 24));
REG_OWR(REG_ROTATION_IMG_SIZE, pixel_format << 24);
return;
}
static void rot_k_software_reset(void)
{
// rot soft reset
REG_OWR(AHB_GLOBAL_REG_SOFTRST, BIT(10));
REG_AWR(AHB_GLOBAL_REG_SOFTRST, ~BIT(10));
}
static int32_t isp_k_hist_block(struct isp_io_param *param)
{
int32_t ret = 0;
struct isp_dev_hist_info_v1 hist_info;
uint32_t val = 0;
memset(&hist_info, 0x00, sizeof(hist_info));
ret = copy_from_user((void *)&hist_info, param->property_param, sizeof(hist_info));
if (0 != ret) {
printk("isp_k_hist_block: copy_from_user error, ret = 0x%x\n", (uint32_t)ret);
return -1;
}
if (hist_info.buf_rst_en) {
REG_OWR(ISP_HIST_PARAM, BIT_1);
} else {
REG_MWR(ISP_HIST_PARAM, BIT_1, 0);
}
if (hist_info.pof_rst_en) {
REG_OWR(ISP_HIST_PARAM, BIT_9);
} else {
REG_MWR(ISP_HIST_PARAM, BIT_9, 0);
}
if (hist_info.skip_num_clr) {
REG_OWR(ISP_HIST_PARAM, BIT_8);
} else {
REG_MWR(ISP_HIST_PARAM, BIT_8, 0);
}
REG_MWR(ISP_HIST_PARAM, 0xF0, hist_info.skip_num << 4);
if (hist_info.mode) {
REG_OWR(ISP_HIST_PARAM, BIT_3);
} else {
REG_MWR(ISP_HIST_PARAM, BIT_3, 0);
}
val = ((hist_info.high_ratio & 0xFFFF) << 16)
| (hist_info.low_ratio & 0xFFFF);
REG_WR(ISP_HIST_RATIO, val);
val = (hist_info.dif_adj & 0xFF) | ((hist_info.small_adj & 0xFF) << 8)
| ((hist_info.big_adj & 0xFF) << 16);
REG_WR(ISP_HIST_ADJUST, val);
if (hist_info.off) {
REG_OWR(ISP_HIST_PARAM, BIT_2);
} else {
REG_MWR(ISP_HIST_PARAM, BIT_2, 0);
}
if (hist_info.bypass) {
REG_OWR(ISP_HIST_PARAM, BIT_0);
} else {
REG_MWR(ISP_HIST_PARAM, BIT_0, 0);
}
return ret;
}