VOID RT35xxLoadRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; #ifdef RT35xx if(IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, 0x00); #endif /* RT35xx */ if(!IS_RT3572(pAd)) { /* RF_BLOCK_en. RF R1 register Bit 0 to 0*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue &= (~0x01); RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 0*/ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue &= (~0x30); RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0*/ RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue &= (~0x0E); RT30xxWriteRFRegister(pAd, RF_R09, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 0*/ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x80); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } /* Don't touch LDO_CFG0 for 3090F & 3593, possibly the board is single power scheme*/ if (IS_RT3090(pAd) || /*IS_RT3090 including RT309x and RT3071/72*/ IS_RT3572(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if (!IS_RT3572(pAd)) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); RFValue |= 0x77; RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue |= 0x1D000000; RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ VOID RT30xxReverseRFSleepModeSetup( IN PRTMP_ADAPTER pAd, IN BOOLEAN FlgIsInitState) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { /* RF_BLOCK_en, RF R1 register Bit 0 to 1*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1*/ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue |= 0x20; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1*/ RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue |= 0x0E; RT30xxWriteRFRegister(pAd, RF_R09, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 1*/ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72*/ IS_RT3390(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); if ((pAd->MACVersion & 0xffff) < 0x0211) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } /* RT3071 version E has fixed this issue*/ } }
/* ========================================================================== Description: Load RF sleep-mode setup ========================================================================== */ void RT30xxLoadRFSleepModeSetup(struct rt_rtmp_adapter *pAd) { u8 RFValue; u32 MACValue; #ifdef RTMP_MAC_USB if (!IS_RT3572(pAd)) #endif /* RTMP_MAC_USB // */ { /* RF_BLOCK_en. RF R1 register Bit 0 to 0 */ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue &= (~0x01); RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 0 */ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue &= (~0x30); RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0 */ RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue &= (~0x0E); RT30xxWriteRFRegister(pAd, RF_R09, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 0 */ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x80); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72 */ IS_RT3572(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { #ifdef RTMP_MAC_USB if (!IS_RT3572(pAd)) #endif /* RTMP_MAC_USB // */ { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); RFValue |= 0x77; RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue |= 0x1D000000; RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } }
/* ======================================================================== Routine Description: Write RT30xx RF register through MAC Arguments: Return Value: IRQL = Note: ======================================================================== */ NDIS_STATUS RT30xxWriteRFRegister( IN PRTMP_ADAPTER pAd, IN UCHAR regID, IN UCHAR value) { RF_CSR_CFG_STRUC rfcsr = { { 0 } }; UINT i = 0; ASSERT((regID <= pAd->chipCap.MaxNumOfRfId)); do { RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word); if (!rfcsr.field.RF_CSR_KICK) break; i++; } while ((i < MAX_BUSY_COUNT) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))); if ((i == MAX_BUSY_COUNT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) { DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed!!!\n")); return STATUS_UNSUCCESSFUL; } rfcsr.field.RF_CSR_WR = 1; rfcsr.field.RF_CSR_KICK = 1; rfcsr.field.TESTCSR_RFACC_REGNUM = regID; if ((pAd->chipCap.RfReg17WtMethod == RF_REG_WT_METHOD_STEP_ON) && (regID == RF_R17)) { UCHAR IdRf; UCHAR RfValue; BOOLEAN beAdd; RT30xxReadRFRegister(pAd, RF_R17, &RfValue); beAdd = (RfValue < value) ? TRUE : FALSE; IdRf = RfValue; while(IdRf != value) { if (beAdd) IdRf++; else IdRf--; rfcsr.field.RF_CSR_DATA = IdRf; RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word); RtmpOsMsDelay(1); } } rfcsr.field.RF_CSR_DATA = value; RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word); return NDIS_STATUS_SUCCESS; }
/* ========================================================================== Description: Load RF sleep-mode setup ========================================================================== */ VOID RT33xxLoadRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; { // RF_BLOCK_en. RF R1 register Bit 0 to 0 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue &= (~0x01); RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // VCO_IC, RF R7 register Bit 4 & Bit 5 to 0 RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue &= (~0x30); RT30xxWriteRFRegister(pAd, RF_R07, RFValue); // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue &= (~0x0E); RT30xxWriteRFRegister(pAd, RF_R09, RFValue); // RX_CTB_en, RF R21 register Bit 7 to 0 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x80); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72 IS_RT3572(pAd) || IS_RT3390(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); RFValue |= 0x77; RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue |= 0x1D000000; RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ VOID RT33xxReverseRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; // RF_BLOCK_en, RF R1 register Bit 0 to 1 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // VCO_IC, RF R7 register Bit 4 & Bit 5 to 1 RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue |= 0x30; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1 RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue |= 0x0E; RT30xxWriteRFRegister(pAd, RF_R09, RFValue); // RX_CTB_en, RF R21 register Bit 7 to 1 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); if (IS_RT3390(pAd)) { // RT3071 version E has fixed this issue if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { // patch tx EVM issue temporarily RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } else { RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ VOID RT33xxReverseRFSleepModeSetup( IN PRTMP_ADAPTER pAd, IN BOOLEAN FlgIsInitState) { UCHAR RFValue; UINT32 MACValue; /* RF_BLOCK_en, RF R1 register Bit 0 to 1*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1*/ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); /* According to HK's comment for Max Input power issue. RF 07 must set to 0x60. */ RFValue |= 0x20; /* 0x30. */ RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 1*/ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); if (IS_RT3390(pAd)) { /* RT3071 version E has fixed this issue*/ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily*/ RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } else { RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } }
/* ======================================================================== Routine Description: Read RF register through MAC with specified bit mask Arguments: pAd - pointer to the adapter structure regID - RF register ID pValue1 - (RF value & BitMask) pValue2 - (RF value & (~BitMask)) BitMask - bit wise mask Return Value: Note: ======================================================================== */ VOID RTMP_ReadRF( IN RTMP_ADAPTER *pAd, IN UCHAR RegID, OUT UCHAR *val1, OUT UCHAR *val2, IN UCHAR BitMask) { UCHAR RfReg = 0; RT30xxReadRFRegister(pAd, RegID, &RfReg); if (val1 != NULL) *val1 = RfReg & BitMask; if (val2 != NULL) *val2 = RfReg & (~BitMask); }
/* ======================================================================== Routine Description: Read RF register through MAC with specified bit mask Arguments: pAd - pointer to the adapter structure regID - RF register ID pValue1 - (RF value & BitMask) pValue2 - (RF value & (~BitMask)) BitMask - bit wise mask Return Value: Note: ======================================================================== */ VOID RTMP_ReadRF( IN PRTMP_ADAPTER pAd, IN UCHAR RegID, OUT PUCHAR pValue1, OUT PUCHAR pValue2, IN UCHAR BitMask) { UCHAR RfReg = 0; RT30xxReadRFRegister(pAd, RegID, &RfReg); if (pValue1 != NULL) *pValue1 = RfReg & BitMask; if (pValue2 != NULL) *pValue2 = RfReg & (~BitMask); }
VOID RT35xx_NICInitAsicFromEEPROM( IN PRTMP_ADAPTER pAd) { UCHAR bbpreg = 0; UCHAR RFValue = 0; if (IS_RT3572(pAd)) { /* enable DC filter*/ if ((pAd->MACVersion & 0xffff) >= 0x0201) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R103, 0xc0); } /* improve power consumption */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg); if (pAd->Antenna.field.TxPath == 1) { /* turn off tx DAC_1 */ bbpreg = (bbpreg | 0x20); } if (pAd->Antenna.field.RxPath == 1) { /* turn off tx ADC_1*/ bbpreg &= (~0x2); } RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg); if ((pAd->MACVersion & 0xffff) >= 0x0211) { RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R31, &bbpreg); bbpreg &= (~0x3); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R31, bbpreg); } /* TX_LO1_en*/ RT30xxReadRFRegister(pAd, RF_R16, &RFValue); /* set RF_R16_bit[2:0] equal to EEPROM setting at 0x48h and the value should start from 2.*/ /*if (pAd->TxMixerGain24G >= 2)*/ { RFValue &= (~0x7); /* clean bit [2:0]*/ RFValue |= pAd->TxMixerGain24G; } RT30xxWriteRFRegister(pAd, RF_R16, RFValue); } }
INT rtmp_cfo_track(RTMP_ADAPTER *pAd, MAC_TABLE_ENTRY *pEntry, INT lastClient) { /* CFO Tracking */ if (IS_RT3883(pAd)) { if (pAd->MacTab.Size !=1 || pAd->CommonCfg.CFOTrack==0) { /* Set to default */ RT3883_AsicSetFreqOffset(pAd, pAd->RfFreqOffset); } else if ((lastClient < MAX_LEN_OF_MAC_TABLE) && (lastClient >=1) && pAd->CommonCfg.CFOTrack < 8 && pEntry->freqOffsetValid) { /* Track CFO */ SHORT foValue, offset = pEntry->freqOffset; UCHAR RFValue; RT30xxReadRFRegister(pAd, RF_R17, (PUCHAR)&RFValue); RFValue &= 0x7F; if (offset > 32) offset = 32; else if (offset < -32) offset = -32; foValue = RFValue - (offset/16); if (foValue < 0) foValue = 0; else if (foValue > 0x5F) foValue = 0x5F; if (foValue != RFValue) RT3883_AsicSetFreqOffset(pAd, foValue); /* If CFOTrack!=1 then keep updating until CFOTrack==8 */ if (pAd->CommonCfg.CFOTrack != 1) pAd->CommonCfg.CFOTrack++; pEntry->freqOffsetValid = FALSE; } } return TRUE; }
/* ========================================================================== Description: Load RF normal operation-mode setup ========================================================================== */ static VOID RT3593LoadRFNormalModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RfReg; CHAR bbpreg = 0; // TX_LO2_en RT30xxReadRFRegister(pAd, RF_R50, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x10) | 0x00); // tx_lo2_en (both bands, 0: LO2 follows TR switch) RT30xxWriteRFRegister(pAd, RF_R50, (UCHAR)RfReg); // TX_LO1_en, RX_MX2_GC RT30xxReadRFRegister(pAd, RF_R51, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x1C) | ((pAd->TxMixerGain24G & 0x07) << 2)); // tx_mx1_cc (RF mixer output tank tuning, both bands) RT30xxWriteRFRegister(pAd, RF_R51, (UCHAR)RfReg); // RX_LO1_en RT30xxReadRFRegister(pAd, RF_R38, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x20) | 0x00); // rx_lo1_en (enable RX LO1, 0: LO1 follows TR switch) RT30xxWriteRFRegister(pAd, RF_R38, (UCHAR)RfReg); // RX_LO2_en RT30xxReadRFRegister(pAd, RF_R39, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x80) | 0x00); // rx_lo2_en (enable RX LO2, 0: LO2 follows TR switch) RT30xxWriteRFRegister(pAd, RF_R39, (UCHAR)RfReg); // // Avoid data lost and CRC error // RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &bbpreg); bbpreg = ((bbpreg & ~0x40) | 0x40); // MAC interface control (MAC_IF_80M, 1: 80 MHz) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, bbpreg); RT30xxReadRFRegister(pAd, RF_R32, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x07) | 0x07); // BB_rx_out_en (enable DAC output or baseband input) //RT30xxWriteRFRegister(pAd, RF_R32, (UCHAR)RfReg); RT30xxReadRFRegister(pAd, RF_R01, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x03) | 0x03); // rf_block_en and pll_en RT30xxWriteRFRegister(pAd, RF_R01, (UCHAR)RfReg); RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x18) | 0x10); // rxvcm (Rx BB filter VCM) RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); } /* End of RT3593LoadRFNormalModeSetup */
INT rtmp_bbp_tx_comp_init(RTMP_ADAPTER *pAd, INT adc_insel, INT tssi_mode) { UCHAR bbp_val, rf_val; /* Set BBP_R47 */ RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R47, &bbp_val); bbp_val &= 0xe7; bbp_val |= ((tssi_mode << 3) & 0x18); bbp_val |= 0x80; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R47, bbp_val); /* Set RF_R27 */ RT30xxReadRFRegister(pAd, RF_R27, &rf_val); rf_val &= 0x3f; rf_val |= ((adc_insel << 6) & 0xc0); RT30xxWriteRFRegister(pAd, RF_R27, rf_val); DBGPRINT(RT_DEBUG_TRACE, ("[temp. compensation] Set RF_R27 to 0x%x\n", rf_val)); }
void NICInitRT3090RFRegisters(struct rt_rtmp_adapter *pAd) { int i; /* Driver must read EEPROM to get RfIcType before initial RF registers */ /* Initialize RF register to default value */ if (IS_RT3090(pAd)) { /* Init RF calibration */ /* Driver should toggle RF R30 bit7 before init RF registers */ u32 RfReg = 0, data; RT30xxReadRFRegister(pAd, RF_R30, (u8 *)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (u8)RfReg); /* init R24, R31 */ RT30xxWriteRFRegister(pAd, RF_R24, 0x0F); RT30xxWriteRFRegister(pAd, RF_R31, 0x0F); /* RT309x version E has fixed this issue */ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily */ RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } else { RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } /* patch LNA_PE_G1 failed issue */ RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); /* Initialize RF register to default value */ for (i = 0; i < NUM_RF_REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value); } /* Driver should set RF R6 bit6 on before calibration */ RT30xxReadRFRegister(pAd, RF_R06, (u8 *)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (u8)RfReg); /*For RF filter Calibration */ RTMPFilterCalibration(pAd); /* Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() */ if ((pAd->MACVersion & 0xffff) < 0x0211) RT30xxWriteRFRegister(pAd, RF_R27, 0x3); /* set led open drain enable */ RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); /* set default antenna as main */ if (pAd->RfIcType == RFIC_3020) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); /* add by johnli, RF power sequence setup, load RF normal operation-mode setup */ RT30xxLoadRFNormalModeSetup(pAd); } }
VOID NICInitRT3370RFRegisters(IN PRTMP_ADAPTER pAd) { INT i; UINT8 RfReg = 0; UINT32 data; CHAR bbpreg; /* Driver must read EEPROM to get RfIcType before initial RF registers*/ /* Initialize RF register to default value*/ /* Init RF calibration*/ /* Driver should toggle RF R30 bit7 before init RF registers*/ RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); for (i = 0; i < RT3370_NUM_RF_REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RT3370_RFRegTable[i].Register, RT3370_RFRegTable[i].Value); } /* Driver should set RF R6 bit6 on before init RF registers */ RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg); /* RT3071 version E has fixed this issue*/ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily*/ RTUSBReadMACRegister(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTUSBWriteMACRegister(pAd, LDO_CFG0, data); } else { /* patch CCK ok, OFDM failed issue, just toggle and restore LDO_CFG0.*/ RTUSBReadMACRegister(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTUSBWriteMACRegister(pAd, LDO_CFG0, data); RTMPusecDelay(1000); data = ((data & 0xE0FFFFFF) | 0x01000000); RTUSBWriteMACRegister(pAd, LDO_CFG0, data); } /* patch LNA_PE_G1 failed issue*/ RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); if (IS_RT3390(pAd)) /* Disable RF filter calibration*/ { pAd->Mlme.CaliBW20RfR24 = BW20RFR24; pAd->Mlme.CaliBW40RfR24 = BW40RFR24; pAd->Mlme.CaliBW20RfR31 = BW20RFR31; pAd->Mlme.CaliBW40RfR31 = BW40RFR31; } else { /*For RF filter Calibration*/ /*RTMPFilterCalibration(pAd);*/ } /* set led open drain enable*/ RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); /* set default antenna as main*/ if (pAd->RfIcType == RFIC_3320) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); /* From RT3071 Power Sequence v1.1 document, the Normal Operation Setting Registers as follow : BBP_R138 / RF_R1 / RF_R15 / RF_R17 / RF_R20 / RF_R21. */ /* add by johnli, RF power sequence setup, load RF normal operation-mode setup*/ RT33xxLoadRFNormalModeSetup(pAd); }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ VOID RT30xxReverseRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { #ifdef RT53xx if (IS_RT5390(pAd)) { UCHAR rfreg; RT30xxReadRFRegister(pAd, RF_R01, &rfreg); if (IS_RT5392(pAd)) { rfreg = ((rfreg & ~0x3F) | 0x3F); } else { rfreg = ((rfreg & ~0x0F) | 0x0F); // Enable rf_block_en, pll_en, rx0_en and tx0_en } RT30xxWriteRFRegister(pAd, RF_R01, rfreg); RT30xxReadRFRegister(pAd, RF_R06, &rfreg); if (IS_RT5390F(pAd) || IS_RT5392C(pAd)) { rfreg = ((rfreg & ~0xC0) | 0xC0); // vco_ic (VCO bias current control, 11: high) } else { rfreg = ((rfreg & ~0xC0) | 0x80); // vco_ic (VCO bias current control, 10: mid.) } RT30xxWriteRFRegister(pAd, RF_R06, rfreg); if (!IS_RT5392(pAd)) { RT30xxReadRFRegister(pAd, RF_R02, &rfreg); rfreg = ((rfreg & ~0x80) | 0x80); // rescal_en (initiate calibration) RT30xxWriteRFRegister(pAd, RF_R02, rfreg); } RT30xxReadRFRegister(pAd, RF_R22, &rfreg); rfreg = ((rfreg & ~0xE0) | 0x20); // cp_ic (reference current control, 001: 0.33 mA) RT30xxWriteRFRegister(pAd, RF_R22, rfreg); RT30xxReadRFRegister(pAd, RF_R42, &rfreg); rfreg = ((rfreg & ~0x40) | 0x40); // rx_ctb_en RT30xxWriteRFRegister(pAd, RF_R42, rfreg); RT30xxReadRFRegister(pAd, RF_R20, &rfreg); rfreg = ((rfreg & ~0x77) | 0x00); // ldo_rf_vc and ldo_pll_vc ( 111: +0.15) RT30xxWriteRFRegister(pAd, RF_R20, rfreg); RT30xxReadRFRegister(pAd, RF_R03, &rfreg); rfreg = ((rfreg & ~0x80) | 0x80); // vcocal_en (initiate VCO calibration (reset after completion)) RT30xxWriteRFRegister(pAd, RF_R03, rfreg); } else #endif // RT53xx // { // RF_BLOCK_en, RF R1 register Bit 0 to 1 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // VCO_IC, RF R7 register Bit 5 to 1 (VCO bias current control, 11: high) RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue |= 0x30; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1 RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue |= 0x0E; RT30xxWriteRFRegister(pAd, RF_R09, RFValue); // RX_CTB_en, RF R21 register Bit 7 to 1 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } } if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72 IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd) || IS_RT5390(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if ((!IS_RT3572(pAd)) && (!IS_RT3593(pAd)) && (!IS_RT5390(pAd)) && (!IS_RT3390(pAd)) && (!IS_RT3090(pAd))) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); if ((pAd->MACVersion & 0xffff) < 0x0211) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } // RT3071 version E has fixed this issue if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { // patch tx EVM issue temporarily RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } // else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd)) || (pAd->CommonCfg.PatchHWControl.field.LDOCfg == 1)) else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd) && !IS_RT5390(pAd))) { RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } if(IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, 0x80); }
/* ========================================================================== Description: Load RF sleep-mode setup ========================================================================== */ VOID RT30xxLoadRFSleepModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { #ifdef RT53xx if (IS_RT5390(pAd)) { UCHAR rfreg; RT30xxReadRFRegister(pAd, RF_R01, &rfreg); rfreg = ((rfreg & ~0x01) | 0x00); // vco_en RT30xxWriteRFRegister(pAd, RF_R01, rfreg); RT30xxReadRFRegister(pAd, RF_R06, &rfreg); rfreg = ((rfreg & ~0xC0) | 0x00); // vco_ic (VCO bias current control, 00: off) RT30xxWriteRFRegister(pAd, RF_R06, rfreg); RT30xxReadRFRegister(pAd, RF_R22, &rfreg); rfreg = ((rfreg & ~0xE0) | 0x00); // cp_ic (reference current control, 000: 0.25 mA) RT30xxWriteRFRegister(pAd, RF_R22, rfreg); RT30xxReadRFRegister(pAd, RF_R42, &rfreg); rfreg = ((rfreg & ~0x40) | 0x00); // rx_ctb_en RT30xxWriteRFRegister(pAd, RF_R42, rfreg); /* RT30xxReadRFRegister(pAd, RF_R20, &rfreg); rfreg = ((rfreg & ~0x77) | 0x77); // ldo_pll_vc and ldo_rf_vc (111: -0.15) RT30xxWriteRFRegister(pAd, RF_R20, rfreg); */ } else #endif // RT53xx // { // RF_BLOCK_en. RF R1 register Bit 0 to 0 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue &= (~0x01); RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // VCO_IC, RF R7 register Bit 4 & Bit 5 to 0 RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue &= (~0x30); RT30xxWriteRFRegister(pAd, RF_R07, RFValue); // Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue &= (~0x0E); RT30xxWriteRFRegister(pAd, RF_R09, RFValue); // RX_CTB_en, RF R21 register Bit 7 to 0 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x80); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } } // Don't touch LDO_CFG0 for 3090F & 3593, possibly the board is single power scheme if (IS_RT3090(pAd) || // IS_RT3090 including RT309x and RT3071/72 IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT5390(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if (!IS_RT3572(pAd) && !IS_RT3390(pAd) && !IS_RT5390(pAd) && !IS_RT3090(pAd)) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); RFValue |= 0x77; RT30xxWriteRFRegister(pAd, RF_R27, RFValue); RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue |= 0x1D000000; RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } }
/* ========================================================================== Description: Load RF normal operation-mode setup ========================================================================== */ VOID RT30xxLoadRFNormalModeSetup( IN PRTMP_ADAPTER pAd) { UCHAR RFValue, bbpreg = 0; { // improve power consumption RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R138, &bbpreg); if (pAd->Antenna.field.TxPath == 1) { // turn off tx DAC_1 bbpreg = (bbpreg | 0x20); } if (pAd->Antenna.field.RxPath == 1) { // turn off tx ADC_1 bbpreg &= (~0x2); } RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R138, bbpreg); } #ifdef RT53xx if (IS_RT5390(pAd)) { RT30xxReadRFRegister(pAd, RF_R38, (PUCHAR)&RFValue); RFValue = ((RFValue & ~0x20) | 0x00); // rx_lo1_en (enable RX LO1, 0: LO1 follows TR switch) RT30xxWriteRFRegister(pAd, RF_R38, (UCHAR)RFValue); RT30xxReadRFRegister(pAd, RF_R39, (PUCHAR)&RFValue); RFValue = ((RFValue & ~0x80) | 0x00); // rx_lo2_en (enable RX LO2, 0: LO2 follows TR switch) RT30xxWriteRFRegister(pAd, RF_R39, (UCHAR)RFValue); // // Avoid data lost and CRC error // RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &bbpreg); bbpreg = ((bbpreg & ~0x40) | 0x40); // MAC interface control (MAC_IF_80M, 1: 80 MHz) RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, bbpreg); RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RFValue); RFValue = ((RFValue & ~0x18) | 0x10); // rxvcm (Rx BB filter VCM) RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue); } else #endif //RT53xx // { // RX0_PD & TX0_PD, RF R1 register Bit 2 & Bit 3 to 0 and RF_BLOCK_en,RX1_PD & TX1_PD, Bit0, Bit 4 & Bit5 to 1 RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue = (RFValue & (~0x0C)) | 0x31; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); // TX_LO2_en, RF R15 register Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R15, &RFValue); RFValue &= (~0x08); RT30xxWriteRFRegister(pAd, RF_R15, RFValue); // TX_LO1_en, RF R17 register Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R17, &RFValue); RFValue &= (~0x08); // to fix rx long range issue if (((pAd->MACVersion & 0xffff) >= 0x0211) && (pAd->NicConfig2.field.ExternalLNAForG == 0)) { RFValue |= 0x20; } // set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h if (pAd->TxMixerGain24G >= 2) { RFValue &= (~0x7); // clean bit [2:0] RFValue |= pAd->TxMixerGain24G; } RT30xxWriteRFRegister(pAd, RF_R17, RFValue); // RX_LO1_en, RF R20 register Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R20, &RFValue); RFValue &= (~0x08); RT30xxWriteRFRegister(pAd, RF_R20, RFValue); // RX_LO2_en, RF R21 register Bit 3 to 0 RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue &= (~0x08); RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } }
/* ========================================================================== Description: Reverse RF sleep-mode setup ========================================================================== */ VOID RT30xxReverseRFSleepModeSetup( IN PRTMP_ADAPTER pAd, IN BOOLEAN FlgIsInitState) { UCHAR RFValue; UINT32 MACValue; if(!IS_RT3572(pAd)) { { /* RF_BLOCK_en, RF R1 register Bit 0 to 1*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue |= 0x01; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); /* VCO_IC, RF R7 register Bit 4 & Bit 5 to 1*/ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue |= 0x20; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); /* Idoh, RF R9 register Bit 1, Bit 2 & Bit 3 to 1*/ RT30xxReadRFRegister(pAd, RF_R09, &RFValue); RFValue |= 0x0E; RT30xxWriteRFRegister(pAd, RF_R09, RFValue); /* RX_CTB_en, RF R21 register Bit 7 to 1*/ RT30xxReadRFRegister(pAd, RF_R21, &RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R21, RFValue); } } if (IS_RT3090(pAd) || /* IS_RT3090 including RT309x and RT3071/72*/ IS_RT3572(pAd) || IS_RT3390(pAd) || IS_RT3593(pAd) || (IS_RT3070(pAd) && ((pAd->MACVersion & 0xffff) < 0x0201))) { if ((!IS_RT3572(pAd)) && (!IS_RT3593(pAd))) { RT30xxReadRFRegister(pAd, RF_R27, &RFValue); if ((pAd->MACVersion & 0xffff) < 0x0211) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); } /* RT3071 version E has fixed this issue*/ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily*/ RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } else if ((!IS_RT3090(pAd) && !IS_RT3593(pAd))) { RTMP_IO_READ32(pAd, LDO_CFG0, &MACValue); MACValue = ((MACValue & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, MACValue); } } if(IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, 0x80); }
VOID RT35xx_ChipSwitchChannel( IN PRTMP_ADAPTER pAd, IN UCHAR Channel, IN BOOLEAN bScan) { CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/ UCHAR index; UINT32 Value = 0; /*BbpReg, Value;*/ UCHAR RFValue; UINT32 i = 0; i = i; /* avoid compile warning */ RFValue = 0; /* Search Tx power value*/ /* We can't use ChannelList to search channel, since some central channl's txpowr doesn't list in ChannelList, so use TxPower array instead. */ for (index = 0; index < MAX_NUM_OF_CHANNELS; index++) { if (Channel == pAd->TxPower[index].Channel) { TxPwer = pAd->TxPower[index].Power; TxPwer2 = pAd->TxPower[index].Power2; break; } } if (index == MAX_NUM_OF_CHANNELS) { DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel)); } #ifdef RT35xx /* 3562:RFIC_3052/ 3062:RFIC_3022 */ if (IS_RT3572(pAd) /*&& (pAd->RfIcType == RFIC_3052)*/) { for (index = 0; index < NUM_OF_3572_CHNL; index++) { if (Channel == FreqItems3572[index].Channel) { /* for 2.4G, restore BBP25, BBP26*/ if (Channel <= 14) { BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, pAd->Bbp25); BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R26, pAd->Bbp26); } /* hard code for 5GGhz, Gary 2008-12-10*/ else { /* Enable IQ Phase Correction*/ BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x09); /* IQ Phase correction value*/ BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R26, 0xFF); } /* Programming channel parameters*/ RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3572[index].N); RT30xxWriteRFRegister(pAd, RF_R03, FreqItems3572[index].K); RT30xxReadRFRegister(pAd, RF_R06, &RFValue); if (Channel <= 14) RFValue = (RFValue & 0xF0) | FreqItems3572[index].R | 0x8; else RFValue = (RFValue & 0xF0) | FreqItems3572[index].R | 0x4; RT30xxWriteRFRegister(pAd, RF_R06, RFValue); /* Pll mode for 2.4G or 5G*/ RT30xxReadRFRegister(pAd, RF_R05, &RFValue); if (Channel <= 14) RFValue = (RFValue & 0xF3) | 0x4; else RFValue = (RFValue & 0xF3) | 0x8; RT30xxWriteRFRegister(pAd, RF_R05, RFValue); /* Set Tx0 Power*/ RT30xxReadRFRegister(pAd, RF_R12, (PUCHAR)&RFValue); if (Channel <= 14) RFValue = 0x60 | TxPwer; else RFValue = 0xE0 | (TxPwer & 0x3) | ((TxPwer & 0xC) << 1); RT30xxWriteRFRegister(pAd, RF_R12, RFValue); /* Set Tx1 Power*/ RT30xxReadRFRegister(pAd, RF_R13, (PUCHAR)&RFValue); if (Channel <= 14) RFValue = 0x60 | TxPwer2; else RFValue = 0xE0 | (TxPwer2 & 0x3) | ((TxPwer2 & 0xC) << 1); RT30xxWriteRFRegister(pAd, RF_R13, RFValue); /* Tx/Rx Stream setting*/ RT30xxReadRFRegister(pAd, RF_R01, (PUCHAR)&RFValue); RFValue &= 0x03; /*clear bit[7~2]*/ if (pAd->Antenna.field.TxPath == 1) RFValue |= 0xA0; else if (pAd->Antenna.field.TxPath == 2) RFValue |= 0x80; if (pAd->Antenna.field.RxPath == 1) RFValue |= 0x50; else if (pAd->Antenna.field.RxPath == 2) RFValue |= 0x40; RT30xxWriteRFRegister(pAd, RF_R01, (UCHAR)RFValue); /* Set RF offset*/ RT30xxReadRFRegister(pAd, RF_R23, (PUCHAR)&RFValue); RFValue = (RFValue & 0x80) | pAd->RfFreqOffset; RT30xxWriteRFRegister(pAd, RF_R23, (UCHAR)RFValue); /* Set BW*/ if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40)) { RFValue = pAd->Mlme.CaliBW40RfR24; /*DISABLE_11N_CHECK(pAd);*/ } else { RFValue = pAd->Mlme.CaliBW20RfR24; } /* R24, R31, one is for tx, the other is for rx*/ RT30xxWriteRFRegister(pAd, RF_R24, (UCHAR)RFValue); RT30xxWriteRFRegister(pAd, RF_R31, (UCHAR)RFValue); /* Enable RF tuning*/ RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue); if (Channel <= 14) /*RFValue = (RFValue & 0x37) | 0xCC;*/ RFValue = 0xd8; /*?? to check 3572?? hardcode*/ else RFValue = (RFValue & 0x37) | 0x14; RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue); /* TSSI_BS*/ RT30xxReadRFRegister(pAd, RF_R09, (PUCHAR)&RFValue); if (Channel <= 14) RFValue = 0xC3; /*RFValue = (RFValue & 0xBF) | 0x40;*/ else RFValue = 0xC0; /*RFValue = (RFValue & 0xBF) | 0x40;*/ RT30xxWriteRFRegister(pAd, RF_R09, (UCHAR)RFValue); /* Loop filter 1*/ RT30xxWriteRFRegister(pAd, RF_R10, (UCHAR)0xF1); /* Loop filter 2*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R11, (UCHAR)0xB9); else RT30xxWriteRFRegister(pAd, RF_R11, (UCHAR)0x00); /* tx_mx2_ic*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R15, (UCHAR)0x53); else RT30xxWriteRFRegister(pAd, RF_R15, (UCHAR)0x43); /* tx_mx1_ic*/ /*RT30xxReadRFRegister(pAd, RF_R16, (PUCHAR)&RFValue);*/ if (Channel <= 14) { RFValue = 0x4c; RFValue &= (~0x7); /* clean bit [2:0]*/ RFValue |= pAd->TxMixerGain24G; } else { RFValue = 0x7a; RFValue &= (~0x7); /* clean bit [2:0]*/ RFValue |= pAd->TxMixerGain5G; } RT30xxWriteRFRegister(pAd, RF_R16, (UCHAR)RFValue); /* tx_lo1*/ RT30xxWriteRFRegister(pAd, RF_R17, (UCHAR)0x23); /* tx_lo2*/ RFValue = ((Channel <= 14) ? (0x93) : ((Channel <= 64) ? (0xb7) : ((Channel <= 128) ? (0x74) : (0x72)))); RT30xxWriteRFRegister(pAd, RF_R19, (UCHAR)RFValue); /* rx_l01*/ RFValue = ((Channel <= 14) ? (0xB3) : ((Channel <= 64) ? (0xF6) : ((Channel <= 128) ? (0xF4) : (0xF3)))); RT30xxWriteRFRegister(pAd, RF_R20, (UCHAR)RFValue); /* pfd_delay*/ RFValue = ((Channel <= 14) ? (0x15) : ((Channel <= 64) ? (0x3d) : ((Channel <= 128) ? (0x01) : (0x01)))); RT30xxWriteRFRegister(pAd, RF_R25, (UCHAR)RFValue); /* rx_lo2*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R26, (UCHAR)0x85); else RT30xxWriteRFRegister(pAd, RF_R26, (UCHAR)0x87); /* ldo_rf_vc*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)0x00); else RT30xxWriteRFRegister(pAd, RF_R27, (UCHAR)0x01); /* drv_cc*/ if (Channel <= 14) RT30xxWriteRFRegister(pAd, RF_R29, (UCHAR)0x9B); else RT30xxWriteRFRegister(pAd, RF_R29, (UCHAR)0x9F); RTMP_IO_READ32(pAd, GPIO_CTRL_CFG, &Value); if (Channel <= 14) Value = ((Value & 0xFFFF7FFF) | 0x00000080); else Value = (Value & 0xFFFF7F7F); RTMP_IO_WRITE32(pAd, GPIO_CTRL_CFG, Value); /* Enable RF tuning, this must be in the last*/ RT30xxReadRFRegister(pAd, RF_R07, (PUCHAR)&RFValue); RFValue = RFValue | 0x1; RT30xxWriteRFRegister(pAd, RF_R07, (UCHAR)RFValue); RTMPusecDelay(2000); /* latch channel for future usage.*/ pAd->LatchRfRegs.Channel = Channel; DBGPRINT(RT_DEBUG_TRACE, ("RT35xx: SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n", Channel, pAd->RfIcType, TxPwer, TxPwer2, pAd->Antenna.field.TxPath, FreqItems3572[index].N, FreqItems3572[index].K, FreqItems3572[index].R)); break; } } } else #endif /* RT35xx */ { switch (pAd->RfIcType) { default: DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n", Channel, pAd->RfIcType)); break; } } /* Change BBP setting during siwtch from a->g, g->a*/ if (Channel <= 14) { ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); /* Rx High power VGA offset for LNA select*/ { if (pAd->NicConfig2.field.ExternalLNAForG) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); } } /* 5G band selection PIN, bit1 and bit2 are complement*/ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x6); Value |= (0x04); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00); #endif /* RT35xx */ { /* Turn off unused PA or LNA when only 1T or 1R*/ if (pAd->Antenna.field.TxPath == 1) { TxPinCfg &= 0xFFFFFFF3; } if (pAd->Antenna.field.RxPath == 1) { TxPinCfg &= 0xFFFFF3FF; } } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x80); #endif /* RT35xx */ } else { ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/ UINT8 bbpValue; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue. */ /* Set the BBP_R82 value here */ bbpValue = 0xF2; #ifdef RT35xx if (IS_RT3572(pAd)) { /* TODO: check if the BBP_R82 value is the same in both of following cases!!!*/ /* Rx High power VGA offset for LNA select*/ bbpValue = 0x94; } #endif /* RT35xx */ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue); /* Rx High power VGA offset for LNA select*/ if (pAd->NicConfig2.field.ExternalLNAForA) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); } /* 5G band selection PIN, bit1 and bit2 are complement*/ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x6); Value |= (0x02); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* Turn off unused PA or LNA when only 1T or 1R*/ #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x00); #endif /* RT35xx */ { /* Turn off unused PA or LNA when only 1T or 1R*/ if (pAd->Antenna.field.TxPath == 1) { TxPinCfg &= 0xFFFFFFF3; } if (pAd->Antenna.field.RxPath == 1) { TxPinCfg &= 0xFFFFF3FF; } } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); #ifdef RT35xx if (IS_RT3572(pAd)) RT30xxWriteRFRegister(pAd, RF_R08, (UCHAR)0x80); #endif /* RT35xx */ } /* R66 should be set according to Channel and use 20MHz when scanning*/ /*RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R66, (0x2E + GET_LNA_GAIN(pAd)));*/ if (bScan) RTMPSetAGCInitValue(pAd, BW_20); else RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW); /* On 11A, We should delay and wait RF/BBP to be stable*/ /* and the appropriate time should be 1000 micro seconds */ /* 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL.*/ RTMPusecDelay(1000); }
VOID NICInitRT3070RFRegisters(IN PRTMP_ADAPTER pAd) { INT i; UCHAR RFValue; /* Driver must read EEPROM to get RfIcType before initial RF registers Initialize RF register to default value */ if (IS_RT3070(pAd) || IS_RT3071(pAd)) { /* Init RF calibration Driver should toggle RF R30 bit7 before init RF registers */ UINT8 RfReg = 0; UINT32 data; RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); /* set default antenna as main */ if (pAd->RfIcType == RFIC_3020 || pAd->RfIcType == RFIC_2020) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); /* Initialize RF register to default value */ for (i = 0; i < NUM_RF_3020_REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RT3020_RFRegTable[i].Register, RT3020_RFRegTable[i].Value); } RT30xxWriteRFRegister(pAd, RF_R31, 0x14); /* add by johnli */ if (IS_RT3070(pAd)) { /* The DAC issue(LDO_CFG0) has been fixed in RT3070(F). The voltage raising patch is no longer needed for RT3070(F) */ if ((pAd->MACVersion & 0xffff) < 0x0201) { /* Update MAC 0x05D4 from 01xxxxxx to 0Dxxxxxx (voltage 1.2V to 1.35V) for RT3070 to improve yield rate */ RTUSBReadMACRegister(pAd, LDO_CFG0, &data); data = ((data & 0xF0FFFFFF) | 0x0D000000); RTUSBWriteMACRegister(pAd, LDO_CFG0, data); } } else if (IS_RT3071(pAd)) { /* Driver should set RF R6 bit6 on before init RF registers */ RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg); /* RT3071 version E has fixed this issue */ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily */ RTUSBReadMACRegister(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTUSBWriteMACRegister(pAd, LDO_CFG0, data); } else { RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } /* patch LNA_PE_G1 failed issue */ RTUSBReadMACRegister(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTUSBWriteMACRegister(pAd, GPIO_SWITCH, data); } /* For RF filter Calibration */ RTMPFilterCalibration(pAd); /* Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F). Raising RF voltage is no longer needed for RT3070(F) */ if ((IS_RT3070(pAd)) && ((pAd->MACVersion & 0xffff) < 0x0201)) { RT30xxWriteRFRegister(pAd, RF_R27, 0x3); } else if ((IS_RT3071(pAd)) && ((pAd->MACVersion & 0xffff) < 0x0211)) { RT30xxWriteRFRegister(pAd, RF_R27, 0x3); } /* set led open drain enable */ RTUSBReadMACRegister(pAd, OPT_14, &data); data |= 0x01; RTUSBWriteMACRegister(pAd, OPT_14, data); if (IS_RT3071(pAd)) { /* RF power sequence setup, load RF normal operation-mode setup */ RT30xxLoadRFNormalModeSetup(pAd); } else if (IS_RT3070(pAd)) { /* TX_LO1_en, RF R17 register Bit 3 to 0 */ RT30xxReadRFRegister(pAd, RF_R17, &RFValue); RFValue &= (~0x08); /* to fix rx long range issue */ if (pAd->NicConfig2.field.ExternalLNAForG == 0) { if ((IS_RT3071(pAd) && ((pAd->MACVersion & 0xffff) >= 0x0211)) || IS_RT3070(pAd)) { RFValue |= 0x20; } } /* set RF_R17_bit[2:0] equal to EEPROM setting at 0x48h */ if (pAd->TxMixerGain24G >= 1) { RFValue &= (~0x7); /* clean bit [2:0] */ RFValue |= pAd->TxMixerGain24G; } RT30xxWriteRFRegister(pAd, RF_R17, RFValue); /* add by johnli, reset RF_R27 when interface down & up to fix throughput problem */ /* LDORF_VC, RF R27 register Bit 2 to 0 */ RT30xxReadRFRegister(pAd, RF_R27, &RFValue); /* TX to RX IQ glitch(RF_R27) has been fixed in RT3070(F). Raising RF voltage is no longer needed for RT3070(F) */ if ((pAd->MACVersion & 0xffff) < 0x0201) RFValue = (RFValue & (~0x77)) | 0x3; else RFValue = (RFValue & (~0x77)); RT30xxWriteRFRegister(pAd, RF_R27, RFValue); /* end johnli */ } } }
/* ======================================================================== Routine Description: Write RT30xx RF register through MAC Arguments: Return Value: IRQL = Note: ======================================================================== */ NDIS_STATUS RT30xxWriteRFRegister( IN PRTMP_ADAPTER pAd, IN UCHAR regID, IN UCHAR value) { RF_CSR_CFG_STRUC rfcsr = { { 0 } }; UINT i = 0; #ifdef RTMP_MAC_PCI if ((pAd->bPCIclkOff == TRUE) || (pAd->LastMCUCmd == SLEEP_MCU_CMD)) { DBGPRINT_ERR(("RT30xxWriteRFRegister. Not allow to write RF 0x%x : fail\n", regID)); return STATUS_UNSUCCESSFUL; } #endif /* RTMP_MAC_PCI */ { ASSERT((regID <= pAd->chipCap.MaxNumOfRfId)); /* R0~R31 or R63*/ do { RTMP_IO_READ32(pAd, RF_CSR_CFG, &rfcsr.word); if (!rfcsr.field.RF_CSR_KICK) break; i++; } while ((i < RETRY_LIMIT) && (!RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))); if ((i == RETRY_LIMIT) || (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST))) { DBGPRINT_RAW(RT_DEBUG_ERROR, ("Retry count exhausted or device removed!!!\n")); return STATUS_UNSUCCESSFUL; } if ((pAd->chipCap.RfReg17WtMethod == RF_REG_WT_METHOD_STEP_ON) && (regID == RF_R17)) { UCHAR IdRf; UCHAR RfValue; RT30xxReadRFRegister(pAd, RF_R17, &RfValue); rfcsr.field.RF_CSR_WR = 1; rfcsr.field.RF_CSR_KICK = 1; rfcsr.field.TESTCSR_RFACC_REGNUM = regID; /* R0~R31*/ if (RfValue <= value) { for(IdRf=RfValue; IdRf<=value; IdRf++) { rfcsr.field.RF_CSR_DATA = IdRf; RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word); RtmpOsMsDelay(1); } } else { for(IdRf=RfValue; IdRf>value; IdRf--) { rfcsr.field.RF_CSR_DATA = IdRf; RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word); RtmpOsMsDelay(1); } rfcsr.field.RF_CSR_DATA = value; RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word); } } else { rfcsr.field.RF_CSR_WR = 1; rfcsr.field.RF_CSR_KICK = 1; rfcsr.field.TESTCSR_RFACC_REGNUM = regID; /* R0~R31*/ rfcsr.field.RF_CSR_DATA = value; RTMP_IO_WRITE32(pAd, RF_CSR_CFG, rfcsr.word); } } return NDIS_STATUS_SUCCESS; }
VOID NICInitRT3390RFRegisters(IN PRTMP_ADAPTER pAd) { INT i; UINT8 RfReg = 0; UINT32 data; /*CHAR bbpreg;*/ // Driver must read EEPROM to get RfIcType before initial RF registers // Initialize RF register to default value // Init RF calibration // Driver should toggle RF R30 bit7 before init RF registers RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); // init R24, R31 // RT30xxWriteRFRegister(pAd, RF_R24, 0x0F); // RT30xxWriteRFRegister(pAd, RF_R31, 0x0F); if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } else { RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); RTMPusecDelay(1000); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } if (IS_RT3071(pAd) || IS_RT3390(pAd)) { RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); // RF registers initialization for (i = 0; i < NUM_RF_3320_REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RF3320_RFRegTable[i].Register, RF3320_RFRegTable[i].Value); } // Driver should set RF R6 bit6 on before calibration RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg); if (IS_RT3390(pAd)) // Disable RF filter calibration { // Disable RF filter calibration pAd->Mlme.CaliBW20RfR24 = BW20RFR24; pAd->Mlme.CaliBW40RfR24 = BW40RFR24; pAd->Mlme.CaliBW20RfR31 = BW20RFR31; pAd->Mlme.CaliBW40RfR31 = BW40RFR31; } else { //For RF filter Calibration //RT33xxFilterCalibration(pAd); } // Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() if ((pAd->MACVersion & 0xffff) < 0x0211) RT30xxWriteRFRegister(pAd, RF_R27, 0x3); // set led open drain enable RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); // Initialize RT3090 serial MAc registers which is different from RT2860 serial RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0); // RT3071 version E has fixed this issue if ((pAd->MACVersion & 0xffff) < 0x0211) { if (pAd->NicConfig2.field.DACTestBit == 1) { RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x1F); // To fix throughput drop drastically } else { RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0F); // To fix throughput drop drastically } } else { RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0); } // set default antenna as main if (pAd->RfIcType == RFIC_3320) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); /* From RT3071 Power Sequence v1.1 document, the Normal Operation Setting Registers as follow : BBP_R138 / RF_R1 / RF_R15 / RF_R17 / RF_R20 / RF_R21. */ // RF power sequence setup, load RF normal operation-mode setup RT33xxLoadRFNormalModeSetup(pAd); } }
VOID NICInitRT3593RFRegisters( IN PRTMP_ADAPTER pAd) { ULONG RfReg = 0; ULONG data; USHORT i; // if (IS_RT3593(pAd)) { // Init RF calibration // Driver should toggle RF R30 bit7 before init RF registers RT30xxReadRFRegister(pAd, RF_R02, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0x80) | 0x80); // rescal_en (initiate calbration) RT30xxWriteRFRegister(pAd, RF_R02, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg = (RfReg & ~0x80); // rescal_en (initiate calbration) RT30xxWriteRFRegister(pAd, RF_R02, (UCHAR)RfReg); // init R24, R31 RT30xxReadRFRegister(pAd, RF_R32, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0xF8) | 0x78); // tx_agc_fc (capacitor control in Tx baseband filter) //RT30xxWriteRFRegister(pAd, RF_R32, (UCHAR)RfReg); RT30xxReadRFRegister(pAd, RF_R31, (PUCHAR)&RfReg); RfReg = ((RfReg & ~0xF8) | 0x78); // rx_agc_fc (capacitor control in Rx baseband filter) //RT30xxWriteRFRegister(pAd, RF_R31, (UCHAR)RfReg); // RT3071 version E has fixed this issue if ((pAd->MACVersion & 0xffff) < 0x0211) { if (pAd->NicConfig2.field.DACTestBit == 1) { // patch tx EVM issue temporarily RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } } else { // Patch CCK ok, OFDM failed issue, just toggle and restore LDO_CFG0. // Patch SRAM for 3572, increase voltage to 1.35V on core voltage and down to 1.2V after 1 msec RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); RTMPusecDelay(1000); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } // patch LNA_PE_G1 failed issue RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); // Initialize RF register to default value for (i = 0; i < NUM_RF_3053_REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RF3053RegTable[i].Register, RF3053RegTable[i].Value); } // Driver should set RF R6 bit6 on before calibration RT30xxReadRFRegister(pAd, RF_R18, (PUCHAR)&RfReg); RfReg |= ((RfReg & ~0x40) | 0x40); // xo_tune_bypass (0: XO is auto-tuned and 1: XO tuning bypassed) RT30xxWriteRFRegister(pAd, RF_R18, (UCHAR)RfReg); //For RF filter Calibration RTMPFilterCalibration(pAd); //2 TODO:? pAd->Mlme.CaliBW20RfR24 = 0x1F; pAd->Mlme.CaliBW40RfR24 = 0x2F; // save R25, R26 for 2.4GHz RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R25, &pAd->Bbp25); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R26, &pAd->Bbp26); // Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() if ((pAd->MACVersion & 0xffff) < 0x0211) RT30xxWriteRFRegister(pAd, RF_R27, 0x3); // set led open drain enable RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); // Initialize RT3090 serial MAc registers which is different from RT2860 serial RTMP_IO_WRITE32(pAd, TX_SW_CFG1, 0); // RT3071 version E has fixed this issue if ((pAd->MACVersion & 0xffff) < 0x0211) { if (pAd->NicConfig2.field.DACTestBit == 1) { RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x1F); // To fix throughput drop drastically } else { RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0F); // To fix throughput drop drastically } } else { RTMP_IO_WRITE32(pAd, TX_SW_CFG2, 0x0); } // set default antenna as main if (pAd->RfIcType == RFIC_3020) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); // add by johnli, RF power sequence setup, load RF normal operation-mode setup RT3593LoadRFNormalModeSetup(pAd); // adjust some BBP register contents // also can put these BBP registers to pBBPRegTable RT3593_PostBBPInitialization(pAd); } } /* End of NICInitRT3593RFRegisters */
UINT32 SetHWAntennaDivsersity( IN PRTMP_ADAPTER pAd, IN BOOLEAN Enable) { if (Enable == TRUE) { UINT8 BBPValue = 0, RFValue = 0; USHORT value; // RF_R29 bit7:6 RT28xx_EEPROM_READ16(pAd, EEPROM_RSSI_GAIN, value); RT30xxReadRFRegister(pAd, RF_R29, &RFValue); RFValue &= 0x3f; // clear bit7:6 RFValue |= (value << 6); RT30xxWriteRFRegister(pAd, RF_R29, RFValue); // BBP_R47 bit7=1 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R47, &BBPValue); BBPValue |= 0x80; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R47, BBPValue); BBPValue = 0xbe; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R150, BBPValue); BBPValue = 0xb0; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R151, BBPValue); BBPValue = 0x23; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R152, BBPValue); BBPValue = 0x3a; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R153, BBPValue); BBPValue = 0x10; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R154, BBPValue); BBPValue = 0x3b; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R155, BBPValue); BBPValue = 0x04; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R253, BBPValue); DBGPRINT(RT_DEBUG_TRACE, ("HwAnDi> Enable!\n")); } else { UINT8 BBPValue = 0; /* main antenna: BBP_R152 bit7=1 aux antenna: BBP_R152 bit7=0 */ if (pAd->FixDefaultAntenna == 0) { /* fix to main antenna */ /* do not care BBP R153, R155, R253 */ BBPValue = 0x3e; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R150, BBPValue); BBPValue = 0x30; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R151, BBPValue); BBPValue = 0x23; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R152, BBPValue); BBPValue = 0x00; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R154, BBPValue); } else { /* fix to aux antenna */ /* do not care BBP R153, R155, R253 */ BBPValue = 0x3e; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R150, BBPValue); BBPValue = 0x30; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R151, BBPValue); BBPValue = 0xa3; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R152, BBPValue); BBPValue = 0x00; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R154, BBPValue); } DBGPRINT(RT_DEBUG_TRACE, ("HwAnDi> Disable!\n")); } return 0; }
VOID RT30xx_ChipSwitchChannel( IN PRTMP_ADAPTER pAd, IN UCHAR Channel, IN BOOLEAN bScan) { CHAR TxPwer = 0, TxPwer2 = DEFAULT_RF_TX_POWER; /*Bbp94 = BBPR94_DEFAULT, TxPwer2 = DEFAULT_RF_TX_POWER;*/ UCHAR index; UINT32 Value = 0; /*BbpReg, Value;*/ UCHAR RFValue; UINT32 i = 0; UCHAR Tx0FinePowerCtrl = 0, Tx1FinePowerCtrl = 0; BBP_R109_STRUC BbpR109 = {{0}}; i = i; /* avoid compile warning */ RFValue = 0; /* Search Tx power value*/ /* We can't use ChannelList to search channel, since some central channl's txpowr doesn't list in ChannelList, so use TxPower array instead. */ for (index = 0; index < MAX_NUM_OF_CHANNELS; index++) { if (Channel == pAd->TxPower[index].Channel) { TxPwer = pAd->TxPower[index].Power; TxPwer2 = pAd->TxPower[index].Power2; #ifdef RT33xx #endif /* RT33xx */ break; } } if (index == MAX_NUM_OF_CHANNELS) { DBGPRINT(RT_DEBUG_ERROR, ("AsicSwitchChannel: Can't find the Channel#%d \n", Channel)); } #ifdef RT30xx /* The RF programming sequence is difference between 3xxx and 2xxx*/ if ((IS_RT30xx(pAd)) && ((pAd->RfIcType == RFIC_3020) || (pAd->RfIcType == RFIC_2020) || (pAd->RfIcType == RFIC_3021) || (pAd->RfIcType == RFIC_3022) || (pAd->RfIcType == RFIC_3320))) { /* modify by WY for Read RF Reg. error */ UCHAR calRFValue; for (index = 0; index < NUM_OF_3020_CHNL; index++) { if (Channel == FreqItems3020[index].Channel) { /* Programming channel parameters*/ RT30xxWriteRFRegister(pAd, RF_R02, FreqItems3020[index].N); /* RT3370/RT3390 RF version is 0x3320 RF_R3 [7:4] is not reserved bits RF_R3[6:4] (pa1_bc_cck) : PA1 Bias CCK RF_R3[7] (pa2_cc_cck) : PA2 Cascode Bias CCK */ RT30xxReadRFRegister(pAd, RF_R03, (PUCHAR)(&RFValue)); RFValue = (RFValue & 0xF0) | (FreqItems3020[index].K & ~0xF0); /* <bit 3:0>:K<bit 3:0>*/ RT30xxWriteRFRegister(pAd, RF_R03, RFValue); RT30xxReadRFRegister(pAd, RF_R06, &RFValue); RFValue = (RFValue & 0xFC) | FreqItems3020[index].R; RT30xxWriteRFRegister(pAd, RF_R06, RFValue); /* Set Tx0 Power*/ RT30xxReadRFRegister(pAd, RF_R12, &RFValue); RFValue = (RFValue & 0xE0) | TxPwer; RT30xxWriteRFRegister(pAd, RF_R12, RFValue); /*Set Tx1 Power*/ RT30xxReadRFRegister(pAd, RF_R13, &RFValue); RFValue = (RFValue & 0xE0) | TxPwer2; RT30xxWriteRFRegister(pAd, RF_R13, RFValue); #ifdef RT33xx #endif /* RT33xx */ /* Tx/Rx Stream setting*/ RT30xxReadRFRegister(pAd, RF_R01, &RFValue); RFValue &= 0x03; /*clear bit[7~2]*/ if (pAd->Antenna.field.TxPath == 1) RFValue |= 0xA0; else if (pAd->Antenna.field.TxPath == 2) RFValue |= 0x80; if (pAd->Antenna.field.RxPath == 1) RFValue |= 0x50; else if (pAd->Antenna.field.RxPath == 2) RFValue |= 0x40; RT30xxWriteRFRegister(pAd, RF_R01, RFValue); RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue); RTMPusecDelay(1000); RFValue &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue); /* Set RF offset*/ RT30xxReadRFRegister(pAd, RF_R23, &RFValue); RFValue = (RFValue & 0x80) | pAd->RfFreqOffset; RT30xxWriteRFRegister(pAd, RF_R23, RFValue); /* Set BW*/ if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40)) { calRFValue = pAd->Mlme.CaliBW40RfR24; } else { calRFValue = pAd->Mlme.CaliBW20RfR24; } /* RT3370/RT3390 RF version is 0x3320 RF_R24 [7:6] is not reserved bits RF_R24[6] (BB_Rx1_out_en) : enable baseband output and ADC input RF_R24[7] (BB_Tx1_out_en) : enable DAC output or baseband input */ RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RFValue)); calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0>*/ RT30xxWriteRFRegister(pAd, RF_R24, calRFValue); /* RT3370/RT3390 RF version is 0x3320 RF_R31 [7:6] is not reserved bits RF_R31[4:0] (rx_agc_fc) : capacitor control in baseband filter RF_R31[5] (rx_ h20M) : rx_ h20M: 0=10 MHz and 1=20MHz RF_R31[7:6] (drv_bc_cck) : Driver Bias CCK */ /* Set BW*/ if (IS_RT3390(pAd)) /* RT3390 has different AGC for Tx and Rx*/ { if (!bScan && (pAd->CommonCfg.BBPCurrentBW == BW_40)) { calRFValue = pAd->Mlme.CaliBW40RfR31; } else { calRFValue = pAd->Mlme.CaliBW20RfR31; } } RT30xxReadRFRegister(pAd, RF_R31, (PUCHAR)(&RFValue)); calRFValue = (RFValue & 0xC0) | (calRFValue & ~0xC0); /* <bit 5>:rx_h20M<bit 5> and <bit 4:0>:rx_agc_fc<bit 4:0>*/ RT30xxWriteRFRegister(pAd, RF_R31, calRFValue); /* Enable RF tuning*/ RT30xxReadRFRegister(pAd, RF_R07, &RFValue); RFValue = RFValue | 0x1; RT30xxWriteRFRegister(pAd, RF_R07, RFValue); RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RFValue); RFValue |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue); RTMPusecDelay(1000); RFValue &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RFValue); /* latch channel for future usage.*/ pAd->LatchRfRegs.Channel = Channel; DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d(RF=%d, Pwr0=%d, Pwr1=%d, %dT), N=0x%02X, K=0x%02X, R=0x%02X\n", Channel, pAd->RfIcType, TxPwer, TxPwer2, pAd->Antenna.field.TxPath, FreqItems3020[index].N, FreqItems3020[index].K, FreqItems3020[index].R)); break; } } } else #endif /* RT30xx */ { switch (pAd->RfIcType) { default: DBGPRINT(RT_DEBUG_TRACE, ("SwitchChannel#%d : unknown RFIC=%d\n", Channel, pAd->RfIcType)); break; } } /* Change BBP setting during siwtch from a->g, g->a*/ if (Channel <= 14) { ULONG TxPinCfg = 0x00050F0A;/*Gary 2007/08/09 0x050A0A*/ RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/ /* Rx High power VGA offset for LNA select*/ { if (pAd->NicConfig2.field.ExternalLNAForG) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x62); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, 0x84); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); } } /* 5G band selection PIN, bit1 and bit2 are complement*/ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x6); Value |= (0x04); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); { /* Turn off unused PA or LNA when only 1T or 1R*/ if (pAd->Antenna.field.TxPath == 1) { TxPinCfg &= 0xFFFFFFF3; } if (pAd->Antenna.field.RxPath == 1) { TxPinCfg &= 0xFFFFF3FF; } } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); } else { ULONG TxPinCfg = 0x00050F05;/*Gary 2007/8/9 0x050505*/ UINT8 bbpValue; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R62, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R63, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R64, (0x37 - GET_LNA_GAIN(pAd))); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R86, 0);/*(0x44 - GET_LNA_GAIN(pAd))); According the Rory's suggestion to solve the middle range issue.*/ /* Set the BBP_R82 value here */ bbpValue = 0xF2; RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R82, bbpValue); /* Rx High power VGA offset for LNA select*/ if (pAd->NicConfig2.field.ExternalLNAForA) { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x46); } else { RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R75, 0x50); } /* 5G band selection PIN, bit1 and bit2 are complement*/ RTMP_IO_READ32(pAd, TX_BAND_CFG, &Value); Value &= (~0x6); Value |= (0x02); RTMP_IO_WRITE32(pAd, TX_BAND_CFG, Value); /* Turn off unused PA or LNA when only 1T or 1R*/ { /* Turn off unused PA or LNA when only 1T or 1R*/ if (pAd->Antenna.field.TxPath == 1) { TxPinCfg &= 0xFFFFFFF3; } if (pAd->Antenna.field.RxPath == 1) { TxPinCfg &= 0xFFFFF3FF; } } RTMP_IO_WRITE32(pAd, TX_PIN_CFG, TxPinCfg); } /* R66 should be set according to Channel and use 20MHz when scanning*/ if (bScan) RTMPSetAGCInitValue(pAd, BW_20); else RTMPSetAGCInitValue(pAd, pAd->CommonCfg.BBPCurrentBW); /* On 11A, We should delay and wait RF/BBP to be stable and the appropriate time should be 1000 micro seconds 2005/06/05 - On 11G, We also need this delay time. Otherwise it's difficult to pass the WHQL. */ RTMPusecDelay(1000); }
VOID NICInitRT3572RFRegisters(IN PRTMP_ADAPTER pAd) { INT i; UINT8 RfReg = 0; UINT32 data; /* Driver must read EEPROM to get RfIcType before initial RF registers Initialize RF register to default value Init RF calibration Driver should toggle RF R30 bit7 before init RF registers */ RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); /* Initialize RF register to default value */ for (i = 0; i < NUM_RF_3572REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RF3572_RFRegTable[i].Register, RF3572_RFRegTable[i].Value); } /* Driver should set RF R6 bit6 on before init RF registers */ RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg); /* init R31 */ /*RT30xxWriteRFRegister(pAd, RF_R31, 0x14);*/ if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { /* patch tx EVM issue temporarily */ RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xF0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } else { /* Patch for SRAM, increase voltage to 1.35V on core voltage and down to 1.2V after 1 msec*/ RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); RTMPusecDelay(1000); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } /* patch LNA_PE_G1 (toggle GPIO_SWITCH) is not necessary for 3572 */ /* RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); */ /* For RF filter Calibration */ RTMPFilterCalibration(pAd); /* save R25, R26 for 2.4GHz */ BBP_IO_READ8_BY_REG_ID(pAd, BBP_R25, &pAd->Bbp25); BBP_IO_READ8_BY_REG_ID(pAd, BBP_R26, &pAd->Bbp26); /* set led open drain enable */ RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); }
VOID NICInitRT3370RFRegisters(IN PRTMP_ADAPTER pAd) { INT i; // Driver must read EEPROM to get RfIcType before initial RF registers // Initialize RF register to default value if (IS_RT3090(pAd)||IS_RT3390(pAd)||IS_RT3572(pAd)) { // Init RF calibration // Driver should toggle RF R30 bit7 before init RF registers UINT32 RfReg = 0, data; RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); // init R24, R31 RT30xxWriteRFRegister(pAd, RF_R24, 0x0F); RT30xxWriteRFRegister(pAd, RF_R31, 0x0F); if (IS_RT3390(pAd)) { // patch LNA_PE_G1 failed issue RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); // RF registers initialization for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++) { RT30xxWriteRFRegister(pAd, RFRegTableOverRT3390[i].Register, RFRegTableOverRT3390[i].Value); } } // patch LNA_PE_G1 failed issue RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); // Initialize RF register to default value for (i = 0; i < NUM_RF_REG_PARMS_OVER_RT3390; i++) { RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value); } // Driver should set RF R6 bit6 on before calibration RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg); //For RF filter Calibration RTMPFilterCalibration(pAd); // Initialize RF R27 register, set RF R27 must be behind RTMPFilterCalibration() if ((pAd->MACVersion & 0xffff) < 0x0211) RT30xxWriteRFRegister(pAd, RF_R27, 0x3); // set led open drain enable RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); // set default antenna as main if (pAd->RfIcType == RFIC_3020) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); // add by johnli, RF power sequence setup, load RF normal operation-mode setup RT30xxLoadRFNormalModeSetup(pAd); } }
/* ======================================================================== Routine Description: For RF filter calibration purpose Arguments: pAd Pointer to our adapter Return Value: None IRQL = PASSIVE_LEVEL ======================================================================== */ VOID RTMPFilterCalibration( IN PRTMP_ADAPTER pAd) { UCHAR R55x = 0, value, FilterTarget = 0x1E, BBPValue=0; UINT loop = 0, count = 0, loopcnt = 0, ReTry = 0; UCHAR RF_R24_Value = 0; // Give bbp filter initial value pAd->Mlme.CaliBW20RfR24 = 0x1F; pAd->Mlme.CaliBW40RfR24 = 0x2F; //Bit[5] must be 1 for BW 40 do { if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) return; if (loop == 1) //BandWidth = 40 MHz { // Write 0x27 to RF_R24 to program filter RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RF_R24_Value)); RF_R24_Value = (RF_R24_Value & 0xC0) | 0x27; // <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0> RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value); if (IS_RT3071(pAd) || IS_RT3572(pAd)) FilterTarget = 0x15; else FilterTarget = 0x19; // when calibrate BW40, BBP mask must set to BW40. RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue); BBPValue&= (~0x18); BBPValue|= (0x10); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue); // set to BW40 RT30xxReadRFRegister(pAd, RF_R31, &value); value |= 0x20; RT30xxWriteRFRegister(pAd, RF_R31, value); } else //BandWidth = 20 MHz { // Write 0x07 to RF_R24 to program filter RT30xxReadRFRegister(pAd, RF_R24, (PUCHAR)(&RF_R24_Value)); RF_R24_Value = (RF_R24_Value & 0xC0) | 0x07; // <bit 5>:tx_h20M<bit 5> and <bit 4:0>:tx_agc_fc<bit 4:0> RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value); if (IS_RT3071(pAd) || IS_RT3572(pAd)) FilterTarget = 0x13; else FilterTarget = 0x16; // set to BW20 RT30xxReadRFRegister(pAd, RF_R31, &value); value &= (~0x20); RT30xxWriteRFRegister(pAd, RF_R31, value); } // Write 0x01 to RF_R22 to enable baseband loopback mode RT30xxReadRFRegister(pAd, RF_R22, &value); value |= 0x01; RT30xxWriteRFRegister(pAd, RF_R22, value); // Write 0x00 to BBP_R24 to set power & frequency of passband test tone RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0); do { if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) return; // Write 0x90 to BBP_R25 to transmit test tone RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90); RTMPusecDelay(1000); // Read BBP_R55[6:0] for received power, set R55x = BBP_R55[6:0] RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value); R55x = value & 0xFF; } while ((ReTry++ < 100) && (R55x == 0)); // Write 0x06 to BBP_R24 to set power & frequency of stopband test tone RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0x06); while(TRUE) { if (RTMP_TEST_FLAG(pAd, fRTMP_ADAPTER_NIC_NOT_EXIST)) return; // Write 0x90 to BBP_R25 to transmit test tone RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, 0x90); //We need to wait for calibration RTMPusecDelay(1000); RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R55, &value); value &= 0xFF; if ((R55x - value) < FilterTarget) { RF_R24_Value ++; } else if ((R55x - value) == FilterTarget) { RF_R24_Value ++; count ++; } else { break; } // prevent infinite loop cause driver hang. if (loopcnt++ > 100) { DBGPRINT(RT_DEBUG_ERROR, ("RTMPFilterCalibration - can't find a valid value, loopcnt=%d stop calibrating", loopcnt)); break; } // Write RF_R24 to program filter RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value); } if (count > 0) { RF_R24_Value = RF_R24_Value - ((count) ? (1) : (0)); } // Store for future usage if (loopcnt < 100) { if (loop++ == 0) { //BandWidth = 20 MHz pAd->Mlme.CaliBW20RfR24 = (UCHAR)RF_R24_Value; } else { //BandWidth = 40 MHz pAd->Mlme.CaliBW40RfR24 = (UCHAR)RF_R24_Value; break; } } else break; RT30xxWriteRFRegister(pAd, RF_R24, RF_R24_Value); // reset count count = 0; } while(TRUE); // // Set back to initial state // RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R24, 0); RT30xxReadRFRegister(pAd, RF_R22, &value); value &= ~(0x01); RT30xxWriteRFRegister(pAd, RF_R22, value); // // Check BBP R25 RF Calibration at bit 4. Patch from windows driver // RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R25, &BBPValue); if (BBPValue & 0x10) { // // Clear RF calibration // BBPValue &= (~0x10); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R25, BBPValue); DBGPRINT(RT_DEBUG_WARN, ("RTMPFilterCalibration, RF calibration should be done\n")); } // set BBP back to BW20 RTMP_BBP_IO_READ8_BY_REG_ID(pAd, BBP_R4, &BBPValue); BBPValue&= (~0x18); RTMP_BBP_IO_WRITE8_BY_REG_ID(pAd, BBP_R4, BBPValue); DBGPRINT(RT_DEBUG_TRACE, ("RTMPFilterCalibration - CaliBW20RfR24=0x%x, CaliBW40RfR24=0x%x\n", pAd->Mlme.CaliBW20RfR24, pAd->Mlme.CaliBW40RfR24)); }
VOID NICInitRT3090RFRegisters(IN PRTMP_ADAPTER pAd) { INT i; if (IS_RT3090(pAd)) { UINT32 RfReg = 0, data; RT30xxReadRFRegister(pAd, RF_R30, (PUCHAR)&RfReg); RfReg |= 0x80; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RTMPusecDelay(1000); RfReg &= 0x7F; RT30xxWriteRFRegister(pAd, RF_R30, (UCHAR)RfReg); RT30xxWriteRFRegister(pAd, RF_R24, 0x0F); RT30xxWriteRFRegister(pAd, RF_R31, 0x0F); if ((pAd->NicConfig2.field.DACTestBit == 1) && ((pAd->MACVersion & 0xffff) < 0x0211)) { RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x0D000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } else { RTMP_IO_READ32(pAd, LDO_CFG0, &data); data = ((data & 0xE0FFFFFF) | 0x01000000); RTMP_IO_WRITE32(pAd, LDO_CFG0, data); } RTMP_IO_READ32(pAd, GPIO_SWITCH, &data); data &= ~(0x20); RTMP_IO_WRITE32(pAd, GPIO_SWITCH, data); for (i = 0; i < NUM_RF_REG_PARMS; i++) { RT30xxWriteRFRegister(pAd, RT30xx_RFRegTable[i].Register, RT30xx_RFRegTable[i].Value); } RT30xxReadRFRegister(pAd, RF_R06, (PUCHAR)&RfReg); RfReg |= 0x40; RT30xxWriteRFRegister(pAd, RF_R06, (UCHAR)RfReg); RTMPFilterCalibration(pAd); if ((pAd->MACVersion & 0xffff) < 0x0211) RT30xxWriteRFRegister(pAd, RF_R27, 0x3); RTMP_IO_READ32(pAd, OPT_14, &data); data |= 0x01; RTMP_IO_WRITE32(pAd, OPT_14, data); if (pAd->RfIcType == RFIC_3020) AsicSetRxAnt(pAd, pAd->RxAnt.Pair1PrimaryRxAnt); RT30xxLoadRFNormalModeSetup(pAd); } }