/*---------------------------------------------------------------------------*/ int cc2420_init(void) { uint16_t reg; { int s = splhigh(); cc2420_arch_init(); /* Initalize ports and SPI. */ CC2420_DISABLE_FIFOP_INT(); CC2420_FIFOP_INT_INIT(); splx(s); } /* Turn on voltage regulator and reset. */ SET_VREG_ACTIVE(); BUSYWAIT_UNTIL(0, RTIMER_SECOND / 100); SET_RESET_ACTIVE(); BUSYWAIT_UNTIL(0, RTIMER_SECOND / 100); SET_RESET_INACTIVE(); BUSYWAIT_UNTIL(0, RTIMER_SECOND / 100); pan = 0xffff; addr = 0x0000; BUSYWAIT_UNTIL(0, RTIMER_SECOND / 100); powerup(); configure(); flushrx(); process_start(&cc2420_process, NULL); return 1; }
/*---------------------------------------------------------------------------*/ int cc2420_init(void) { uint16_t reg; { int s = splhigh(); cc2420_arch_init(); /* Initalize ports and SPI. */ DISABLE_FIFOP_INT(); FIFOP_INT_INIT(); splx(s); } /* Turn on voltage regulator and reset. */ SET_VREG_ACTIVE(); //clock_delay(250); OK SET_RESET_ACTIVE(); clock_delay(127); SET_RESET_INACTIVE(); //clock_delay(125); OK /* Turn on the crystal oscillator. */ strobe(CC2420_SXOSCON); /* Turn on/off automatic packet acknowledgment and address decoding. */ reg = getreg(CC2420_MDMCTRL0); reg |= 0x40; /* XXX CCA mode 1 */ #if CC2420_CONF_AUTOACK reg |= AUTOACK | ADR_DECODE; #else reg &= ~(AUTOACK | ADR_DECODE); #endif /* CC2420_CONF_AUTOACK */ setreg(CC2420_MDMCTRL0, reg); /* Change default values as recomended in the data sheet, */ /* correlation threshold = 20, RX bandpass filter = 1.3uA. */ setreg(CC2420_MDMCTRL1, CORR_THR(20)); reg = getreg(CC2420_RXCTRL1); reg |= RXBPF_LOCUR; setreg(CC2420_RXCTRL1, reg); /* Set the FIFOP threshold to maximum. */ setreg(CC2420_IOCFG0, FIFOP_THR(127)); /* Turn off "Security enable" (page 32). */ reg = getreg(CC2420_SECCTRL0); reg &= ~RXFIFO_PROTECTION; setreg(CC2420_SECCTRL0, reg); cc2420_set_pan_addr(0xffff, 0x0000, NULL); cc2420_set_channel(26); process_start(&cc2420_process, NULL); return 1; }
void cc2420_init(void) { u16_t reg; { int s = splhigh(); __cc2420_arch_init(); /* Initalize ports and SPI. */ DISABLE_FIFOP_INT(); FIFOP_INT_INIT(); splx(s); } /* Turn on voltage regulator and reset. */ SET_VREG_ACTIVE(); //clock_delay(250); OK SET_RESET_ACTIVE(); clock_delay(127); SET_RESET_INACTIVE(); //clock_delay(125); OK /* Turn on the crystal oscillator. */ cc2420_strobe(CC2420_SXOSCON); /* Turn on automatic packet acknowledgment. */ reg = cc2420_getreg(CC2420_MDMCTRL0); reg |= AUTOACK; cc2420_setreg(CC2420_MDMCTRL0, reg); /* Change default values as recomended in the data sheet, */ /* correlation threshold = 20, RX bandpass filter = 1.3uA. */ cc2420_setreg(CC2420_MDMCTRL1, CORR_THR(20)); reg = cc2420_getreg(CC2420_RXCTRL1); reg |= RXBPF_LOCUR; cc2420_setreg(CC2420_RXCTRL1, reg); /* Set the FIFOP threshold to maximum. */ cc2420_setreg(CC2420_IOCFG0, FIFOP_THR(127)); /* Turn off "Security enable" (page 32). */ reg = cc2420_getreg(CC2420_SECCTRL0); reg &= ~RXFIFO_PROTECTION; cc2420_setreg(CC2420_SECCTRL0, reg); cc2420_set_chan_pan_addr(11, 0xffff, 0x0000, NULL); }
/*---------------------------------------------------------------------------*/ int cc2520_init(void) { { int s = splhigh(); cc2520_arch_init(); /* Initalize ports and SPI. */ CC2520_DISABLE_FIFOP_INT(); CC2520_FIFOP_INT_INIT(); splx(s); } SET_VREG_INACTIVE(); clock_delay(250); /* Turn on voltage regulator and reset. */ SET_VREG_ACTIVE(); clock_delay(250); SET_RESET_ACTIVE(); clock_delay(127); SET_RESET_INACTIVE(); clock_delay(125); /* Turn on the crystal oscillator. */ strobe(CC2520_INS_SXOSCON); clock_delay(125); BUSYWAIT_UNTIL(status() & (BV(CC2520_XOSC16M_STABLE)), RTIMER_SECOND / 100); /* Change default values as recommended in the data sheet, */ /* correlation threshold = 20, RX bandpass filter = 1.3uA.*/ setreg(CC2520_TXCTRL, 0x94); setreg(CC2520_TXPOWER, 0x13); // Output power 1 dBm /* valeurs de TXPOWER 0x03 -> -18 dBm 0x2C -> -7 dBm 0x88 -> -4 dBm 0x81 -> -2 dBm 0x32 -> 0 dBm 0x13 -> 1 dBm 0x32 -> 0 dBm 0x13 -> 1 dBm 0xAB -> 2 dBm 0xF2 -> 3 dBm 0xF7 -> 5 dBm */ setreg(CC2520_CCACTRL0, 0xF8); // CCA treshold -80dBm // Recommended RX settings setreg(CC2520_MDMCTRL0, 0x84); // Controls modem setreg(CC2520_MDMCTRL1, 0x14); // Controls modem setreg(CC2520_RXCTRL, 0x3F); // Adjust currents in RX related analog modules setreg(CC2520_FSCTRL, 0x5A); // Adjust currents in synthesizer. setreg(CC2520_FSCAL1, 0x2B); // Adjust currents in VCO setreg(CC2520_AGCCTRL1, 0x11); // Adjust target value for AGC control loop setreg(CC2520_AGCCTRL2, 0xEB); // Disable external clock setreg(CC2520_EXTCLOCK, 0x00); // Tune ADC performance setreg(CC2520_ADCTEST0, 0x10); setreg(CC2520_ADCTEST1, 0x0E); setreg(CC2520_ADCTEST2, 0x03); /* Set auto CRC on frame. */ #if CC2520_CONF_AUTOACK setreg(CC2520_FRMCTRL0, AUTOCRC | AUTOACK); setreg(CC2520_FRMFILT0, FRAME_MAX_VERSION|FRAME_FILTER_ENABLE); #else /* setreg(CC2520_FRMCTRL0, 0x60); */ setreg(CC2520_FRMCTRL0, AUTOCRC); /* Disable filter on @ (remove if you want to address specific wismote) */ setreg(CC2520_FRMFILT0, 0x00); #endif /* CC2520_CONF_AUTOACK */ /* SET_RXENMASK_ON_TX */ setreg(CC2520_FRMCTRL1, 1); /* Set FIFOP threshold to maximum .*/ setreg(CC2520_FIFOPCTRL, FIFOP_THR(0x7F)); cc2520_set_pan_addr(0xffff, 0x0000, NULL); cc2520_set_channel(26); flushrx(); process_start(&cc2520_process, NULL); return 1; }
/*---------------------------------------------------------------------------*/ int cc2420_init(void) { uint16_t reg; { int s = splhigh(); cc2420_arch_init(); /* Initalize ports and SPI. */ CC2420_DISABLE_FIFOP_INT(); CC2420_FIFOP_INT_INIT(); splx(s); } /* Turn on voltage regulator and reset. */ SET_VREG_ACTIVE(); clock_delay(250); SET_RESET_ACTIVE(); clock_delay(127); SET_RESET_INACTIVE(); clock_delay(125); /* Turn on the crystal oscillator. */ strobe(CC2420_SXOSCON); /* Turn on/off automatic packet acknowledgment and address decoding. */ reg = getreg(CC2420_MDMCTRL0); #if CC2420_CONF_AUTOACK reg |= AUTOACK | ADR_DECODE; #else reg &= ~(AUTOACK | ADR_DECODE); #endif /* CC2420_CONF_AUTOACK */ setreg(CC2420_MDMCTRL0, reg); /* Set transmission turnaround time to the lower setting (8 symbols = 0.128 ms) instead of the default (12 symbols = 0.192 ms). */ /* reg = getreg(CC2420_TXCTRL); reg &= ~(1 << 13); setreg(CC2420_TXCTRL, reg);*/ /* Change default values as recomended in the data sheet, */ /* correlation threshold = 20, RX bandpass filter = 1.3uA. */ setreg(CC2420_MDMCTRL1, CORR_THR(20)); reg = getreg(CC2420_RXCTRL1); reg |= RXBPF_LOCUR; setreg(CC2420_RXCTRL1, reg); /* Set the FIFOP threshold to maximum. */ setreg(CC2420_IOCFG0, FIFOP_THR(127)); /* Turn off "Security enable" (page 32). */ reg = getreg(CC2420_SECCTRL0); reg &= ~RXFIFO_PROTECTION; setreg(CC2420_SECCTRL0, reg); cc2420_set_pan_addr(0xffff, 0x0000, NULL); cc2420_set_channel(CC2420_CONF_CHANNEL); cc2420_set_cca_threshold(CC2420_CONF_CCA_THRESH); flushrx(); process_start(&cc2420_process, NULL); return 1; }
//------------------------------------------------------------------------------------------------------- // void rf_init(RF_RX_INFO *pRRI, uint8_t channel, WORD panId, WORD myAddr) // // DESCRIPTION: // Initializes CC2420 for radio communication via the basic RF library functions. Turns on the // voltage regulator, resets the CC2420, turns on the crystal oscillator, writes all necessary // registers and protocol addresses (for automatic address recognition). Note that the crystal // oscillator will remain on (forever). // // ARGUMENTS: // RF_RX_INFO *pRRI // A pointer the RF_RX_INFO data structure to be used during the first packet reception. // The structure can be switched upon packet reception. // uint8_t channel // The RF channel to be used (11 = 2405 MHz to 26 = 2480 MHz) // WORD panId // The personal area network identification number // WORD myAddr // The 16-bit short address which is used by this node. Must together with the PAN ID form a // unique 32-bit identifier to avoid addressing conflicts. Normally, in a 802.15.4 network, the // short address will be given to associated nodes by the PAN coordinator. //------------------------------------------------------------------------------------------------------- void rf_init(RF_RX_INFO *pRRI, uint8_t channel, uint16_t panId, uint16_t myAddr) { uint8_t n; #ifdef RADIO_PRIORITY_CEILING int8_t v; radio_sem = nrk_sem_create(1,RADIO_PRIORITY_CEILING); if (radio_sem == NULL) nrk_kernel_error_add (NRK_SEMAPHORE_CREATE_ERROR, nrk_get_pid ()); v = nrk_sem_pend (radio_sem); if (v == NRK_ERROR) { nrk_kprintf (PSTR ("CC2420 ERROR: Access to semaphore failed\r\n")); } #endif // Make sure that the voltage regulator is on, and that the reset pin is inactive SET_VREG_ACTIVE(); halWait(1000); SET_RESET_ACTIVE(); halWait(1); SET_RESET_INACTIVE(); halWait(100); // Initialize the FIFOP external interrupt //FIFOP_INT_INIT(); //ENABLE_FIFOP_INT(); // Turn off all interrupts while we're accessing the CC2420 registers DISABLE_GLOBAL_INT(); FASTSPI_STROBE(CC2420_SXOSCON); mdmctrl0=0x02E2; FASTSPI_SETREG(CC2420_MDMCTRL0, mdmctrl0); // Std Preamble, CRC, no auto ack, no hw addr decoding //FASTSPI_SETREG(CC2420_MDMCTRL0, 0x0AF2); // Turn on automatic packet acknowledgment // Turn on hw addre decoding FASTSPI_SETREG(CC2420_MDMCTRL1, 0x0500); // Set the correlation threshold = 20 FASTSPI_SETREG(CC2420_IOCFG0, 0x007F); // Set the FIFOP threshold to maximum FASTSPI_SETREG(CC2420_SECCTRL0, 0x01C4); // Turn off "Security" FASTSPI_SETREG(CC2420_RXCTRL1, 0x1A56); // All default except // reference bias current to RX // bandpass filter is set to 3uA /* // FIXME: remove later for auto ack myAddr=MY_MAC; panId=0x02; FASTSPI_SETREG(CC2420_MDMCTRL0, 0x0AF2); // Turn on automatic packet acknowledgment // FASTSPI_SETREG(CC2420_MDMCTRL0, 0x0AE2); // Turn on automatic packet acknowledgment nrk_spin_wait_us(500); nrk_spin_wait_us(500); FASTSPI_WRITE_RAM_LE(&myAddr, CC2420RAM_SHORTADDR, 2, n); nrk_spin_wait_us(500); FASTSPI_WRITE_RAM_LE(&panId, CC2420RAM_PANID, 2, n); nrk_spin_wait_us(500); printf( "myAddr=%d\r\n",myAddr ); */ nrk_spin_wait_us(500); FASTSPI_WRITE_RAM_LE(&panId, CC2420RAM_PANID, 2, n); nrk_spin_wait_us(500); ENABLE_GLOBAL_INT(); // Set the RF channel halRfSetChannel(channel); // Turn interrupts back on ENABLE_GLOBAL_INT(); // Set the protocol configuration rfSettings.pRxInfo = pRRI; rfSettings.panId = panId; rfSettings.myAddr = myAddr; rfSettings.txSeqNumber = 0; rfSettings.receiveOn = FALSE; // Wait for the crystal oscillator to become stable halRfWaitForCrystalOscillator(); // Write the short address and the PAN ID to the CC2420 RAM (requires that the XOSC is on and stable) // DISABLE_GLOBAL_INT(); // FASTSPI_WRITE_RAM_LE(&myAddr, CC2420RAM_SHORTADDR, 2, n); // FASTSPI_WRITE_RAM_LE(&panId, CC2420RAM_PANID, 2, n); // ENABLE_GLOBAL_INT(); #ifdef RADIO_PRIORITY_CEILING v = nrk_sem_post (radio_sem); if (v == NRK_ERROR) { nrk_kprintf (PSTR ("CC2420 ERROR: Release of semaphore failed\r\n")); _nrk_errno_set (2); } #endif auto_ack_enable=0; security_enable=0; last_pkt_encrypted=0; } // rf_init()