/******************************************************************************
* @brief Main function.
*
* @return Always returns 0.
******************************************************************************/
int main()
{
Xil_ICacheEnable();
Xil_DCacheEnable();
I2C_Init_axi(IIC_BASEADDR, AD7991IICAddr);
unsigned char rxBuffer[2] = {0x00, 0x00};
// Configure AD7991
/*
Use external reference (2V, selected from Jumper JP1)
Read all 3 Channels
4th Channel used as reference
*/
AD7991_Config(0,1,1,1,1,0,0,0);
// Print the value read on one of the channels
AD7991_Print(20,VREF);
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
/***************************************************************************//**
* @brief Main function.
*
* @return Returns 0.
*******************************************************************************/
int main()
{
UINT32 StartCount;
MajorRev = 1;
MinorRev = 1;
RcRev = 1;
DriverEnable = TRUE;
LastEnable = FALSE;
Xil_ICacheEnable();
Xil_DCacheEnable();
#ifdef XPAR_AXI_IIC_0_BASEADDR
HAL_PlatformInit(XPAR_AXI_IIC_0_BASEADDR, /* Perform any required platform init */
XPAR_SCUTIMER_DEVICE_ID, /* including hardware reset to HDMI devices */
XPAR_SCUGIC_SINGLE_DEVICE_ID,
XPAR_SCUTIMER_INTR);
#else
HAL_PlatformInit(XPAR_AXI_IIC_MAIN_BASEADDR, /* Perform any required platform init */
XPAR_SCUTIMER_DEVICE_ID, /* including hardware reset to HDMI devices */
XPAR_SCUGIC_SINGLE_DEVICE_ID,
XPAR_SCUTIMER_INTR);
#endif
Xil_ExceptionEnable();
SetVideoResolution(RESOLUTION_640x480);
InitHdmiAudioPcore();
APP_PrintRevisions(); /* Display S/W and H/W revisions */
DBG_MSG("To change the video resolution press:\r\n");
DBG_MSG(" '0' - 640x480; '1' - 800x600; '2' - 1024x768; '3' - 1280x720 \r\n");
DBG_MSG(" '4' - 1360x768; '5' - 1600x900; '6' - 1920x1080.\r\n");
ADIAPI_TransmitterInit(); /* Initialize ADI repeater software and h/w */
ADIAPI_TransmitterSetPowerMode(REP_POWER_UP);
StartCount = HAL_GetCurrentMsCount();
while(1)
{
if (ATV_GetElapsedMs (StartCount, NULL) >= HDMI_CALL_INTERVAL_MS)
{
StartCount = HAL_GetCurrentMsCount();
if (APP_DriverEnabled())
{
ADIAPI_TransmitterMain();
}
}
APP_ChangeResolution();
}
Xil_DCacheDisable();
Xil_ICacheDisable();
return(0);
}
int main()
{
volatile unsigned int *vram_ptr;
int h,v,i;
volatile int delay_cnt;
init_platform();
Xil_DCacheDisable();//キャッシュの無効化
print("Hello World !!\n\r");
while(1){
for(i=0;i<16;i++){
for(v=0;v<480;v++){//ライン数カウント
//1ラインあたり8192バイトを割り当て
vram_ptr = (unsigned int *)(VRAM_P2_BSASE_ADDR + v*8192);
//水平方向ピクセル数カウント 2ピクセル毎に書き込み
for(h=0;h<720;h++) {
if(h<150)
*vram_ptr = 0xffffff; //白
else if(h<300)
*vram_ptr = 0xff; //赤
else if(h<450)
*vram_ptr = 0xff00; //緑
else if(h<600)
*vram_ptr = 0xff0000; //青
else
*vram_ptr = 0x0; //黒
vram_ptr++;
}
}
for(delay_cnt=0;delay_cnt<2000000;delay_cnt++);
}
while(1);
}
}
int main()
{
int ret = XST_SUCCESS;
u32 n, wdata;
Xil_DCacheDisable();
Xil_ICacheDisable();
/* walking 1 */
for(n = 0; n < 28; n++) {
wdata = 1 << n;
gpio_write(wdata);
gpio_wait();
if (gpio_read(n, wdata) != XST_SUCCESS)
ret = XST_FAILURE;
}
/* walking 0 */
for(n = 0; n < 28; n++) {
wdata = 1 << n;
wdata = ~wdata;
gpio_write(wdata);
gpio_wait();
if (gpio_read(n, wdata) != XST_SUCCESS)
ret = XST_FAILURE;
}
return ret;
}
/***************************************************************************//**
* @brief main
*******************************************************************************/
int main(void)
{
Xil_ICacheEnable();
Xil_DCacheEnable();
gpio_init(GPIO_DEVICE_ID);
gpio_direction(54 + 46, 1);
spi_init(SPI_DEVICE_ID, 1, 0);
adc_init();
dac_init(DATA_SEL_DDS);
ad9361_phy = ad9361_init(&default_init_param);
ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
#ifdef DAC_DMA
dac_init(DATA_SEL_DMA);
#else
dac_init(DATA_SEL_DDS);
#endif
#ifdef CAPTURE_SCRIPT
adc_capture(16384, ADC_DDR_BASEADDR);
while(1);
#endif
get_help(NULL, 0);
while(1)
{
console_get_command(received_cmd);
invalid_cmd = 0;
for(cmd = 0; cmd < cmd_no; cmd++)
{
param_no = 0;
cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
param, ¶m_no);
if(cmd_type == UNKNOWN_CMD)
{
invalid_cmd++;
}
else
{
cmd_list[cmd].function(param, param_no);
}
}
if(invalid_cmd == cmd_no)
{
console_print("Invalid command!\n");
}
}
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
/***************************************************************************//**
* @brief Main function.
*
* @return Returns 0.
*******************************************************************************/
int main()
{
UINT32 StartCount;
MajorRev = 1;
MinorRev = 1;
RcRev = 1;
DriverEnable = TRUE;
LastEnable = FALSE;
Xil_ICacheEnable();
Xil_DCacheEnable();
HAL_PlatformInit(XPAR_AXI_IIC_0_BASEADDR, /* Perform any required platform init */
XPAR_SCUTIMER_DEVICE_ID, /* including hardware reset to HDMI devices */
XPAR_SCUGIC_SINGLE_DEVICE_ID,
XPAR_SCUTIMER_INTR);
Xil_ExceptionEnable();
/* Set the default values for 1080P 60Hz */
CLKGEN_SetRate(148500000, 200000000);
InitHdmiVideoPcore(1920,
1080,
280,
45,
44,
5,
88,
4);
InitHdmiAudioPcore();
APP_PrintRevisions(); /* Display S/W and H/W revisions */
ADIAPI_TransmitterInit(); /* Initialize ADI repeater software and h/w */
ADIAPI_TransmitterSetPowerMode(REP_POWER_UP);
StartCount = HAL_GetCurrentMsCount();
while(1)
{
if (ATV_GetElapsedMs (StartCount, NULL) >= HDMI_CALL_INTERVAL_MS)
{
StartCount = HAL_GetCurrentMsCount();
if (APP_DriverEnabled())
{
ADIAPI_TransmitterMain();
}
}
}
Xil_DCacheDisable();
Xil_ICacheDisable();
return(0);
}
/***************************************************************************//**
* @brief Main function.
*
* @return 0.
*******************************************************************************/
int main(){
uint32_t mode;
Xil_ICacheEnable();
Xil_DCacheEnable();
/* AD9467 Setup. */
ad9467_setup(SPI_DEVICE_ID, 0);
/* AD9517 Setup. */
ad9517_setup(SPI_DEVICE_ID, 1); // Initialize device.
ad9517_power_mode(3, 0); // Set channel 3 for normal operation
ad9517_frequency(3, 250000000); // Set the channel 3 frequency to 250Mhz
ad9517_update(); // Update registers
/* Read the device ID for AD9467 and AD9517. */
xil_printf("\n\r********************************************************************\r\n");
xil_printf(" ADI AD9467-FMC-EBZ Reference Design\n\r");
xil_printf(" AD9467 CHIP ID: 0x%02x\n\r", ad9467_read(AD9467_REG_CHIP_ID));
xil_printf(" AD9467 CHIP GRADE: 0x%02x\n\r", ad9467_read(AD9467_REG_CHIP_GRADE));
xil_printf(" AD9517 CHIP ID: 0x%02x", ad9517_read(AD9517_REG_PART_ID));
xil_printf("\n\r********************************************************************\r\n");
/* AD9467 test. */
adc_setup(0);
for (mode = MIDSCALE; mode <= ONE_ZERO_TOGGLE; mode++) // Data pattern checks
{
adc_test(mode, OFFSET_BINARY); // Data format is offset binary
adc_test(mode, TWOS_COMPLEMENT); // Data format is twos complement
}
xil_printf("Testing done.\n\r");
/* AD9467 Setup for data acquisition */
ad9467_output_invert(0); // Output invert Off
ad9467_transfer(); // Synchronously update registers
ad9467_output_format(0); // Offset binary
ad9467_transfer(); // Synchronously update registers
ad9467_reset_PN9(0); // Clear PN9 bit
ad9467_transfer(); // Synchronously update registers
ad9467_reset_PN23(0); // Clear PN23 bit
ad9467_transfer(); // Synchronously update registers
ad9467_test_mode(0); // Test mode Off
ad9467_transfer(); // Synchronously update registers
xil_printf("Start capturing data...\n\r");
while(1)
{
adc_capture(1024, DDR_BASEADDR);
}
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
void cleanup_platform()
{
#if __MICROBLAZE__ || __PPC__
disable_caches();
#endif
#ifdef __arm__
Xil_ICacheDisable();
Xil_DCacheDisable();
#endif
}
//------------------------------------------------------------------------------
int main()
{
Xil_ICacheEnable();
Xil_DCacheEnable();
while(1){ main_loop(); }
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
void
disable_caches()
{
#ifdef __MICROBLAZE__
#ifdef XPAR_MICROBLAZE_USE_DCACHE
Xil_DCacheDisable();
#endif
#ifdef XPAR_MICROBLAZE_USE_ICACHE
Xil_ICacheDisable();
#endif
#endif
}
int main()
{
int i = 0;
int audioSize = 0;
int sendValDac = 0;
Xil_DCacheFlush();
Xil_DCacheDisable();
xil_printf("PmodAMP3 Demonstration Project\n\r");
audioSize = (sizeof(audio_data) / sizeof(u32));
xil_printf("Preparing Audio Data...");
for(i = 0; i < audioSize; i++)
{
sendValDac = audio_data[i];
Xil_Out32((PMOD_DATA_BASEADDR + (i * 0x04)), sendValDac);
}
xil_printf("Done!\n\r");
xil_printf("Programming VDMA Core...");
Xil_Out32((VDMA_BASEADDR + 0x000), 0x00000000);
Xil_Out32((VDMA_BASEADDR + 0x000), 0x00000003); // enable circular mode
while((Xil_In32(VDMA_BASEADDR + 0x04) & 0x01) != 0x00);
Xil_Out32((VDMA_BASEADDR + 0x018), 0x01); // frm store
Xil_Out32((VDMA_BASEADDR + 0x05c), PMOD_DATA_BASEADDR); // start address
Xil_Out32((VDMA_BASEADDR + 0x058), 63928); // h offset bytes
Xil_Out32((VDMA_BASEADDR + 0x054), 63928); // h size bytes
Xil_Out32((VDMA_BASEADDR + 0x050), 12); // v size
xil_printf("Done!\n\r");
xil_printf("Enabling SSM2518 Core...");
Xil_Out32(CF_BASEADDR + 0x4040, 0x01);
Xil_Out32(CF_BASEADDR + 0x4044, 0x01);
xil_printf("Done!\n\r");
while(1)
{
}
return 0;
}
int main()
{
static XIntc intc;
Xil_ICacheEnable();
Xil_DCacheEnable();
print("---Entering main---\n\r");
//XIntc_DeviceInterruptHandler(XPAR_INTC_0_DEVICE_ID);
//print (XPAR_INTC_0_DEVICE_ID);
{
int status;
print("\r\n Running IntcSelfTestExample() for axi_intc_0...\r\n");
status = IntcSelfTestExample(XPAR_AXI_INTC_0_DEVICE_ID);
if (status == 0) {
print("IntcSelfTestExample PASSED\r\n");
}
else {
print("IntcSelfTestExample FAILED\r\n");
}
}
{
int Status;
Status = IntcInterruptSetup(&intc, XPAR_AXI_INTC_0_DEVICE_ID);
if (Status == 0) {
print("Intc Interrupt Setup PASSED\r\n");
}
else {
print("Intc Interrupt Setup FAILED\r\n");
}
}
/*
* Peripheral SelfTest will not be run for axi_uartlite_0
* because it has been selected as the STDOUT device
*/
print("---Exiting main---\n\r");
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
int main (void) {
/*
* Enable and initialize cache
*/
#if XPAR_MICROBLAZE_0_USE_ICACHE
Xil_ICacheInvalidate();
Xil_ICacheEnable();
#endif
#if XPAR_MICROBLAZE_0_USE_DCACHE
Xil_DCacheInvalidate();
Xil_DCacheEnable();
#endif
print("-- Entering main() --\r\n");
/*
* MemoryTest routine will not be run for the memory at
* 0x84c00000 (FLASH_2Mx16)
* because it is a read-only memory
*/
/*
* MemoryTest routine will not be run for the memory at
* 0x00000000 (dlmb_cntlr)
* because it is being used to hold a part of this application program
*/
/*
* Disable cache and reinitialize it so that other
* applications can be run with no problems
*/
#if XPAR_MICROBLAZE_0_USE_DCACHE
Xil_DCacheDisable();
Xil_DCacheInvalidate();
#endif
#if XPAR_MICROBLAZE_0_USE_ICACHE
Xil_ICacheDisable();
Xil_ICacheInvalidate();
#endif
print("-- Exiting main() --\r\n");
return 0;
}
/***************************************************************************//**
* @brief Main function.
*
* @return 0.
*******************************************************************************/
int main(){
u32 mode;
Xil_ICacheEnable();
Xil_DCacheEnable();
/* AD9467 Setup. */
ad9467_setup(XPAR_AXI_SPI_0_BASEADDR, 1);
/* AD9517 Setup. */
ad9517_setup(XPAR_AXI_SPI_0_BASEADDR, 2); // Initialize device.
ad9517_power_mode(3, 0); // Set channel 3 for normal operation
ad9517_frequency(3, 250000000); // Set the channel 3 frequency to 250Mhz
ad9517_update(); // Update registers
/* Read the device ID for AD9467 and AD9517. */
xil_printf("AD9467[REG_CHIP_ID]: %02x\n\r",
ad9467_read(AD9467_REG_CHIP_ID));
xil_printf("AD9467[REG_CHIP_GRADE]: %02x\n\r",
ad9467_read(AD9467_REG_CHIP_GRADE));
xil_printf("AD9517[REG_PART_ID]: %02x\n\r",
ad9517_read(AD9517_REG_PART_ID));
/* AD9467 test. */
adc_setup(0);
for (mode = 0x01; mode <= 0x07; mode++) // Data pattern checks
{
adc_test(mode, 0x0); // Data format is offset binary
adc_test(mode, 0x1); // Data format is twos complement
}
ad9467_output_invert(0); // Output invert Off
ad9467_output_format(0); // Offset binary
ad9467_reset_PN9(0); // Clear PN9 bit
ad9467_reset_PN23(0); // Clear PN23 bit
ad9467_test_mode(0); // Test mode Off
ad9467_transfer(); // Synchronously update registers
xil_printf("done\n\r");
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
void XFsbl_EccInitialize(u32 Address, u32 Length)
{
u32 Index=0U;
/* Disable cache to ensure proper ECC initialization */
Xil_DCacheDisable();
while (Index<Length)
{
XFsbl_Out32(Address+Index, 1U) ;
Index += 4U;
}
Xil_DCacheEnable();
XFsbl_Printf(DEBUG_INFO,
"Address 0x%0lx, Length %0lx, ECC initialized \r\n",
Address, Length);
return ;
}
/**
* @brief Disable MPU for Cortex R5 processors. This function invalidates I
* cache and flush the D Caches, and then disabes the MPU.
*
* @param None.
*
* @return None.
*
******************************************************************************/
void Xil_DisableMPU(void)
{
u32 CtrlReg, Reg;
s32 DCacheStatus=0, ICacheStatus=0;
/* enable caches only if they are disabled */
#if defined (__GNUC__)
CtrlReg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL,CtrlReg);
#endif
if ((CtrlReg & XREG_CP15_CONTROL_C_BIT) != 0x00000000U) {
DCacheStatus=1;
}
if ((CtrlReg & XREG_CP15_CONTROL_I_BIT) != 0x00000000U) {
ICacheStatus=1;
}
if(DCacheStatus != 0) {
Xil_DCacheDisable();
}
if(ICacheStatus != 0){
Xil_ICacheDisable();
}
mtcp(XREG_CP15_INVAL_BRANCH_ARRAY, 0);
#if defined (__GNUC__)
Reg = mfcp(XREG_CP15_SYS_CONTROL);
#elif defined (__ICCARM__)
mfcp(XREG_CP15_SYS_CONTROL,Reg);
#endif
Reg &= ~(0x00000001U);
dsb();
mtcp(XREG_CP15_SYS_CONTROL, Reg);
isb();
/* enable caches only if they are disabled in routine*/
if(DCacheStatus != 0) {
Xil_DCacheEnable();
}
if(ICacheStatus != 0) {
Xil_ICacheEnable();
}
}
int main() {
Xil_DCacheDisable();
int i, mismatch = 0;
volatile unsigned int src_data[256], dst_data[256];
for(i = 0; i < 256; i++) src_data[i] = i;
unsigned int *baseaddr = (unsigned int*)0x43c00000;
xil_printf("\r\n");
baseaddr[1] = (unsigned int)src_data;
baseaddr[2] = (unsigned int)dst_data;
baseaddr[0] = 0xFFFFFFFF;
xil_printf("memcpy start, src=%08x dest=%08x\n\r", src_data, dst_data);
while(baseaddr[0] != 0) ;
xil_printf("memcpy done\n\r");
for(i = 0; i < 256; i++){
xil_printf("src_data[%d] = %d, ", i, src_data[i]);
xil_printf("dst_data[%d] = %d\n\r", i, dst_data[i]);
if(src_data[i] != dst_data[i]) mismatch = 1;
}
(mismatch==0)? xil_printf("memcpy success!\n\r") : xil_printf("memcpy fail\n\r"); return 0;
}
/**
* FSBL exit function before the assembly code
*
* @param HandoffAddress is handoff address for the FSBL running cpu
*
* @param Flags is to determine whether to handoff to applicatio or
* to be in wfe state
*
* @return None
*
*
*****************************************************************************/
void XFsbl_HandoffExit(u64 HandoffAddress, u32 Flags)
{
/**
* Flush the L1 data cache and L2 cache, Disable Data Cache
*/
Xil_DCacheDisable();
XFsbl_Printf(DEBUG_GENERAL,"Exit from FSBL \n\r");
/**
* Exit to handoff address
* PTRSIZE is used since handoff is in same running cpu
* and address is of PTRSIZE
*/
XFsbl_Exit((PTRSIZE) HandoffAddress, Flags);
/**
* should not reach here
*/
return ;
}
int main()
{
Xil_ICacheEnable();
Xil_DCacheEnable();
print("---Entering main---\n\r");
{
printf("LEDs and switches\r\n");
XGpio_Initialize(&inGpio,XPAR_AXI_GPIO_1_DEVICE_ID);
XGpio_Initialize(&outGpio,XPAR_AXI_GPIO_0_DEVICE_ID);
XGpio_DiscreteWrite(&outGpio,1,0); // leds off
}
{
printf("Deca SPI test\r\n");
if (0 != openspi()){
printf("Init SPI failed\r\n");
} else {
// get switches
int sw = XGpio_DiscreteRead(&inGpio,1);
XGpio_DiscreteWrite(&outGpio,1,sw);
//printf("LED: %x\r\n",XGpio_DiscreteRead(&outGpio,1));
switch (sw & 0x7){
case 1:
printf("SS TWR INIT\r\n");
ssTwrInit();
break;
case 2:
printf("SS TWR RESP\r\n");
ssTwrResp();
break;
case 3:
printf("Simple TX\r\n");
simpleTx();
break;
case 4:
printf("Simple RX\r\n");
simpleRx();
break;
case 5:
printf("TX Wait\r\n");
txWait();
break;
case 6:
printf("RX Wait\r\n");
rxWait();
break;
default:
/* Reset and initialise DW1000. */
reset_DW1000();
dwt_initialise(DWT_LOADNONE);
/* Configure DW1000. */
printf("UBW configuration sequence\r\n");
dwt_configure(&config);
dwt_configuretxrf(&txconfig);
/* Activate continuous wave mode. */
dwt_configcwmode(config.chan);
/* Wait for the wanted duration of the continuous wave transmission. */
printf("Waiting for UBW continuous wave transmission delay: %ds\r\n",CONT_WAVE_DURATION_MS/1000);
deca_sleep(CONT_WAVE_DURATION_MS);
/* Software reset of the DW1000 to deactivate continuous wave mode and go back to default state. Initialisation and configuration should be run
* again if one wants to get the DW1000 back to normal operation. */
dwt_softreset();
}
printf("Deca test done. press any key\r\n");
getchar();
}
}
print("---Exiting main---\n\r");
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
void platform_cache_disable() {
Xil_DCacheDisable();
Xil_ICacheDisable();
}
/* Program main loop. */
int main()
{
int32_t ret;
int32_t mode = 0;
float retGain;
uint64_t retFreqRx;
uint64_t retFreqTx;
int32_t fmcSel;
int32_t i;
int32_t valArray[17];
XCOMM_Version boardVersion;
XCOMM_DefaultInit defInit = {FMC_LPC, //fmcPort
XILINX_ML605, //carrierBoard
100000000, //adcSamplingRate
122880000, //dacSamplingRate
10000, //rxGain1000
2400000000ull, //rxFrequency
2400000000ull};//txFrequency
Xil_ICacheEnable();
Xil_DCacheEnable();
xil_printf("Running XCOMM Test Program\n\r");
if(defInit.carrierBoard == XILINX_ZC702)
{
fmcSel = (defInit.fmcPort == FMC_LPC ? IICSEL_B0LPC_PS7 : IICSEL_B1HPC_PS7);
}
else
{
if(defInit.carrierBoard == XILINX_ZC706)
{
fmcSel = (defInit.fmcPort == FMC_LPC ? IICSEL_B0LPC_PS7_ZC706 :
IICSEL_B1HPC_PS7_ZC706);
}
else
{
fmcSel = (defInit.fmcPort == FMC_LPC ? IICSEL_B0LPC_AXI : IICSEL_B1HPC_AXI);
}
}
xil_printf("\n\rInitializing XCOMM I2C...\n\r");
ret = XCOMM_InitI2C(&defInit);
if(ret < 0)
{
xil_printf("XCOMM Init I2C Failed!\n\r");
return 0;
}
else
{
xil_printf("XCOMM Init I2C OK!\n\r");
}
xil_printf("\n\rGetting XCOMM Revision...\n\r");
boardVersion = XCOMM_GetBoardVersion(XCOMM_ReadMode_FromHW);
if(boardVersion.error == -1)
{
xil_printf("\n\rGetting XCOMM Revision Failed!\n\r");
}
else
{
xil_printf("Board Version: %s\n\r", boardVersion.value);
}
xil_printf("\n\rInitializing XCOMM Components...\n\r");
ret = XCOMM_Init(&defInit);
if(ret < 0)
{
xil_printf("XCOMM Init Failed!\n\r");
return 0;
}
else
{
xil_printf("XCOMM Init OK!\n\r");
}
xil_printf("\n\rInitializing the Rx path...\n\r");
ret = XCOMM_InitRx(&defInit);
if(ret < 0)
{
xil_printf("XCOMM Rx Init Failed!\n\r");
return 0;
}
else
{
xil_printf("XCOMM Rx Init OK!\n\r");
}
xil_printf("\n\rInitializing the Tx path...\n\r");
ret = XCOMM_InitTx(&defInit);
if(ret < 0)
{
xil_printf("XCOMM Tx Init Failed!\n\r");
return 0;
}
else
{
xil_printf("XCOMM Tx Init OK!\n\r");
}
xil_printf("\n\rADC sampling rate [Hz]: ");
ret = XCOMM_GetAdcSamplingRate(XCOMM_ReadMode_FromHW);
xil_printf("%d \n\r", ret);
xil_printf("\n\rDAC sampling rate [Hz]: ");
ret = XCOMM_GetDacSamplingRate(XCOMM_ReadMode_FromHW);
xil_printf("%d \n\r", ret);
xil_printf("\n\rDAC available interpolation frequencies [Hz]: ");
XCOMM_GetDacAvailableInterpolationFreq(valArray);
i = 0;
while((valArray[i] != 0) && (i < 5))
{
xil_printf("%d ", valArray[i]);
i++;
}
xil_printf("\n\r");
xil_printf("\n\rDAC available center shift frequencies [Hz]: ");
XCOMM_GetDacAvailableCenterShiftFreq(valArray);
i = 0;
while((valArray[i] != -1) && (i < 17))
{
xil_printf("%d ", valArray[i]);
i++;
}
xil_printf("\n\r");
xil_printf("\n\rTesting the ADC communication... \n\r");
XCOMM_SetAdcTestMode(0x01, XCOMM_AdcChannel_All);
adc_capture(fmcSel, 1024, DDR_BASEADDR);
for (mode = 0x1; mode <= 0x7; mode++)
{
XCOMM_SetAdcTestMode(mode, XCOMM_AdcChannel_All);
adc_test(fmcSel, mode, 0x1);
}
xil_printf("ADC test complete.\n\r");
xil_printf("\n\rTesting the DAC communication... \n\r");
dac_test(fmcSel);
xil_printf("DAC test complete.\n\r");
xil_printf("\n\rSetting the VGA gain to: %d.%d dB\n\r", (int)defInit.rxGain1000/1000, (int)((defInit.rxGain1000 - (int)(defInit.rxGain1000/1000)*1000)));
retGain = (float)XCOMM_SetRxGain(defInit.rxGain1000) / 1000.0f;
xil_printf("Actual set VGA gain: %d.%d dB\n\r", (int)retGain, (int)((retGain - (int)retGain) * 1000));
xil_printf("\n\rSetting the Rx frequency to: %lld%06lld\n\r", defInit.rxFrequency/(uint64_t)1e6, defInit.rxFrequency%(uint64_t)1e6);
retFreqRx = XCOMM_SetRxFrequency(defInit.rxFrequency);
xil_printf("Actual set Rx frequency: %lld%06lld\n\r", retFreqRx/(uint64_t)1e6, retFreqRx%(uint64_t)1e6);
xil_printf("\n\rSetting the Tx frequency to: %lld%06lld\n\r", defInit.txFrequency/(uint64_t)1e6, defInit.txFrequency%(uint64_t)1e6);
retFreqTx = XCOMM_SetTxFrequency(defInit.txFrequency);
xil_printf("Actual set Tx frequency: %lld%06lld\n\r", retFreqTx/(uint64_t)1e6, retFreqTx%(uint64_t)1e6);
xil_printf("\n\rSetting up the DDS... \n\r");
dds_setup(fmcSel, 5, 5);
xil_printf("DDS setup complete.\n\r");
xil_printf("\n\rReading data from air... \n\r");
XCOMM_SetAdcTestMode(XCOMM_AdcTestMode_Off, XCOMM_AdcChannel_All);
while(1)
{
adc_capture(fmcSel, 1024, DDR_BASEADDR);
}
xil_printf("Read data from air complete. \n\r");
xil_printf("\n\rFinished XCOMM Test Program\n\r");
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
int main()
{
static XIntc intc;
static XSpi axi_spi_0_Spi;
static XTmrCtr axi_timer_0_Timer;
Xil_ICacheEnable();
Xil_DCacheEnable();
print("---Entering main---\n\r");
{
int status;
print("\r\n Running IntcSelfTestExample() for microblaze_0_intc...\r\n");
status = IntcSelfTestExample(XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
if (status == 0) {
print("IntcSelfTestExample PASSED\r\n");
}
else {
print("IntcSelfTestExample FAILED\r\n");
}
}
{
int Status;
Status = IntcInterruptSetup(&intc, XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
if (Status == 0) {
print("Intc Interrupt Setup PASSED\r\n");
}
else {
print("Intc Interrupt Setup FAILED\r\n");
}
}
{
XStatus status;
print("\r\n Runnning SpiSelfTestExample() for axi_spi_0...\r\n");
status = SpiSelfTestExample(XPAR_AXI_SPI_0_DEVICE_ID);
if (status == 0) {
print("SpiSelfTestExample PASSED\r\n");
}
else {
print("SpiSelfTestExample FAILED\r\n");
}
}
{
XStatus Status;
print("\r\n Running Interrupt Test for axi_spi_0...\r\n");
Status = SpiIntrExample(&intc, &axi_spi_0_Spi, \
XPAR_AXI_SPI_0_DEVICE_ID, \
XPAR_MICROBLAZE_0_INTC_AXI_SPI_0_IP2INTC_IRPT_INTR);
if (Status == 0) {
print("Spi Interrupt Test PASSED\r\n");
}
else {
print("Spi Interrupt Test FAILED\r\n");
}
}
{
int status;
print("\r\n Running TmrCtrSelfTestExample() for axi_timer_0...\r\n");
status = TmrCtrSelfTestExample(XPAR_AXI_TIMER_0_DEVICE_ID, 0x0);
if (status == 0) {
print("TmrCtrSelfTestExample PASSED\r\n");
}
else {
print("TmrCtrSelfTestExample FAILED\r\n");
}
}
{
int Status;
print("\r\n Running Interrupt Test for axi_timer_0...\r\n");
Status = TmrCtrIntrExample(&intc, &axi_timer_0_Timer, \
XPAR_AXI_TIMER_0_DEVICE_ID, \
XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR, 0);
if (Status == 0) {
print("Timer Interrupt Test PASSED\r\n");
}
else {
print("Timer Interrupt Test FAILED\r\n");
}
}
{
int status;
print("\r\nRunning UartLiteSelfTestExample() for be2fe_console0...\r\n");
status = UartLiteSelfTestExample(XPAR_BE2FE_CONSOLE0_DEVICE_ID);
if (status == 0) {
print("UartLiteSelfTestExample PASSED\r\n");
}
else {
print("UartLiteSelfTestExample FAILED\r\n");
}
}
{
int status;
print("\r\nRunning UartLiteSelfTestExample() for be2fe_console1...\r\n");
status = UartLiteSelfTestExample(XPAR_BE2FE_CONSOLE1_DEVICE_ID);
if (status == 0) {
print("UartLiteSelfTestExample PASSED\r\n");
}
else {
print("UartLiteSelfTestExample FAILED\r\n");
}
}
/*
* Peripheral SelfTest will not be run for debug_module
* because it has been selected as the STDOUT device
*/
print("---Exiting main---\n\r");
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
int main(void)
{
XIntc intc;
XTmrCtr tmrctr;
int Status;
Xil_ICacheEnable();
Xil_DCacheEnable();
// Initialize the timer counter so that it's ready to use,
// specify the device ID that is generated in xparameters.h
Status = XTmrCtr_Initialize(&tmrctr, XPAR_TMRCTR_0_DEVICE_ID);
if (Status != XST_SUCCESS) {
return Status;
}
// Initialize the interrupt controller driver so that
// it's ready to use, specify the device ID that is generated in
// xparameters.h
Status = XIntc_Initialize(&intc, XPAR_INTC_0_DEVICE_ID);
if (Status != XST_SUCCESS) {
return Status;
}
// Connect a device driver handler that will be called when an interrupt
// for the device occurs, the device driver handler performs the specific
// interrupt processing for the device
Status = XIntc_Connect(&intc, XPAR_INTC_0_TMRCTR_0_VEC_ID,
XTmrCtr_InterruptHandler, &tmrctr);
if (Status != XST_SUCCESS) {
return Status;
}
// Enable the interrupt for the timer counter
XIntc_Enable(&intc, XPAR_INTC_0_TMRCTR_0_VEC_ID );
// Start the interrupt controller such that interrupts are enabled for
// all devices that cause interrupts, specific real mode so that
// the timer counter can cause interrupts thru the interrupt controller.
Status = XIntc_Start(&intc, XIN_REAL_MODE);
if (Status != XST_SUCCESS) {
return Status;
}
// Initialize the exception table.
Xil_ExceptionInit();
// Register the interrupt controller handler with the exception table.
Xil_ExceptionRegisterHandler(XIL_EXCEPTION_ID_INT,
(Xil_ExceptionHandler)XIntc_InterruptHandler, &intc);
// Enable non-critical exceptions.
Xil_ExceptionEnable();
// Setup the handler for the timer counter that will be called from the
// interrupt context when the timer expires, specify a pointer to the
// timer counter driver instance as the callback reference so the handler
// is able to access the instance data
XTmrCtr_SetHandler(&tmrctr, TimerCounterHandler, &tmrctr);
// Enable the interrupt of the timer counter so interrupts will occur
// and use auto reload mode such that the timer counter will reload
// itself automatically and continue repeatedly, without this option
// it would expire once only
XTmrCtr_SetOptions(&tmrctr, 0, XTC_INT_MODE_OPTION | XTC_AUTO_RELOAD_OPTION
| XTC_DOWN_COUNT_OPTION);
// Set a reset value for the timer counter such that it will expire
// when it rolls under to 0, the reset value is loaded
// into the timer counter when it is started
XTmrCtr_SetResetValue(&tmrctr, 0, XPAR_AXI_TIMER_0_CLOCK_FREQ_HZ-1);
// Start the timer counter
XTmrCtr_Start(&tmrctr, 0);
while (1) {
}
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
int main()
{
static XIntc intc;
static XGpio dip_switches_4bits_Gpio;
static XTmrCtr axi_timer_0_Timer;
Xil_ICacheEnable();
Xil_DCacheEnable();
print("---Entering main---\n\r");
{
int status;
print("\r\n Running IntcSelfTestExample() for microblaze_0_intc...\r\n");
status = IntcSelfTestExample(XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
if (status == 0) {
print("IntcSelfTestExample PASSED\r\n");
}
else {
print("IntcSelfTestExample FAILED\r\n");
}
}
{
int Status;
Status = IntcInterruptSetup(&intc, XPAR_MICROBLAZE_0_INTC_DEVICE_ID);
if (Status == 0) {
print("Intc Interrupt Setup PASSED\r\n");
}
else {
print("Intc Interrupt Setup FAILED\r\n");
}
}
{
int status;
print("\r\nRunning UartLiteSelfTestExample() for debug_module...\r\n");
status = UartLiteSelfTestExample(XPAR_DEBUG_MODULE_DEVICE_ID);
if (status == 0) {
print("UartLiteSelfTestExample PASSED\r\n");
}
else {
print("UartLiteSelfTestExample FAILED\r\n");
}
}
/*
* Peripheral SelfTest will not be run for usb_uart
* because it has been selected as the STDOUT device
*/
{
u32 status;
print("\r\nRunning GpioInputExample() for dip_switches_4bits...\r\n");
u32 DataRead;
status = GpioInputExample(XPAR_DIP_SWITCHES_4BITS_DEVICE_ID, &DataRead);
if (status == 0) {
xil_printf("GpioInputExample PASSED. Read data:0x%X\r\n", DataRead);
}
else {
print("GpioInputExample FAILED.\r\n");
}
}
{
int Status;
u32 DataRead;
print(" Press button to Generate Interrupt\r\n");
Status = GpioIntrExample(&intc, &dip_switches_4bits_Gpio, \
XPAR_DIP_SWITCHES_4BITS_DEVICE_ID, \
XPAR_MICROBLAZE_0_INTC_DIP_SWITCHES_4BITS_IP2INTC_IRPT_INTR, \
GPIO_CHANNEL1, &DataRead);
if (Status == 0 ){
if(DataRead == 0)
print("No button pressed. \r\n");
else
print("Gpio Interrupt Test PASSED. \r\n");
}
else {
print("Gpio Interrupt Test FAILED.\r\n");
}
}
{
u32 status;
print("\r\nRunning GpioOutputExample() for leds_4bits...\r\n");
status = GpioOutputExample(XPAR_LEDS_4BITS_DEVICE_ID,4);
if (status == 0) {
print("GpioOutputExample PASSED.\r\n");
}
else {
print("GpioOutputExample FAILED.\r\n");
}
}
{
int status;
print("\r\nRunning EmacLitePolledExample() for ethernet_mac...\r\n");
status = EmacLitePolledExample(XPAR_ETHERNET_MAC_DEVICE_ID);
if (status == 0) {
print("EmacLite Polled Example PASSED\r\n");
}
else {
print("EmacLite Polled Example FAILED\r\n");
}
}
{
int status;
print("\r\n Running TmrCtrSelfTestExample() for axi_timer_0...\r\n");
status = TmrCtrSelfTestExample(XPAR_AXI_TIMER_0_DEVICE_ID, 0x0);
if (status == 0) {
print("TmrCtrSelfTestExample PASSED\r\n");
}
else {
print("TmrCtrSelfTestExample FAILED\r\n");
}
}
{
int Status;
print("\r\n Running Interrupt Test for axi_timer_0...\r\n");
Status = TmrCtrIntrExample(&intc, &axi_timer_0_Timer, \
XPAR_AXI_TIMER_0_DEVICE_ID, \
XPAR_MICROBLAZE_0_INTC_AXI_TIMER_0_INTERRUPT_INTR, 0);
if (Status == 0) {
print("Timer Interrupt Test PASSED\r\n");
}
else {
print("Timer Interrupt Test FAILED\r\n");
}
}
{
XStatus status;
print("\r\n Runnning SpiSelfTestExample() for spi_flash...\r\n");
status = SpiSelfTestExample(XPAR_SPI_FLASH_DEVICE_ID);
if (status == 0) {
print("SpiSelfTestExample PASSED\r\n");
}
else {
print("SpiSelfTestExample FAILED\r\n");
}
}
print("---Exiting main---\n\r");
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
void cleanup_platform()
{
Xil_ICacheDisable();
Xil_DCacheDisable();
return;
}
int main()
{
static XIntc intc;
Xil_ICacheEnable();
Xil_DCacheEnable();
xil_printf("Testing UART output.\r\n");
// Camera DMA Configuration
XAxiDma_Config *dmaconf = XAxiDma_LookupConfig(XPAR_AXI_DMA_0_DEVICE_ID);
XAxiDma dma;
XAxiDma_CfgInitialize(&dma, dmaconf);
XAxiDma_Resume(&dma);
XAxiDma_Reset(&dma);
while(!XAxiDma_ResetIsDone(&dma));
// Initialize Video
InitVideo();
// Example camera DMA read
// Note - transfer MUST be 4096B
// Data format is 20-bit pixel number (stored in a 32 bit integer) followed by 16-bit RGB values
// This will not work until you implement camera_stream.v.
// (or at least, until you have it barely working)
//int resdde = XAxiDma_SimpleTransfer(&dma, (u32)((unsigned char*)&camera), 4096, XAXIDMA_DEVICE_TO_DMA);
//while(XAxiDma_Busy(&dma,XAXIDMA_DEVICE_TO_DMA));
int Status;
XEmacLite *EmacLiteInstPtr = &EmacLiteInstance;
u32 PhyAddress = 0;
RecvFrameLength = 0;
XEmacLite_Config *ConfigPtr;
/*
* Initialize the EmacLite device.
*/
ConfigPtr = XEmacLite_LookupConfig(XPAR_ETHERNET_LITE_DEVICE_ID);
if (ConfigPtr == NULL) {
return XST_FAILURE;
}
Status = XEmacLite_CfgInitialize(EmacLiteInstPtr,
ConfigPtr,
ConfigPtr->BaseAddress);
if (Status != XST_SUCCESS) {
return XST_FAILURE;
}
/*
* Set the MAC address.
*/
XEmacLite_SetMacAddress(EmacLiteInstPtr, LocalAddress);
/*
* Empty any existing receive frames.
*/
XEmacLite_FlushReceive(EmacLiteInstPtr);
/*
* Check if there is a TX buffer available, if there isn't it is an
* error.
*/
if (XEmacLite_TxBufferAvailable(EmacLiteInstPtr) != TRUE) {
return XST_FAILURE;
}
/*
* Reset the receive frame length to zero.
*/
RecvFrameLength = 0;
// Example program that sends packets and changes the color of an on-screen box upon receiving a packet.
unsigned char c = 0;
unsigned char r=0xFF, g=0x0, b=0x0;
while(1) {
c++;
if(XEmacLite_IsTxDone(ConfigPtr->BaseAddress)) {
Status = EmacLiteSendFrame(EmacLiteInstPtr, EMACLITE_TEST_FRAME_SIZE);
if (Status != XST_SUCCESS) {
if (XEmacLite_IsMdioConfigured(EmacLiteInstPtr)) {
return XST_FAILURE;
}
}
}
else {
RecvFrameLength = XEmacLite_Recv(EmacLiteInstPtr, (u8 *)RxFrame);
if (RecvFrameLength > 0) {
xil_printf("Received a packet!\r\n");
unsigned char oldr = r;
r=g;
g=b;
b=oldr;
}
// Example of writing data to the screen
int x, y;
for (x = 0; x < 20; x++)
for (y = 0; y < 20; y++)
if (t[y*20 + x]) {
fptr[y*640*4 + x*4] = b;
fptr[y*640*4 + x*4 + 1] = g;
fptr[y*640*4 + x*4 + 2] = r;
}
}
}
Xil_DCacheDisable();
Xil_ICacheDisable();
return 0;
}
/**
* @brief disable_caches() - Disable caches
*/
void disable_caches()
{
Xil_DCacheDisable();
Xil_ICacheDisable();
}
int main()
{
#if __aarch64__
Xil_DCacheDisable();
#endif
struct ip_addr ipaddr, netmask, gw;
/* the mac address of the board. this should be unique per board */
unsigned char mac_ethernet_address[] =
{ 0x00, 0x0a, 0x35, 0x00, 0x01, 0x02 };
echo_netif = &server_netif;
#if defined (__arm__) || defined(__aarch64__)
#if XPAR_GIGE_PCS_PMA_SGMII_CORE_PRESENT == 1 || XPAR_GIGE_PCS_PMA_1000BASEX_CORE_PRESENT == 1
ProgramSi5324();
ProgramSfpPhy();
#endif
#endif
init_platform();
#if LWIP_DHCP==1
ipaddr.addr = 0;
gw.addr = 0;
netmask.addr = 0;
#else
/* initliaze IP addresses to be used */
IP4_ADDR(&ipaddr, 192, 168, 1, 10);
IP4_ADDR(&netmask, 255, 255, 255, 0);
IP4_ADDR(&gw, 192, 168, 1, 1);
#endif
print_app_header();
lwip_init();
/* Add network interface to the netif_list, and set it as default */
if (!xemac_add(echo_netif, &ipaddr, &netmask,
&gw, mac_ethernet_address,
PLATFORM_EMAC_BASEADDR)) {
xil_printf("Error adding N/W interface\n\r");
return -1;
}
netif_set_default(echo_netif);
/* now enable interrupts */
platform_enable_interrupts();
/* specify that the network if is up */
netif_set_up(echo_netif);
#if (LWIP_DHCP==1)
/* Create a new DHCP client for this interface.
* Note: you must call dhcp_fine_tmr() and dhcp_coarse_tmr() at
* the predefined regular intervals after starting the client.
*/
dhcp_start(echo_netif);
dhcp_timoutcntr = 24;
while(((echo_netif->ip_addr.addr) == 0) && (dhcp_timoutcntr > 0))
xemacif_input(echo_netif);
if (dhcp_timoutcntr <= 0) {
if ((echo_netif->ip_addr.addr) == 0) {
xil_printf("DHCP Timeout\r\n");
xil_printf("Configuring default IP of 192.168.1.10\r\n");
IP4_ADDR(&(echo_netif->ip_addr), 192, 168, 1, 10);
IP4_ADDR(&(echo_netif->netmask), 255, 255, 255, 0);
IP4_ADDR(&(echo_netif->gw), 192, 168, 1, 1);
}
}
ipaddr.addr = echo_netif->ip_addr.addr;
gw.addr = echo_netif->gw.addr;
netmask.addr = echo_netif->netmask.addr;
#endif
print_ip_settings(&ipaddr, &netmask, &gw);
/* start the application (web server, rxtest, txtest, etc..) */
start_application();
xil_printf("Ethernet Port 0:\n\r");
EthFMC_init_axiemac(XPAR_AXIETHERNET_0_BASEADDR,mac_ethernet_address);
xil_printf("Ethernet Port 1:\n\r");
EthFMC_init_axiemac(XPAR_AXIETHERNET_1_BASEADDR,mac_ethernet_address);
xil_printf("Ethernet Port 2:\n\r");
EthFMC_init_axiemac(XPAR_AXIETHERNET_2_BASEADDR,mac_ethernet_address);
xil_printf("Ethernet Port 3:\n\r");
EthFMC_init_axiemac(XPAR_AXIETHERNET_3_BASEADDR,mac_ethernet_address);
/* receive and process packets */
while (1) {
if (TcpFastTmrFlag) {
tcp_fasttmr();
TcpFastTmrFlag = 0;
}
if (TcpSlowTmrFlag) {
tcp_slowtmr();
TcpSlowTmrFlag = 0;
}
xemacif_input(echo_netif);
transfer_data();
}
/* never reached */
cleanup_platform();
return 0;
}
/***************************************************************************//**
* @brief main
*******************************************************************************/
int initAd9361(void) {
int Status;
uint64_t Value;
uint8_t en_dis;
/*
* NOTE: The user has to choose the GPIO numbers according to desired
* carrier board. The following configuration is valid for boards other
* than the Fmcomms5.
*/
default_init_param.gpio_resetb = GPIO_RESET_PIN;
default_init_param.gpio_sync = -1;
default_init_param.gpio_cal_sw1 = -1;
default_init_param.gpio_cal_sw2 = -1;
/*
* Initialize the GPIO
*/
gpio_init(GPIO_DEVICE_ID);
gpio_direction(default_init_param.gpio_resetb, 1);
/*
* Initialize the SPI
*/
spi_init(SPI_DEVICE_ID, 1, 0);
/*
* Initialize AD9361
*/
Status = ad9361_init(&ad9361_phy, &default_init_param);
if (Status != 0) {
xil_printf("Could not initialize AD9361\r\n");
xil_printf("Status\t%d\r\n", Status);
return 1;
}
/*
* Sampling frequency
*/
Status = ad9361_set_tx_sampling_freq(ad9361_phy, SAMPLING_FREQ);
if (Status != 0) {
xil_printf("Could not set Tx sampling freq.\r\n");
return 1;
}
Status = ad9361_set_rx_sampling_freq(ad9361_phy, SAMPLING_FREQ);
if (Status != 0) {
xil_printf("Could not set Rx sampling freq.\r\n");
return 1;
}
/*
* Set Tx and Rx FIR
*/
Status = ad9361_set_tx_fir_config(ad9361_phy, tx_fir_config);
if (Status != 0) {
xil_printf("Could not set Tx FIR\r\n");
return 1;
}
Status = ad9361_set_rx_fir_config(ad9361_phy, rx_fir_config);
if (Status != 0) {
xil_printf("Could not set Rx FIR\r\n");
return 1;
}
// Enable both at the same time
Status = ad9361_set_trx_fir_en_dis(ad9361_phy, 1);
if (Status != 0) {
xil_printf("Could not enable Tx and Rx FIR\r\n");
return 1;
}
// Check status
Status = ad9361_get_tx_fir_en_dis(ad9361_phy, &en_dis);
if (Status == 0) {
xil_printf("Tx FIR status\t %d\r\n", en_dis);
} else {
xil_printf("Could not get Tx FIR enable\r\n");
return 1;
}
Status = ad9361_get_rx_fir_en_dis(ad9361_phy, &en_dis);
if (Status == 0) {
xil_printf("Rx FIR status\t %d\r\n", en_dis);
} else {
xil_printf("Could not get Rx FIR enable\r\n");
return 1;
}
/*
* Rf bandwidth
*/
Status = ad9361_set_tx_rf_bandwidth(ad9361_phy, RF_BW);
if (Status != 0) {
xil_printf("Could not set Tx Rf bandwidth\r\n");
return 1;
}
Status = ad9361_set_rx_rf_bandwidth(ad9361_phy, RF_BW);
if (Status != 0) {
xil_printf("Could not set Rx Rf bandwidth\r\n");
return 1;
}
/*
* Gain control mode
*/
Status = ad9361_set_rx_gain_control_mode(ad9361_phy, 0,
RF_GAIN_SLOWATTACK_AGC);
if (Status != 0) {
xil_printf("Could not set Rx gain control mode for channel 0\r\n");
return 1;
}
/*
* Hardware gains
*/
Status = ad9361_set_rx_rf_gain(ad9361_phy, 0, -10);
if (Status != 0) {
xil_printf("Could not set Rx gain for channel 0\r\n");
return 1;
}
Status = ad9361_get_rx_lo_freq(ad9361_phy, &Value);
if (Status == 0) {
xil_printf("LO Frequency\t %u \r\n", Value);
} else {
xil_printf("Could not get current LO frequency\r\n");
return 1;
}
#if ROE_CPRI_SINK == ROE_SINK_DAC
dac_init(ad9361_phy, DATA_SEL_DMA, 1);
#endif
#ifndef AXI_ADC_NOT_PRESENT
#if defined XILINX_PLATFORM && defined CAPTURE_SCRIPT
// NOTE: To prevent unwanted data loss, it's recommended to invalidate
// cache after each adc_capture() call, keeping in mind that the
// size of the capture and the start address must be alinged to the size
// of the cache line.
mdelay(1000);
adc_capture(16384, ADC_DDR_BASEADDR);
Xil_DCacheInvalidateRange(ADC_DDR_BASEADDR, 16384);
#endif
#endif
#ifdef CONSOLE_COMMANDS
get_help(NULL, 0);
while (1)
{
console_get_command(received_cmd);
invalid_cmd = 0;
for (cmd = 0; cmd < cmd_no; cmd++)
{
param_no = 0;
cmd_type = console_check_commands(received_cmd, cmd_list[cmd].name,
param, ¶m_no);
if (cmd_type == UNKNOWN_CMD)
{
invalid_cmd++;
}
else
{
cmd_list[cmd].function(param, param_no);
}
}
if (invalid_cmd == cmd_no)
{
console_print("Invalid command!\n");
}
}
#endif
printf("AD9361 Initialization Done.\n");
#ifdef XILINX_PLATFORM
Xil_DCacheDisable();
Xil_ICacheDisable();
#endif
return 0;
}
/**
* This function validates the partition
*
* @param FsblInstancePtr is pointer to the XFsbl Instance
*
* @param PartitionNum is the partition number in the image to be loaded
*
* @return returns the error codes described in xfsbl_error.h on any error
* returns XFSBL_SUCCESS on success
*
*****************************************************************************/
static u32 XFsbl_PartitionValidation(XFsblPs * FsblInstancePtr,
u32 PartitionNum)
{
u32 Status=XFSBL_SUCCESS;
u32 ChecksumType=0U;
s32 IsEncryptionEnabled=FALSE;
s32 IsAuthenticationEnabled=FALSE;
u32 DestinationDevice=0U;
u32 DestinationCpu=0U;
u32 ExecState=0U;
u32 CpuNo=0U;
XFsblPs_PartitionHeader * PartitionHeader;
#if defined(XFSBL_RSA)
u32 HashLen=0U;
#endif
#if defined(XFSBL_AES)
u32 ImageOffset = 0U;
u32 FsblIv[XIH_BH_IV_LENGTH / 4U];
u32 UnencryptedLength = 0;
u32 IvLocation;
#endif
#if defined(XFSBL_RSA) || defined(XFSBL_AES)
u32 Length=0U;
#endif
#if defined(XFSBL_RSA) || defined(XFSBL_AES) || defined(XFSBL_BS)
PTRSIZE LoadAddress=0U;
#endif
#if defined(XFSBL_BS)
u32 BitstreamWordSize = 0;
#endif
/**
* Update the variables
*/
PartitionHeader =
&FsblInstancePtr->ImageHeader.PartitionHeader[PartitionNum];
ChecksumType = XFsbl_GetChecksumType(PartitionHeader);
/**
* Check the encryption status
*/
if (XFsbl_IsEncrypted(PartitionHeader) ==
XIH_PH_ATTRB_ENCRYPTION )
{
IsEncryptionEnabled = TRUE;
#ifdef XFSBL_AES
/* Copy the Iv from Flash into local memory */
IvLocation = ImageOffset + XIH_BH_IV_OFFSET;
Status = FsblInstancePtr->DeviceOps.DeviceCopy(IvLocation,
(PTRSIZE) FsblIv, XIH_BH_IV_LENGTH);
if (Status != XFSBL_SUCCESS) {
XFsbl_Printf(DEBUG_GENERAL,
"XFSBL_ERROR_DECRYPTION_IV_COPY_FAIL \r\n");
Status = XFSBL_ERROR_DECRYPTION_IV_COPY_FAIL;
goto END;
}
#else
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_AES_NOT_ENABLED \r\n");
Status = XFSBL_ERROR_AES_NOT_ENABLED;
goto END;
#endif
}
/**
* check the authentication status
*/
if (XFsbl_IsRsaSignaturePresent(PartitionHeader) ==
XIH_PH_ATTRB_RSA_SIGNATURE )
{
IsAuthenticationEnabled = TRUE;
}
DestinationDevice = XFsbl_GetDestinationDevice(PartitionHeader);
DestinationCpu = XFsbl_GetDestinationCpu(PartitionHeader);
/**
* Get the execution state
*/
ExecState = XFsbl_GetA53ExecState(PartitionHeader);
/**
* if destination cpu is not present, it means it is for same cpu
*/
if (DestinationCpu == XIH_PH_ATTRB_DEST_CPU_NONE)
{
DestinationCpu = FsblInstancePtr->ProcessorID;
}
/**
* Checksum Validation
*/
if (ChecksumType == XIH_PH_ATTRB_CHECKSUM_MD5)
{
/**
* Do the checksum validation
*/
}
#if defined(XFSBL_RSA) || defined(XFSBL_AES)
if ((IsAuthenticationEnabled == TRUE) || (IsEncryptionEnabled == TRUE))
{
LoadAddress = PartitionHeader->DestinationLoadAddress;
Length = PartitionHeader->TotalDataWordLength * 4U;
Status = XFsbl_GetLoadAddress(DestinationCpu,
&LoadAddress, Length);
if (XFSBL_SUCCESS != Status)
{
goto END;
}
}
#endif
#ifdef XFSBL_BS
if ((DestinationDevice == XIH_PH_ATTRB_DEST_DEVICE_PL) &&
(LoadAddress == 0U))
{
LoadAddress = XFSBL_DDR_TEMP_ADDRESS;
}
#endif
/**
* Authentication Check
*/
if (IsAuthenticationEnabled == TRUE)
{
XFsbl_Printf(DEBUG_INFO,"Authentication Enabled\r\n");
#ifdef XFSBL_RSA
/**
* Get the Sha type to be used from
* boot header attributes
*/
if ((FsblInstancePtr->BootHdrAttributes &
XIH_BH_IMAGE_ATTRB_SHA2_MASK) ==
XIH_BH_IMAGE_ATTRB_SHA2_MASK)
{
HashLen = XFSBL_HASH_TYPE_SHA2;
} else {
HashLen = XFSBL_HASH_TYPE_SHA3;
}
/**
* cache disbale can be removed
*/
Xil_DCacheDisable();
/**
* Do the authentication validation
*/
Status = XFsbl_Authentication(FsblInstancePtr, LoadAddress, Length,
(LoadAddress + Length) - XFSBL_AUTH_CERT_MIN_SIZE,
HashLen);
if (Status != XFSBL_SUCCESS)
{
goto END;
}
#else
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_RSA_NOT_ENABLED \r\n");
Status = XFSBL_ERROR_RSA_NOT_ENABLED;
goto END;
#endif
}
/**
* Decrypt image through CSU DMA
*/
if (IsEncryptionEnabled == TRUE) {
XFsbl_Printf(DEBUG_INFO, "Decryption Enabled\r\n");
#ifdef XFSBL_AES
/* AES expects IV in big endian form */
FsblIv[0] = Xil_Htonl(FsblIv[0]);
FsblIv[1] = Xil_Htonl(FsblIv[1]);
FsblIv[2] = Xil_Htonl(FsblIv[2]);
/* Initialize the Aes Instance so that it's ready to use */
XSecure_AesInitialize(&SecureAes, &CsuDma,
XSECURE_CSU_AES_KEY_SRC_DEV, FsblIv, NULL);
XFsbl_Printf(DEBUG_INFO, " Aes initialized \r\n");
UnencryptedLength = PartitionHeader->UnEncryptedDataWordLength * 4U;
if (DestinationDevice != XIH_PH_ATTRB_DEST_DEVICE_PL) {
Status = XSecure_AesDecrypt(&SecureAes, (u8 *) LoadAddress,
(u8 *) LoadAddress, UnencryptedLength);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_DECRYPTION_FAIL;
XFsbl_Printf(DEBUG_GENERAL, "XFSBL_ERROR_DECRYPTION_FAIL\r\n");
goto END;
} else {
XFsbl_Printf(DEBUG_GENERAL, "Decryption Successful\r\n");
}
}
#else
XFsbl_Printf(DEBUG_GENERAL,"XFSBL_ERROR_AES_NOT_ENABLED \r\n");
Status = XFSBL_ERROR_AES_NOT_ENABLED;
goto END;
#endif
}
#ifdef XFSBL_BS
/**
* for PL image use CSU DMA to route to PL
*/
if (DestinationDevice == XIH_PH_ATTRB_DEST_DEVICE_PL)
{
/**
* Fsbl hook before bit stream download
*/
Status = XFsbl_HookBeforeBSDownload();
if (Status != XFSBL_SUCCESS)
{
Status = XFSBL_ERROR_HOOK_BEFORE_BITSTREAM_DOWNLOAD;
XFsbl_Printf(DEBUG_GENERAL,
"XFSBL_ERROR_HOOK_BEFORE_BITSTREAM_DOWNLOAD\r\n");
goto END;
}
XFsbl_Printf(DEBUG_GENERAL, "Bitstream download to start now\r\n");
Status = XFsbl_PcapInit();
if (Status != XFSBL_SUCCESS) {
goto END;
}
if (IsEncryptionEnabled == TRUE) {
#ifdef XFSBL_AES
/*
* The secure bitstream would be sent through CSU DMA to AES
* and the decrypted bitstream is sent directly to PCAP
* by configuring SSS appropriately
*/
Status = XSecure_AesDecrypt(&SecureAes,
(u8 *) XFSBL_DESTINATION_PCAP_ADDR,
(u8 *) LoadAddress, UnencryptedLength);
if (Status != XFSBL_SUCCESS) {
Status = XFSBL_ERROR_BITSTREAM_DECRYPTION_FAIL;
XFsbl_Printf(DEBUG_GENERAL,
"XFSBL_ERROR_BITSTREAM_DECRYPTION_FAIL\r\n");
/* Reset PL */
XFsbl_Out32(CSU_PCAP_PROG, 0x0);
goto END;
} else {
XFsbl_Printf(DEBUG_GENERAL,
"Bitstream decryption Successful\r\n");
}
#endif
}
else {
/* Use CSU DMA to load Bit stream to PL */
BitstreamWordSize = PartitionHeader->UnEncryptedDataWordLength;
Status = XFsbl_WriteToPcap(BitstreamWordSize, (u8 *) LoadAddress);
if (Status != XFSBL_SUCCESS) {
goto END;
}
}
Status = XFsbl_PLWaitForDone();
if (Status != XFSBL_SUCCESS) {
goto END;
}
/**
* Fsbl hook after bit stream download
*/
Status = XFsbl_HookAfterBSDownload();
if (Status != XFSBL_SUCCESS)
{
Status = XFSBL_ERROR_HOOK_AFTER_BITSTREAM_DOWNLOAD;
XFsbl_Printf(DEBUG_GENERAL,
"XFSBL_ERROR_HOOK_AFTER_BITSTREAM_DOWNLOAD\r\n");
goto END;
}
}
#endif
/**
* Update the handoff details
*/
if ((DestinationDevice != XIH_PH_ATTRB_DEST_DEVICE_PL) &&
(DestinationDevice != XIH_PH_ATTRB_DEST_DEVICE_PMU))
{
CpuNo = FsblInstancePtr->HandoffCpuNo;
if (XFsbl_CheckHandoffCpu(FsblInstancePtr,
DestinationCpu) == XFSBL_SUCCESS)
{
FsblInstancePtr->HandoffValues[CpuNo].CpuSettings =
DestinationCpu | ExecState;
FsblInstancePtr->HandoffValues[CpuNo].HandoffAddress =
PartitionHeader->DestinationExecutionAddress;
FsblInstancePtr->HandoffCpuNo += 1U;
}
}
END:
return Status;
}
