void omap3_prcm_save_context(void) { prcm_context.control_padconf_sys_nirq = omap_ctrl_readl(OMAP343X_CONTROL_PADCONF_SYSNIRQ); prcm_context.iva2_cm_clksel1 = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL1); prcm_context.iva2_cm_clksel2 = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSEL2); prcm_context.cm_sysconfig = __raw_readl(OMAP3430_CM_SYSCONFIG); prcm_context.sgx_cm_clksel = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSEL); prcm_context.dss_cm_clksel = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSEL); prcm_context.cam_cm_clksel = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSEL); prcm_context.per_cm_clksel = cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSEL); prcm_context.emu_cm_clksel = cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSEL1); prcm_context.emu_cm_clkstctrl = cm_read_mod_reg(OMAP3430_EMU_MOD, CM_CLKSTCTRL); prcm_context.pll_cm_autoidle2 = cm_read_mod_reg(PLL_MOD, CM_AUTOIDLE2); prcm_context.pll_cm_clksel4 = cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL4); prcm_context.pll_cm_clksel5 = cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKSEL5); prcm_context.pll_cm_clken2 = cm_read_mod_reg(PLL_MOD, OMAP3430ES2_CM_CLKEN2); prcm_context.cm_polctrl = __raw_readl(OMAP3430_CM_POLCTRL); prcm_context.iva2_cm_fclken = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_FCLKEN); prcm_context.iva2_cm_clken_pll = cm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_CM_CLKEN_PLL); prcm_context.core_cm_fclken1 = cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); prcm_context.core_cm_fclken3 = cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); prcm_context.sgx_cm_fclken = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_FCLKEN); prcm_context.wkup_cm_fclken = cm_read_mod_reg(WKUP_MOD, CM_FCLKEN); prcm_context.dss_cm_fclken = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_FCLKEN); prcm_context.cam_cm_fclken = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_FCLKEN); prcm_context.per_cm_fclken = cm_read_mod_reg(OMAP3430_PER_MOD, CM_FCLKEN); prcm_context.usbhost_cm_fclken = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_FCLKEN); prcm_context.core_cm_iclken1 = cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); prcm_context.core_cm_iclken2 = cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); prcm_context.core_cm_iclken3 = cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); prcm_context.sgx_cm_iclken = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_ICLKEN); prcm_context.wkup_cm_iclken = cm_read_mod_reg(WKUP_MOD, CM_ICLKEN); prcm_context.dss_cm_iclken = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_ICLKEN); prcm_context.cam_cm_iclken = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_ICLKEN); prcm_context.per_cm_iclken = cm_read_mod_reg(OMAP3430_PER_MOD, CM_ICLKEN); prcm_context.usbhost_cm_iclken = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_ICLKEN); prcm_context.iva2_cm_autiidle2 = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_AUTOIDLE2); prcm_context.mpu_cm_autoidle2 = cm_read_mod_reg(MPU_MOD, CM_AUTOIDLE2); prcm_context.iva2_cm_clkstctrl = cm_read_mod_reg(OMAP3430_IVA2_MOD, CM_CLKSTCTRL); prcm_context.mpu_cm_clkstctrl = cm_read_mod_reg(MPU_MOD, CM_CLKSTCTRL); prcm_context.core_cm_clkstctrl = cm_read_mod_reg(CORE_MOD, CM_CLKSTCTRL); prcm_context.sgx_cm_clkstctrl = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, CM_CLKSTCTRL); prcm_context.dss_cm_clkstctrl = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_CLKSTCTRL); prcm_context.cam_cm_clkstctrl = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_CLKSTCTRL); prcm_context.per_cm_clkstctrl = cm_read_mod_reg(OMAP3430_PER_MOD, CM_CLKSTCTRL); prcm_context.neon_cm_clkstctrl = cm_read_mod_reg(OMAP3430_NEON_MOD, CM_CLKSTCTRL); prcm_context.usbhost_cm_clkstctrl = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_CLKSTCTRL); prcm_context.core_cm_autoidle1 = cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); prcm_context.core_cm_autoidle2 = cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); prcm_context.core_cm_autoidle3 = cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); prcm_context.wkup_cm_autoidle = cm_read_mod_reg(WKUP_MOD, CM_AUTOIDLE); prcm_context.dss_cm_autoidle = cm_read_mod_reg(OMAP3430_DSS_MOD, CM_AUTOIDLE); prcm_context.cam_cm_autoidle = cm_read_mod_reg(OMAP3430_CAM_MOD, CM_AUTOIDLE); prcm_context.per_cm_autoidle = cm_read_mod_reg(OMAP3430_PER_MOD, CM_AUTOIDLE); prcm_context.usbhost_cm_autoidle = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, CM_AUTOIDLE); prcm_context.sgx_cm_sleepdep = cm_read_mod_reg(OMAP3430ES2_SGX_MOD, OMAP3430_CM_SLEEPDEP); prcm_context.dss_cm_sleepdep = cm_read_mod_reg(OMAP3430_DSS_MOD, OMAP3430_CM_SLEEPDEP); prcm_context.cam_cm_sleepdep = cm_read_mod_reg(OMAP3430_CAM_MOD, OMAP3430_CM_SLEEPDEP); prcm_context.per_cm_sleepdep = cm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_CM_SLEEPDEP); prcm_context.usbhost_cm_sleepdep = cm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, OMAP3430_CM_SLEEPDEP); prcm_context.cm_clkout_ctrl = cm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_CM_CLKOUT_CTRL_OFFSET); prcm_context.prm_clkout_ctrl = prm_read_mod_reg(OMAP3430_CCR_MOD, OMAP3_PRM_CLKOUT_CTRL_OFFSET); prcm_context.sgx_pm_wkdep = prm_read_mod_reg(OMAP3430ES2_SGX_MOD, PM_WKDEP); prcm_context.dss_pm_wkdep = prm_read_mod_reg(OMAP3430_DSS_MOD, PM_WKDEP); prcm_context.cam_pm_wkdep = prm_read_mod_reg(OMAP3430_CAM_MOD, PM_WKDEP); prcm_context.per_pm_wkdep = prm_read_mod_reg(OMAP3430_PER_MOD, PM_WKDEP); prcm_context.neon_pm_wkdep = prm_read_mod_reg(OMAP3430_NEON_MOD, PM_WKDEP); prcm_context.usbhost_pm_wkdep = prm_read_mod_reg(OMAP3430ES2_USBHOST_MOD, PM_WKDEP); prcm_context.core_pm_mpugrpsel1 = prm_read_mod_reg(CORE_MOD, OMAP3430_PM_MPUGRPSEL1); prcm_context.iva2_pm_ivagrpsel1 = prm_read_mod_reg(OMAP3430_IVA2_MOD, OMAP3430_PM_IVAGRPSEL1); prcm_context.core_pm_mpugrpsel3 = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_MPUGRPSEL3); prcm_context.core_pm_ivagrpsel3 = prm_read_mod_reg(CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); prcm_context.wkup_pm_mpugrpsel = prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_MPUGRPSEL); prcm_context.wkup_pm_ivagrpsel = prm_read_mod_reg(WKUP_MOD, OMAP3430_PM_IVAGRPSEL); prcm_context.per_pm_mpugrpsel = prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_MPUGRPSEL); prcm_context.per_pm_ivagrpsel = prm_read_mod_reg(OMAP3430_PER_MOD, OMAP3430_PM_IVAGRPSEL); prcm_context.wkup_pm_wken = prm_read_mod_reg(WKUP_MOD, PM_WKEN); return; }
static inline u32 dsps_readl(const void __iomem *addr, unsigned offset) { return __raw_readl(addr + offset); }
static __u32 scb2_read32(struct map_info *map, unsigned long ofs) { return __raw_readl(map->map_priv_1 + ofs); }
static int __exynos5_mipi_phy_control(int id, bool on, u32 reset) { static DEFINE_SPINLOCK(lock); void __iomem *addr_phy; void __iomem *addr_reset; unsigned long flags; u32 cfg; addr_phy = S5P_MIPI_DPHY_CONTROL(id); spin_lock_irqsave(&lock, flags); /* PHY PMU enable */ if (on) { cfg = __raw_readl(addr_phy); cfg |= S5P_MIPI_DPHY_ENABLE; __raw_writel(cfg, addr_phy); } /* PHY reset */ switch(id) { case 0: if (reset == S5P_MIPI_DPHY_SRESETN) { if (readl(EXYNOS5430_CAM0_STATUS) & 0x1) { addr_reset = S5P_VA_SYSREG_CAM0 + 0x1014; cfg = __raw_readl(addr_reset); cfg = on ? (cfg | MIPI_PHY_BIT0) : (cfg & ~MIPI_PHY_BIT0); __raw_writel(cfg, addr_reset); } } else { if (readl(EXYNOS5430_DISP_STATUS) & 0x1) { addr_reset = S5P_VA_SYSREG_DISP + 0x000c; cfg = __raw_readl(addr_reset); /* 0: enable reset, 1: release reset */ cfg = (cfg & ~MIPI_PHY_BIT0); __raw_writel(cfg, addr_reset); cfg = (cfg | MIPI_PHY_BIT0); __raw_writel(cfg, addr_reset); } } break; case 1: if (readl(EXYNOS5430_CAM0_STATUS) & 0x1) { addr_reset = S5P_VA_SYSREG_CAM0 + 0x1014; cfg = __raw_readl(addr_reset); cfg = on ? (cfg | MIPI_PHY_BIT1) : (cfg & ~MIPI_PHY_BIT1); __raw_writel(cfg, addr_reset); } break; case 2: if (readl(EXYNOS5430_CAM1_STATUS) & 0x1) { addr_reset = S5P_VA_SYSREG_CAM1 + 0x1020; cfg = __raw_readl(addr_reset); cfg = on ? (cfg | MIPI_PHY_BIT0) : (cfg & ~MIPI_PHY_BIT0); __raw_writel(cfg, addr_reset); } break; default: pr_err("id(%d) is invalid", id); spin_unlock_irqrestore(&lock, flags); return -EINVAL; } /* PHY PMU disable */ if (!on) { cfg = __raw_readl(addr_phy); if (id == 0) { if (!exynos5_phy0_is_running(reset)) cfg &= ~S5P_MIPI_DPHY_ENABLE; } else { cfg &= ~S5P_MIPI_DPHY_ENABLE; } __raw_writel(cfg, addr_phy); } spin_unlock_irqrestore(&lock, flags); return 0; }
static inline u32 hecc_read_mbx(struct ti_hecc_priv *priv, u32 mbxno, u32 reg) { return __raw_readl(priv->base + priv->mbx_offset + mbxno * 0x10 + reg); }
static cycle_t txx9_cs_read(void) { return __raw_readl(&txx9_cs_tmrptr->trr); }
static u32 notrace omap_32k_read_sched_clock(void) { return sync32k_cnt_reg ? __raw_readl(sync32k_cnt_reg) : 0; }
static u32 txx9ndfmc_read(struct platform_device *dev, unsigned int reg) { return __raw_readl(ndregaddr(dev, reg)); }
static inline void setup_dvi_panel(u16 h_active, u16 v_active, u16 h_blanking, u16 v_lines, u16 v1_blank_start, u16 v1_blank_end, u16 v2_blank_start, u16 v2_blank_end, u16 f1_start, u16 f1_end, u16 f2_start, u16 f2_end) { u32 val; if (!g_elcdif_axi_clk_enable) { clk_enable(g_elcdif_axi_clk); g_elcdif_axi_clk_enable = true; } /* 32bit packed format (RGB) */ __raw_writel(BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT, elcdif_base + HW_ELCDIF_CTRL1_CLR); __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7) | BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW, elcdif_base + HW_ELCDIF_CTRL1_SET); val = __raw_readl(elcdif_base + HW_ELCDIF_TRANSFER_COUNT); val &= ~(BM_ELCDIF_TRANSFER_COUNT_V_COUNT | BM_ELCDIF_TRANSFER_COUNT_H_COUNT); val |= BF_ELCDIF_TRANSFER_COUNT_H_COUNT(h_active) | BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v_active); __raw_writel(val, elcdif_base + HW_ELCDIF_TRANSFER_COUNT); /* set elcdif to DVI mode */ __raw_writel(BM_ELCDIF_CTRL_DVI_MODE, elcdif_base + HW_ELCDIF_CTRL_SET); __raw_writel(BM_ELCDIF_CTRL_VSYNC_MODE, elcdif_base + HW_ELCDIF_CTRL_CLR); __raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE, elcdif_base + HW_ELCDIF_CTRL_CLR); __raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT, elcdif_base + HW_ELCDIF_CTRL_SET); /* convert input RGB -> YCbCr */ __raw_writel(BM_ELCDIF_CTRL_RGB_TO_YCBCR422_CSC, elcdif_base + HW_ELCDIF_CTRL_SET); /* interlace odd and even fields */ __raw_writel(BM_ELCDIF_CTRL1_INTERLACE_FIELDS, elcdif_base + HW_ELCDIF_CTRL1_SET); __raw_writel(BM_ELCDIF_CTRL_WORD_LENGTH | BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE | BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH, elcdif_base + HW_ELCDIF_CTRL_CLR); __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) | /* 24 bit */ BM_ELCDIF_CTRL_DATA_SELECT | /* data mode */ BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0) | /* no swap */ BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(1), /* 8 bit */ elcdif_base + HW_ELCDIF_CTRL_SET); /* ELCDIF_DVI */ /* set frame size */ val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL0); __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL0); /* set start/end of field-1 and start of field-2 */ val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL1); val &= ~(BM_ELCDIF_DVICTRL1_F1_START_LINE | BM_ELCDIF_DVICTRL1_F1_END_LINE | BM_ELCDIF_DVICTRL1_F2_START_LINE); val |= BF_ELCDIF_DVICTRL1_F1_START_LINE(f1_start) | BF_ELCDIF_DVICTRL1_F1_END_LINE(f1_end) | BF_ELCDIF_DVICTRL1_F2_START_LINE(f2_start); __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL1); /* set first vertical blanking interval and end of filed-2 */ val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL2); val &= ~(BM_ELCDIF_DVICTRL2_F2_END_LINE | BM_ELCDIF_DVICTRL2_V1_BLANK_START_LINE | BM_ELCDIF_DVICTRL2_V1_BLANK_END_LINE); val |= BF_ELCDIF_DVICTRL2_F2_END_LINE(f2_end) | BF_ELCDIF_DVICTRL2_V1_BLANK_START_LINE(v1_blank_start) | BF_ELCDIF_DVICTRL2_V1_BLANK_END_LINE(v1_blank_end); __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL2); /* set second vertical blanking interval */ val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL3); val &= ~(BM_ELCDIF_DVICTRL3_V2_BLANK_START_LINE | BM_ELCDIF_DVICTRL3_V2_BLANK_END_LINE); val |= BF_ELCDIF_DVICTRL3_V2_BLANK_START_LINE(v2_blank_start) | BF_ELCDIF_DVICTRL3_V2_BLANK_END_LINE(v2_blank_end); __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL3); /* fill the rest area black color if the input frame * is not 720 pixels/line */ if (h_active != 720) { /* the input frame can't be less then (720-256) pixels/line */ if (720 - h_active > 0xff) h_active = 720 - 0xff; val = __raw_readl(elcdif_base + HW_ELCDIF_DVICTRL4); val &= ~(BM_ELCDIF_DVICTRL4_H_FILL_CNT | BM_ELCDIF_DVICTRL4_Y_FILL_VALUE | BM_ELCDIF_DVICTRL4_CB_FILL_VALUE | BM_ELCDIF_DVICTRL4_CR_FILL_VALUE); val |= BF_ELCDIF_DVICTRL4_H_FILL_CNT(720 - h_active) | BF_ELCDIF_DVICTRL4_Y_FILL_VALUE(16) | BF_ELCDIF_DVICTRL4_CB_FILL_VALUE(128) | BF_ELCDIF_DVICTRL4_CR_FILL_VALUE(128); __raw_writel(val, elcdif_base + HW_ELCDIF_DVICTRL4); } /* Color Space Conversion RGB->YCbCr */ val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF0); val &= ~(BM_ELCDIF_CSC_COEFF0_C0 | BM_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER); val |= BF_ELCDIF_CSC_COEFF0_C0(0x41) | BF_ELCDIF_CSC_COEFF0_CSC_SUBSAMPLE_FILTER(3); __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF0); val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF1); val &= ~(BM_ELCDIF_CSC_COEFF1_C1 | BM_ELCDIF_CSC_COEFF1_C2); val |= BF_ELCDIF_CSC_COEFF1_C1(0x81) | BF_ELCDIF_CSC_COEFF1_C2(0x19); __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF1); val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF2); val &= ~(BM_ELCDIF_CSC_COEFF2_C3 | BM_ELCDIF_CSC_COEFF2_C4); val |= BF_ELCDIF_CSC_COEFF2_C3(0x3DB) | BF_ELCDIF_CSC_COEFF2_C4(0x3B6); __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF2); val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF3); val &= ~(BM_ELCDIF_CSC_COEFF3_C5 | BM_ELCDIF_CSC_COEFF3_C6); val |= BF_ELCDIF_CSC_COEFF3_C5(0x70) | BF_ELCDIF_CSC_COEFF3_C6(0x70); __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF3); val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_COEFF4); val &= ~(BM_ELCDIF_CSC_COEFF4_C7 | BM_ELCDIF_CSC_COEFF4_C8); val |= BF_ELCDIF_CSC_COEFF4_C7(0x3A2) | BF_ELCDIF_CSC_COEFF4_C8(0x3EE); __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_COEFF4); val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_OFFSET); val &= ~(BM_ELCDIF_CSC_OFFSET_CBCR_OFFSET | BM_ELCDIF_CSC_OFFSET_Y_OFFSET); val |= BF_ELCDIF_CSC_OFFSET_CBCR_OFFSET(0x80) | BF_ELCDIF_CSC_OFFSET_Y_OFFSET(0x10); __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_OFFSET); val = __raw_readl(elcdif_base + HW_ELCDIF_CSC_LIMIT); val &= ~(BM_ELCDIF_CSC_LIMIT_CBCR_MIN | BM_ELCDIF_CSC_LIMIT_CBCR_MAX | BM_ELCDIF_CSC_LIMIT_Y_MIN | BM_ELCDIF_CSC_LIMIT_Y_MAX); val |= BF_ELCDIF_CSC_LIMIT_CBCR_MIN(16) | BF_ELCDIF_CSC_LIMIT_CBCR_MAX(240) | BF_ELCDIF_CSC_LIMIT_Y_MIN(16) | BF_ELCDIF_CSC_LIMIT_Y_MAX(235); __raw_writel(val, elcdif_base + HW_ELCDIF_CSC_LIMIT); return; }
static inline u32 dm644x_reg_modify(void *reg, u32 val, u32 mask) { u32 new_val = (__raw_readl(reg) & ~mask) | (val & mask); __raw_writel(new_val, reg); return new_val; }
/* Read a register in CM2 */ u32 omap4_cm2_read_inst_reg(s16 inst, u16 reg) { return __raw_readl(OMAP44XX_CM2_REGADDR(inst, reg)); }
static int exynos4_usb_phy20_init(struct platform_device *pdev) { u32 phypwr, phyclk, rstcon; atomic_inc(&host_usage); if (exynos4_usb_phy20_is_on()) { dev_err(&pdev->dev, "Already power on PHY\n"); return 0; } /* * set XuhostOVERCUR to in-active by controlling ET6PUD[15:14] * 0x0 : pull-up/down disabled * 0x1 : pull-down enabled * 0x2 : reserved * 0x3 : pull-up enabled */ writel((__raw_readl(ETC6PUD) & ~(0x3 << 14)) | (0x3 << 14), ETC6PUD); exynos_usb_phy_control(USB_PHY | USB_PHY_HSIC0 | USB_PHY_HSIC1, PHY_ENABLE); /* set clock frequency for PLL */ phyclk = exynos_usb_phy_set_clock(pdev); /* COMMON Block configuration during suspend */ phyclk &= ~(PHY0_COMMON_ON_N | PHY1_COMMON_ON_N); writel(phyclk, EXYNOS4_PHYCLK); /* set to normal of Device */ phypwr = readl(EXYNOS4_PHYPWR) & ~PHY0_NORMAL_MASK; writel(phypwr, EXYNOS4_PHYPWR); /* set to normal of Host */ phypwr = readl(EXYNOS4_PHYPWR); phypwr &= ~(PHY1_STD_NORMAL_MASK | EXYNOS4X12_HSIC0_NORMAL_MASK | EXYNOS4X12_HSIC1_NORMAL_MASK); writel(phypwr, EXYNOS4_PHYPWR); /* reset both PHY and Link of Device */ rstcon = readl(EXYNOS4_RSTCON) | PHY0_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); udelay(10); rstcon &= ~PHY0_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); /* reset both PHY and Link of Host */ rstcon = readl(EXYNOS4_RSTCON) | EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK | EXYNOS4X12_PHY1_SWRST_MASK; writel(rstcon, EXYNOS4_RSTCON); udelay(10); rstcon &= ~(EXYNOS4X12_HOST_LINK_PORT_SWRST_MASK | EXYNOS4X12_PHY1_SWRST_MASK); writel(rstcon, EXYNOS4_RSTCON); udelay(80); return 0; }
/* * While SL2C is architecturally visible, reflected in CLIDR/CCSIDR * cp15 regs and therefore common ARMv7 clean by set/way is supposed to * be effective, it is NOT (does not evict dirty lines). * Therefore, added clean using the implementation specific register. */ void v7_outer_cache_flush_all(void) { __raw_writel(1, WHITNEY_L2_CLEANALL); while (__raw_readl(WHITNEY_L2_CLEANALL) & 1) ; }
u32 omap2_prm_read_mod_reg(s16 module, u16 idx) { return __raw_readl(prm_base + module + idx); }
/*! * @brief asrc interrupt handler */ static irqreturn_t asrc_isr(int irq, void *dev_id) { unsigned long status; int reg = 0x40; status = __raw_readl(asrc_vrt_base_addr + ASRC_ASRSTR_REG); if (g_asrc_data->asrc_pair[ASRC_PAIR_A].active == 1) { if (status & ASRC_ASRSTR_ATQOL) g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= ASRC_TASK_Q_OVERLOAD; if (status & ASRC_ASRSTR_AOOLA) g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= ASRC_OUTPUT_TASK_OVERLOAD; if (status & ASRC_ASRSTR_AIOLA) g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= ASRC_INPUT_TASK_OVERLOAD; if (status & ASRC_ASRSTR_AODOA) g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= ASRC_OUTPUT_BUFFER_OVERFLOW; if (status & ASRC_ASRSTR_AIDUA) g_asrc_data->asrc_pair[ASRC_PAIR_A].overload_error |= ASRC_INPUT_BUFFER_UNDERRUN; } else if (g_asrc_data->asrc_pair[ASRC_PAIR_B].active == 1) { if (status & ASRC_ASRSTR_ATQOL) g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= ASRC_TASK_Q_OVERLOAD; if (status & ASRC_ASRSTR_AOOLB) g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= ASRC_OUTPUT_TASK_OVERLOAD; if (status & ASRC_ASRSTR_AIOLB) g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= ASRC_INPUT_TASK_OVERLOAD; if (status & ASRC_ASRSTR_AODOB) g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= ASRC_OUTPUT_BUFFER_OVERFLOW; if (status & ASRC_ASRSTR_AIDUB) g_asrc_data->asrc_pair[ASRC_PAIR_B].overload_error |= ASRC_INPUT_BUFFER_UNDERRUN; } else if (g_asrc_data->asrc_pair[ASRC_PAIR_C].active == 1) { if (status & ASRC_ASRSTR_ATQOL) g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= ASRC_TASK_Q_OVERLOAD; if (status & ASRC_ASRSTR_AOOLC) g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= ASRC_OUTPUT_TASK_OVERLOAD; if (status & ASRC_ASRSTR_AIOLC) g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= ASRC_INPUT_TASK_OVERLOAD; if (status & ASRC_ASRSTR_AODOC) g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= ASRC_OUTPUT_BUFFER_OVERFLOW; if (status & ASRC_ASRSTR_AIDUC) g_asrc_data->asrc_pair[ASRC_PAIR_C].overload_error |= ASRC_INPUT_BUFFER_UNDERRUN; } /* try to clean the overload error */ __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRSTR_REG); return IRQ_HANDLED; }
static inline void setup_dotclk_panel(u32 pixel_clk, u16 v_pulse_width, u16 v_period, u16 v_wait_cnt, u16 v_active, u16 h_pulse_width, u16 h_period, u16 h_wait_cnt, u16 h_active, int in_pixel_format, int out_pixel_format, struct elcdif_signal_cfg sig_cfg, int enable_present) { u32 val, rounded_pixel_clk; if (!g_elcdif_axi_clk_enable) { clk_enable(g_elcdif_axi_clk); g_elcdif_axi_clk_enable = true; } dev_dbg(g_elcdif_dev, "pixel clk = %d\n", pixel_clk); rounded_pixel_clk = clk_round_rate(g_elcdif_pix_clk, pixel_clk); clk_set_rate(g_elcdif_pix_clk, rounded_pixel_clk); __raw_writel(BM_ELCDIF_CTRL_DATA_SHIFT_DIR, elcdif_base + HW_ELCDIF_CTRL_CLR); __raw_writel(BM_ELCDIF_CTRL_SHIFT_NUM_BITS, elcdif_base + HW_ELCDIF_CTRL_CLR); __raw_writel(BF_ELCDIF_CTRL2_OUTSTANDING_REQS (BV_ELCDIF_CTRL2_OUTSTANDING_REQS__REQ_8), elcdif_base + HW_ELCDIF_CTRL2_SET); /* Recover on underflow */ __raw_writel(BM_ELCDIF_CTRL1_RECOVER_ON_UNDERFLOW, elcdif_base + HW_ELCDIF_CTRL1_SET); /* Configure the input pixel format */ __raw_writel(BM_ELCDIF_CTRL_WORD_LENGTH | BM_ELCDIF_CTRL_INPUT_DATA_SWIZZLE | BM_ELCDIF_CTRL_DATA_FORMAT_16_BIT | BM_ELCDIF_CTRL_DATA_FORMAT_18_BIT | BM_ELCDIF_CTRL_DATA_FORMAT_24_BIT, elcdif_base + HW_ELCDIF_CTRL_CLR); __raw_writel(BM_ELCDIF_CTRL1_BYTE_PACKING_FORMAT, elcdif_base + HW_ELCDIF_CTRL1_CLR); switch (in_pixel_format) { case ELCDIF_PIX_FMT_RGB565: __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF), elcdif_base + HW_ELCDIF_CTRL1_SET); __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(0) | BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0), elcdif_base + HW_ELCDIF_CTRL_SET); break; case ELCDIF_PIX_FMT_RGB24: __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0xF), elcdif_base + HW_ELCDIF_CTRL1_SET); __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) | BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0), elcdif_base + HW_ELCDIF_CTRL_SET); break; case ELCDIF_PIX_FMT_RGB32: __raw_writel(BF_ELCDIF_CTRL1_BYTE_PACKING_FORMAT(0x7), elcdif_base + HW_ELCDIF_CTRL1_SET); __raw_writel(BF_ELCDIF_CTRL_WORD_LENGTH(3) | BF_ELCDIF_CTRL_INPUT_DATA_SWIZZLE(0), elcdif_base + HW_ELCDIF_CTRL_SET); break; default: dev_err(g_elcdif_dev, "ELCDIF unsupported input pixel format " "%d\n", in_pixel_format); break; } /* Configure the output pixel format */ __raw_writel(BM_ELCDIF_CTRL_LCD_DATABUS_WIDTH, elcdif_base + HW_ELCDIF_CTRL_CLR); switch (out_pixel_format) { case ELCDIF_PIX_FMT_RGB565: __raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(0), elcdif_base + HW_ELCDIF_CTRL_SET); break; case ELCDIF_PIX_FMT_RGB666: __raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(2), elcdif_base + HW_ELCDIF_CTRL_SET); break; case ELCDIF_PIX_FMT_RGB24: __raw_writel(BF_ELCDIF_CTRL_LCD_DATABUS_WIDTH(3), elcdif_base + HW_ELCDIF_CTRL_SET); break; default: dev_err(g_elcdif_dev, "ELCDIF unsupported output pixel format " "%d\n", out_pixel_format); break; } val = __raw_readl(elcdif_base + HW_ELCDIF_TRANSFER_COUNT); val &= ~(BM_ELCDIF_TRANSFER_COUNT_V_COUNT | BM_ELCDIF_TRANSFER_COUNT_H_COUNT); val |= BF_ELCDIF_TRANSFER_COUNT_H_COUNT(h_active) | BF_ELCDIF_TRANSFER_COUNT_V_COUNT(v_active); __raw_writel(val, elcdif_base + HW_ELCDIF_TRANSFER_COUNT); __raw_writel(BM_ELCDIF_CTRL_VSYNC_MODE, elcdif_base + HW_ELCDIF_CTRL_CLR); __raw_writel(BM_ELCDIF_CTRL_WAIT_FOR_VSYNC_EDGE, elcdif_base + HW_ELCDIF_CTRL_CLR); __raw_writel(BM_ELCDIF_CTRL_DVI_MODE, elcdif_base + HW_ELCDIF_CTRL_CLR); __raw_writel(BM_ELCDIF_CTRL_DOTCLK_MODE, elcdif_base + HW_ELCDIF_CTRL_SET); __raw_writel(BM_ELCDIF_CTRL_BYPASS_COUNT, elcdif_base + HW_ELCDIF_CTRL_SET); val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0); val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_POL | BM_ELCDIF_VDCTRL0_HSYNC_POL | BM_ELCDIF_VDCTRL0_ENABLE_POL | BM_ELCDIF_VDCTRL0_DOTCLK_POL); if (sig_cfg.Vsync_pol) val |= BM_ELCDIF_VDCTRL0_VSYNC_POL; if (sig_cfg.Hsync_pol) val |= BM_ELCDIF_VDCTRL0_HSYNC_POL; if (sig_cfg.clk_pol) val |= BM_ELCDIF_VDCTRL0_DOTCLK_POL; if (sig_cfg.enable_pol) val |= BM_ELCDIF_VDCTRL0_ENABLE_POL; __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0); /* vsync is output */ val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0); val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_OEB); __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0); /* * need enable sig for true RGB i/f. Or, if not true RGB, leave it * zero. */ if (enable_present) { val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0); val |= BM_ELCDIF_VDCTRL0_ENABLE_PRESENT; __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0); } /* * For DOTCLK mode, count VSYNC_PERIOD in terms of complete hz lines */ val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL0); val &= ~(BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT); val |= BM_ELCDIF_VDCTRL0_VSYNC_PERIOD_UNIT | BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT; __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL0); __raw_writel(BM_ELCDIF_VDCTRL0_VSYNC_PULSE_WIDTH, elcdif_base + HW_ELCDIF_VDCTRL0_CLR); __raw_writel(v_pulse_width, elcdif_base + HW_ELCDIF_VDCTRL0_SET); __raw_writel(BF_ELCDIF_VDCTRL1_VSYNC_PERIOD(v_period), elcdif_base + HW_ELCDIF_VDCTRL1); __raw_writel(BF_ELCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(h_pulse_width) | BF_ELCDIF_VDCTRL2_HSYNC_PERIOD(h_period), elcdif_base + HW_ELCDIF_VDCTRL2); val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL4); val &= ~BM_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT; val |= BF_ELCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(h_active); __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL4); val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL3); val &= ~(BM_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT | BM_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT); val |= BF_ELCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(h_wait_cnt) | BF_ELCDIF_VDCTRL3_VERTICAL_WAIT_CNT(v_wait_cnt); __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL3); val = __raw_readl(elcdif_base + HW_ELCDIF_VDCTRL4); val |= BM_ELCDIF_VDCTRL4_SYNC_SIGNALS_ON; __raw_writel(val, elcdif_base + HW_ELCDIF_VDCTRL4); return; }
int s3cfb_clk_on(struct platform_device *pdev, struct clk **s3cfb_clk) { struct clk *sclk = NULL; struct clk *mout_mpll = NULL; struct clk *lcd_clk = NULL; struct clksrc_clk *src_clk = NULL; struct s3c_platform_fb *pdata = pdev->dev.platform_data; struct s3cfb_lcd *lcd = (struct s3cfb_lcd *)pdata->lcd; u32 rate = 0, clkdiv = 0; int ret = 0; lcd_clk = clk_get(&pdev->dev, "lcd"); if (IS_ERR(lcd_clk)) { dev_err(&pdev->dev, "failed to get operation clk for fimd\n"); goto err_clk0; } ret = clk_enable(lcd_clk); if (ret < 0) { dev_err(&pdev->dev, "failed to clk_enable of lcd clk for fimd\n"); goto err_clk0; } clk_put(lcd_clk); sclk = clk_get(&pdev->dev, "sclk_fimd"); if (IS_ERR(sclk)) { dev_err(&pdev->dev, "failed to get sclk for fimd\n"); goto err_clk1; } if (soc_is_exynos4210()) mout_mpll = clk_get(&pdev->dev, "mout_mpll"); else mout_mpll = clk_get(&pdev->dev, "mout_mpll_user"); if (IS_ERR(mout_mpll)) { dev_err(&pdev->dev, "failed to get mout_mpll for fimd\n"); goto err_clk2; } ret = clk_set_parent(sclk, mout_mpll); if (ret < 0) { dev_err(&pdev->dev, "failed to clk_set_parent for fimd\n"); goto err_clk2; } if (!lcd->vclk) { rate = get_clk_rate(pdev, mout_mpll); if (!rate) rate = 800 * MHZ; /* MOUT PLL */ lcd->vclk = rate; } else rate = lcd->vclk; ret = clk_set_rate(sclk, rate); if (ret < 0) { dev_err(&pdev->dev, "failed to clk_set_rate of sclk for fimd\n"); goto err_clk2; } dev_dbg(&pdev->dev, "set fimd sclk rate to %d\n", rate); clk_put(mout_mpll); ret = clk_enable(sclk); if (ret < 0) { dev_err(&pdev->dev, "failed to clk_enable of sclk for fimd\n"); goto err_clk2; } *s3cfb_clk = sclk; #ifdef CONFIG_FB_S5P_MIPI_DSIM s3cfb_mipi_clk_enable(1); #endif #ifdef CONFIG_FB_S5P_MDNIE s3cfb_mdnie_clk_on(rate); #ifdef CONFIG_FB_MDNIE_PWM s3cfb_mdnie_pwm_clk_on(); #endif #endif src_clk = container_of(sclk, struct clksrc_clk, clk); clkdiv = __raw_readl(src_clk->reg_div.reg); dev_info(&pdev->dev, "fimd sclk rate %ld, clkdiv 0x%x\n", clk_get_rate(sclk), clkdiv); return 0; err_clk2: clk_put(mout_mpll); err_clk1: clk_put(sclk); err_clk0: clk_put(lcd_clk); return -EINVAL; }
static void __raw_bits_and(unsigned int v, unsigned int a) { __raw_writel((__raw_readl(a) & v), a); }
static inline void iommu_mm_reg_write(u32 reg, u32 val, u32 msk) { __raw_writel((__raw_readl((void *)reg) & ~msk) | val, (void *)reg); }
/* Interrupt handler */ static irqreturn_t omap4_keypad_interrupt(int irq, void *dev_id) { struct omap4_keypad *keypad_data = dev_id; struct input_dev *input_dev = keypad_data->input; unsigned char key_state[ARRAY_SIZE(keypad_data->key_state)]; unsigned int col, row, code, changed; u32 *new_state = (u32 *) key_state; /* */ wake_lock_timeout(&keypad_data->wlock, 1 * HZ); *new_state = __raw_readl(keypad_data->base + OMAP4_KBD_FULLCODE31_0); *(new_state + 1) = __raw_readl(keypad_data->base + OMAP4_KBD_FULLCODE63_32); // if(debug_mask) { printk("========================================================\n"); printk("%s: [%#x][%#x]\n", __func__, *new_state, *(new_state+1)); printk("========================================================\n"); } // for (col = 0; col < keypad_data->cols; col++) { changed = key_state[col] ^ keypad_data->key_state[col]; if (!changed) continue; for (row = 0; row < keypad_data->rows; row++) { if (changed & (1 << row)) { code = MATRIX_SCAN_CODE(row, col, keypad_data->row_shift); // if(debug_mask) { printk("%s: [changed][col][row][code] = [%#x][%d][%d][%d]\n", __func__, changed, col, row, code); printk("========================================================\n"); } // // #ifdef CONFIG_MACH_LGE_COSMO if( keypad_data->keymap[code] && !atcmd_keylock) { #else if( keypad_data->keymap[code] ) { #endif // input_event(input_dev, EV_MSC, MSC_SCAN, code); input_report_key(input_dev, keypad_data->keymap[code], (bool)(key_state[col] & (1 << row))); #ifdef CONFIG_MACH_LGE_U2 /* */ printk("[omap4-keypad] %s KEY %s\n", (keypad_data->keymap[code] == KEY_VOLUMEUP) ? "Vol_UP" : ((keypad_data->keymap[code] == KEY_VOLUMEDOWN) ? "Vol_DOWN" : "HOME"), (key_state[col] & (1 << row)) ? "PRESS" : "RELEASE" ); #else printk("[omap4-keypad] %s KEY %s\n", (keypad_data->keymap[code] == KEY_VOLUMEUP) ? "Vol_UP" : ((keypad_data->keymap[code] == KEY_VOLUMEDOWN) ? "Vol_DOWN" : "CAPTURE"), (key_state[col] & (1 << row)) ? "PRESS" : "RELEASE" ); #endif #ifdef CONFIG_INPUT_LGE_GKPD gkpd_report_key(keypad_data->keymap[code], (bool)(key_state[col] & (1 << row))); #endif break; } /* */ #ifdef CONFIG_KEYBOARD_OMAP4_SAFEMODE if (keypad_data->keymap[code] == KEY_VOLUMEUP) { safemode_key = !!(key_state[col] & (1 << row)); } #endif } } } input_sync(input_dev); memcpy(keypad_data->key_state, key_state, sizeof(keypad_data->key_state)); /* clear pending interrupts */ __raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS), keypad_data->base + OMAP4_KBD_IRQSTATUS); printk("#################################### %s is finished!!!!!\n", __func__); return IRQ_HANDLED; } static int omap4_keypad_open(struct input_dev *input) { struct omap4_keypad *keypad_data = input_get_drvdata(input); #ifdef KBD_DEBUG printk("omap4-keypad: omap4_keypad_open \n"); #endif pm_runtime_get_sync(input->dev.parent); disable_irq(keypad_data->irq); __raw_writel(OMAP4_DEF_CTRL_NOSOFTMODE | (OMAP4_VAL_PVT << OMAP4_DEF_CTRL_PTV), keypad_data->base + OMAP4_KBD_CTRL); __raw_writel(OMAP4_VAL_DEBOUNCINGTIME, keypad_data->base + OMAP4_KBD_DEBOUNCINGTIME); /* Enable event IRQ*/ __raw_writel(OMAP4_DEF_IRQENABLE_EVENTEN, keypad_data->base + OMAP4_KBD_IRQENABLE); /* Enable event wkup*/ __raw_writel(OMAP4_DEF_WUP_EVENT_ENA, keypad_data->base + OMAP4_KBD_WAKEUPENABLE); /* clear pending interrupts */ __raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS), keypad_data->base + OMAP4_KBD_IRQSTATUS); enable_irq(keypad_data->irq); return 0; } static void omap4_keypad_close(struct input_dev *input) { struct omap4_keypad *keypad_data = input_get_drvdata(input); disable_irq(keypad_data->irq); /* Disable interrupts */ __raw_writel(OMAP4_VAL_IRQDISABLE, keypad_data->base + OMAP4_KBD_IRQENABLE); /* clear pending interrupts */ __raw_writel(__raw_readl(keypad_data->base + OMAP4_KBD_IRQSTATUS), keypad_data->base + OMAP4_KBD_IRQSTATUS); enable_irq(keypad_data->irq); #ifdef KBD_DEBUG printk("omap4-keypad: omap4_keypad_close \n"); #endif pm_runtime_put_sync(input->dev.parent); } static int __devinit omap4_keypad_probe(struct platform_device *pdev) { const struct omap4_keypad_platform_data *pdata; struct omap4_keypad *keypad_data; struct input_dev *input_dev; struct resource *res; resource_size_t size; unsigned int row_shift, max_keys; int irq; int error; /* platform data */ pdata = pdev->dev.platform_data; if (!pdata) { dev_err(&pdev->dev, "no platform data defined\n"); return -EINVAL; } res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) { dev_err(&pdev->dev, "no base address specified\n"); return -EINVAL; } irq = platform_get_irq(pdev, 0); if (!irq) { dev_err(&pdev->dev, "no keyboard irq assigned\n"); return -EINVAL; } if (!pdata->keymap_data) { dev_err(&pdev->dev, "no keymap data defined\n"); return -EINVAL; } row_shift = get_count_order(pdata->cols); max_keys = pdata->rows << row_shift; keypad_data = kzalloc(sizeof(struct omap4_keypad) + max_keys * sizeof(keypad_data->keymap[0]), GFP_KERNEL); if (!keypad_data) { dev_err(&pdev->dev, "keypad_data memory allocation failed\n"); return -ENOMEM; } size = resource_size(res); res = request_mem_region(res->start, size, pdev->name); if (!res) { dev_err(&pdev->dev, "can't request mem region\n"); error = -EBUSY; goto err_free_keypad; } keypad_data->base = ioremap(res->start, resource_size(res)); if (!keypad_data->base) { dev_err(&pdev->dev, "can't ioremap mem resource\n"); error = -ENOMEM; goto err_release_mem; } keypad_data->irq = irq; keypad_data->row_shift = row_shift; keypad_data->rows = pdata->rows; keypad_data->cols = pdata->cols; keypad_data->keypad_pad_wkup = pdata->keypad_pad_wkup; /* input device allocation */ keypad_data->input = input_dev = input_allocate_device(); if (!input_dev) { error = -ENOMEM; goto err_unmap; } input_dev->name = pdev->name; input_dev->dev.parent = &pdev->dev; input_dev->id.bustype = BUS_HOST; input_dev->id.vendor = 0x0001; input_dev->id.product = 0x0001; input_dev->id.version = 0x0001; input_dev->open = omap4_keypad_open; input_dev->close = omap4_keypad_close; input_dev->keycode = keypad_data->keymap; input_dev->keycodesize = sizeof(keypad_data->keymap[0]); input_dev->keycodemax = max_keys; __set_bit(EV_KEY, input_dev->evbit); __set_bit(EV_REP, input_dev->evbit); input_set_capability(input_dev, EV_MSC, MSC_SCAN); input_set_drvdata(input_dev, keypad_data); matrix_keypad_build_keymap(pdata->keymap_data, row_shift, input_dev->keycode, input_dev->keybit); /* */ #if defined(CONFIG_MHL_INPUT_RCP) hdmi_common_register_keys(input_dev); #endif /* */ #if defined(CONFIG_SND_OMAP_SOC_LGE_JACK) __set_bit(KEY_HOOK, input_dev->keybit); #endif /* */ wake_lock_init(&keypad_data->wlock, WAKE_LOCK_SUSPEND, "omap4-keypad"); /* * Set irq level detection for mpu. Edge event are missed * in gic if the mpu is in low power and keypad event * is a wakeup. */ error = request_irq(keypad_data->irq, omap4_keypad_interrupt, IRQF_TRIGGER_HIGH, "omap4-keypad", keypad_data); if (error) { dev_err(&pdev->dev, "failed to register interrupt\n"); goto err_free_input; } enable_irq_wake(OMAP44XX_IRQ_KBD_CTL); pm_runtime_enable(&pdev->dev); error = input_register_device(keypad_data->input); if (error < 0) { dev_err(&pdev->dev, "failed to register input device\n"); goto err_pm_disable; } platform_set_drvdata(pdev, keypad_data); /* */ #ifdef CONFIG_KEYBOARD_OMAP4_SAFEMODE error = device_create_file(&pdev->dev, &dev_attr_key_saving); if (error < 0) { dev_warn(&pdev->dev, "failed to create sysfs for key_saving\n"); } #endif // error = device_create_file(&pdev->dev, &dev_attr_keypad_debug); if (error < 0) { dev_warn(&pdev->dev, "failed to create sysfs for keypad_debug\n"); } // // #ifdef CONFIG_MACH_LGE_COSMO error = device_create_file(&pdev->dev, &dev_attr_keylock); if (error) { printk( "keypad: keylock create file: Fail\n"); device_remove_file(&pdev->dev, &dev_attr_keylock); } #endif // /* */ #ifdef CONFIG_MACH_LGE lge_input_set(input_dev); #endif return 0; err_pm_disable: pm_runtime_disable(&pdev->dev); free_irq(keypad_data->irq, keypad_data); /* */ wake_lock_destroy(&keypad_data->wlock); err_free_input: input_free_device(input_dev); err_unmap: iounmap(keypad_data->base); err_release_mem: release_mem_region(res->start, size); err_free_keypad: kfree(keypad_data); return error; } static int __devexit omap4_keypad_remove(struct platform_device *pdev) { struct omap4_keypad *keypad_data = platform_get_drvdata(pdev); struct resource *res; // device_remove_file(&pdev->dev, &dev_attr_keypad_debug); // // #ifdef CONFIG_MACH_LGE_COSMO device_remove_file(&pdev->dev, &dev_attr_keylock); #endif // /* */ #ifdef CONFIG_KEYBOARD_OMAP4_SAFEMODE device_remove_file(&pdev->dev, &dev_attr_key_saving); #endif free_irq(keypad_data->irq, keypad_data); /* */ wake_lock_destroy(&keypad_data->wlock); pm_runtime_disable(&pdev->dev); input_unregister_device(keypad_data->input); iounmap(keypad_data->base); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); release_mem_region(res->start, resource_size(res)); kfree(keypad_data); platform_set_drvdata(pdev, NULL); return 0; } static int omap4_keypad_suspend(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); struct omap4_keypad *keypad_data = platform_get_drvdata(pdev); if (keypad_data->keypad_pad_wkup) keypad_data->keypad_pad_wkup(1); return 0; } static int omap4_keypad_resume(struct device *dev) { struct platform_device *pdev = to_platform_device(dev); struct omap4_keypad *keypad_data = platform_get_drvdata(pdev); if (keypad_data->keypad_pad_wkup) keypad_data->keypad_pad_wkup(0); return 0; } static const struct dev_pm_ops omap4_keypad_pm_ops = { .suspend = omap4_keypad_suspend, .resume = omap4_keypad_resume, }; static struct platform_driver omap4_keypad_driver = { .probe = omap4_keypad_probe, .remove = __devexit_p(omap4_keypad_remove), .driver = { .name = "omap4-keypad", .owner = THIS_MODULE, .pm = &omap4_keypad_pm_ops, }, }; static int __init omap4_keypad_init(void) { return platform_driver_register(&omap4_keypad_driver); } module_init(omap4_keypad_init); static void __exit omap4_keypad_exit(void) { platform_driver_unregister(&omap4_keypad_driver); }
static inline u32 omap_rng_read_reg(int reg) { return __raw_readl(rng_base + reg); }
/* blocking notifier support */ int musb_notifier_call(struct notifier_block *nb, unsigned long event, void *unused) { struct musb *musb = container_of(nb, struct musb, nb); struct device *dev = musb->controller; struct musb_hdrc_platform_data *pdata = dev->platform_data; struct omap_musb_board_data *data = pdata->board_data; static int hostmode; u32 val; switch (event) { case USB_EVENT_ID: DBG(1, "ID GND\n"); /* configure musb into smartidle with wakeup enabled * smart standby mode. */ musb_writel(musb->mregs, OTG_FORCESTDBY, 0); val = musb_readl(musb->mregs, OTG_SYSCONFIG); if (cpu_is_omap44xx()) val |= SMARTIDLEWKUP | SMARTSTDBY | ENABLEWAKEUP; else val |= SMARTIDLE | SMARTSTDBY | ENABLEWAKEUP; musb_writel(musb->mregs, OTG_SYSCONFIG, val); if (data->interface_type == MUSB_INTERFACE_UTMI) { otg_init(musb->xceiv); hostmode = 1; musb_enable_vbus(musb); } val = __raw_readl(phymux_base + USBA0_OTG_CE_PAD1_USBA0_OTG_DP); val |= DP_WAKEUPENABLE; __raw_writel(val, phymux_base + USBA0_OTG_CE_PAD1_USBA0_OTG_DP); break; case USB_EVENT_VBUS: DBG(1, "VBUS Connect\n"); /* configure musb into smartidle with wakeup enabled * smart standby mode. */ musb_writel(musb->mregs, OTG_FORCESTDBY, 0); val = musb_readl(musb->mregs, OTG_SYSCONFIG); if (cpu_is_omap44xx()) val |= SMARTIDLEWKUP | SMARTSTDBY | ENABLEWAKEUP; else val |= SMARTIDLE | SMARTSTDBY | ENABLEWAKEUP; musb_writel(musb->mregs, OTG_SYSCONFIG, val); if (data->interface_type == MUSB_INTERFACE_UTMI) { otg_init(musb->xceiv); if (!hostmode) { /* Enable VBUS Valid, AValid. Clear SESSEND.*/ __raw_writel(IDDIG | AVALID | VBUSVALID, ctrl_base + USBOTGHS_CONTROL); } } break; case USB_EVENT_NONE: DBG(1, "VBUS Disconnect\n"); if (data->interface_type == MUSB_INTERFACE_UTMI) { /* enable this clock because in suspend interrupt * handler phy clocks are disabled. If phy clocks are * not enabled then DISCONNECT interrupt will not be * reached to mentor */ otg_set_clk(musb->xceiv, 1); __raw_writel(SESSEND | IDDIG, ctrl_base + USBOTGHS_CONTROL); if (musb->xceiv->set_vbus) otg_set_vbus(musb->xceiv, 0); otg_shutdown(musb->xceiv); } hostmode = 0; /* configure in force idle/ standby */ musb_writel(musb->mregs, OTG_FORCESTDBY, 1); val = musb_readl(musb->mregs, OTG_SYSCONFIG); val &= ~(SMARTIDLEWKUP | SMARTSTDBY | ENABLEWAKEUP); val |= FORCEIDLE | FORCESTDBY; musb_writel(musb->mregs, OTG_SYSCONFIG, val); val = __raw_readl(phymux_base + USBA0_OTG_CE_PAD1_USBA0_OTG_DP); val &= ~DP_WAKEUPENABLE; __raw_writel(val, phymux_base + USBA0_OTG_CE_PAD1_USBA0_OTG_DP); break; default: DBG(1, "ID float\n"); return NOTIFY_DONE; } return NOTIFY_OK; }
static int __exynos5_mipi_phy_control(int id, bool on, u32 reset) { int ret = 0; static DEFINE_SPINLOCK(lock); void __iomem *pmu_addr; void __iomem *cmu_addr; unsigned long flags; u32 cfg; spin_lock_irqsave(&lock, flags); if (reset == S5P_MIPI_DPHY_SRESETN) { if (on) { switch(id) { case 0: ++dphy_m4s4_status; if (dphy_m4s4_status == 1) { cmu_addr = EXYNOS7420_VA_SYSREG + 0x2930; cfg = __raw_readl(cmu_addr); /* enable reset -> release reset */ cfg &= ~(1 << 0); __raw_writel(cfg, cmu_addr); cfg |= (1 << 0); __raw_writel(cfg, cmu_addr); pmu_addr = S7P_MIPI_DPHY_CONTROL(0); __raw_writel(S5P_MIPI_DPHY_ENABLE, pmu_addr); } break; case 1: cmu_addr = EXYNOS7420_VA_SYSREG + 0x2930; cfg = __raw_readl(cmu_addr); cfg &= ~(1 << 8); __raw_writel(cfg, cmu_addr); cfg |= (1 << 8); __raw_writel(cfg, cmu_addr); pmu_addr = S7P_MIPI_DPHY_CONTROL(2); __raw_writel(S5P_MIPI_DPHY_ENABLE, pmu_addr); break; case 2: cmu_addr = EXYNOS7420_VA_SYSREG + 0x2930; cfg = __raw_readl(cmu_addr); cfg &= ~(1 << 12); __raw_writel(cfg, cmu_addr); cfg |= (1 << 12); __raw_writel(cfg, cmu_addr); pmu_addr = S7P_MIPI_DPHY_CONTROL(3); __raw_writel(S5P_MIPI_DPHY_ENABLE, pmu_addr); break; default: pr_err("id(%d) is invalid", id); ret = -EINVAL; goto p_err; break; } } else { switch(id) { case 0: --dphy_m4s4_status; if (dphy_m4s4_status == 0) { cmu_addr = EXYNOS7420_VA_SYSREG + 0x2930; cfg = __raw_readl(cmu_addr); cfg &= ~(1 << 0); __raw_writel(cfg, cmu_addr); cfg |= (1 << 0); __raw_writel(cfg, cmu_addr); pmu_addr = S7P_MIPI_DPHY_CONTROL(0); __raw_writel(0, pmu_addr); } break; case 1: cmu_addr = EXYNOS7420_VA_SYSREG + 0x2930; cfg = __raw_readl(cmu_addr); cfg &= ~(1 << 8); __raw_writel(cfg, cmu_addr); cfg |= (1 << 8); __raw_writel(cfg, cmu_addr); pmu_addr = S7P_MIPI_DPHY_CONTROL(2); __raw_writel(0, pmu_addr); break; case 2: cmu_addr = EXYNOS7420_VA_SYSREG + 0x2930; cfg = __raw_readl(cmu_addr); cfg &= ~(1 << 12); __raw_writel(cfg, cmu_addr); cfg |= (1 << 12); __raw_writel(cfg, cmu_addr); pmu_addr = S7P_MIPI_DPHY_CONTROL(3); __raw_writel(0, pmu_addr); break; default: pr_err("id(%d) is invalid", id); ret = -EINVAL; goto p_err; break; } } } else { /* reset == S5P_MIPI_DPHY_MRESETN */ if (on) { switch(id) { case 0: ++dphy_m4s4_status; if (dphy_m4s4_status == 1) { cmu_addr = EXYNOS7420_VA_SYSREG + 0x2930; cfg = __raw_readl(cmu_addr); cfg &= ~(1 << 0); __raw_writel(cfg, cmu_addr); cfg |= (1 << 0); __raw_writel(cfg, cmu_addr); pmu_addr = S7P_MIPI_DPHY_CONTROL(0); __raw_writel(S5P_MIPI_DPHY_ENABLE, pmu_addr); } break; case 1: cmu_addr = EXYNOS7420_VA_SYSREG + 0x2930; cfg = __raw_readl(cmu_addr); cfg &= ~(1 << 4); __raw_writel(cfg, cmu_addr); cfg |= (1 << 4); __raw_writel(cfg, cmu_addr); pmu_addr = S7P_MIPI_DPHY_CONTROL(1); __raw_writel(S5P_MIPI_DPHY_ENABLE, pmu_addr); break; default: pr_err("id(%d) is invalid", id); ret = -EINVAL; goto p_err; break; } } else { /* off */ switch(id) { case 0: --dphy_m4s4_status; if (dphy_m4s4_status == 0) { cmu_addr = EXYNOS7420_VA_SYSREG + 0x2930; cfg = __raw_readl(cmu_addr); cfg &= ~(1 << 0); __raw_writel(cfg, cmu_addr); cfg |= (1 << 0); __raw_writel(cfg, cmu_addr); pmu_addr = S7P_MIPI_DPHY_CONTROL(0); __raw_writel(0, pmu_addr); } break; case 1: cmu_addr = EXYNOS7420_VA_SYSREG + 0x2930; cfg = __raw_readl(cmu_addr); cfg &= ~(1 << 4); __raw_writel(cfg, cmu_addr); cfg |= (1 << 4); __raw_writel(cfg, cmu_addr); pmu_addr = S7P_MIPI_DPHY_CONTROL(1); __raw_writel(0, pmu_addr); break; default: pr_err("id(%d) is invalid", id); ret = -EINVAL; goto p_err; break; } } } p_err: spin_unlock_irqrestore(&lock, flags); return ret; }
static int __init b15_rac_init(void) { struct device_node *dn, *cpu_dn; int ret = 0, cpu; u32 reg, en_mask = 0; dn = of_find_compatible_node(NULL, NULL, "brcm,brcmstb-cpu-biu-ctrl"); if (!dn) return -ENODEV; if (WARN(num_possible_cpus() > 4, "RAC only supports 4 CPUs\n")) goto out; b15_rac_base = of_iomap(dn, 0); if (!b15_rac_base) { pr_err("failed to remap BIU control base\n"); ret = -ENOMEM; goto out; } cpu_dn = of_get_cpu_node(0, NULL); if (!cpu_dn) { ret = -ENODEV; goto out; } if (of_device_is_compatible(cpu_dn, "brcm,brahma-b15")) rac_flush_offset = B15_RAC_FLUSH_REG; else if (of_device_is_compatible(cpu_dn, "brcm,brahma-b53")) rac_flush_offset = B53_RAC_FLUSH_REG; else { pr_err("Unsupported CPU\n"); of_node_put(cpu_dn); ret = -EINVAL; goto out; } of_node_put(cpu_dn); ret = register_reboot_notifier(&b15_rac_reboot_nb); if (ret) { pr_err("failed to register reboot notifier\n"); iounmap(b15_rac_base); goto out; } if (IS_ENABLED(CONFIG_HOTPLUG_CPU)) { ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DEAD, "arm/cache-b15-rac:dead", NULL, b15_rac_dead_cpu); if (ret) goto out_unmap; ret = cpuhp_setup_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DYING, "arm/cache-b15-rac:dying", NULL, b15_rac_dying_cpu); if (ret) goto out_cpu_dead; } if (IS_ENABLED(CONFIG_PM_SLEEP)) register_syscore_ops(&b15_rac_syscore_ops); spin_lock(&rac_lock); reg = __raw_readl(b15_rac_base + RAC_CONFIG0_REG); for_each_possible_cpu(cpu) en_mask |= ((1 << RACPREFDATA_SHIFT) << (cpu * RAC_CPU_SHIFT)); WARN(reg & en_mask, "Read-ahead cache not previously disabled\n"); b15_rac_enable(); set_bit(RAC_ENABLED, &b15_rac_flags); spin_unlock(&rac_lock); pr_info("Broadcom Brahma-B15 readahead cache at: 0x%p\n", b15_rac_base + RAC_CONFIG0_REG); goto out; out_cpu_dead: cpuhp_remove_state_nocalls(CPUHP_AP_ARM_CACHE_B15_RAC_DYING); out_unmap: unregister_reboot_notifier(&b15_rac_reboot_nb); iounmap(b15_rac_base); out: of_node_put(dn); return ret; }
static inline u32 hecc_read(struct ti_hecc_priv *priv, int reg) { return __raw_readl(priv->base + reg); }
static int asrc_set_process_configuration(enum asrc_pair_index index, int input_sample_rate, int output_sample_rate) { int i = 0, j = 0; unsigned long reg; switch (input_sample_rate) { case 5512: i = 0; case 8000: i = 1; break; case 11025: i = 2; break; case 16000: i = 3; break; case 22050: i = 4; break; case 32000: i = 5; break; case 44100: i = 6; break; case 48000: i = 7; break; case 64000: i = 8; break; case 88200: i = 9; break; case 96000: i = 10; break; case 176400: i = 11; break; case 192000: i = 12; break; default: return -1; } switch (output_sample_rate) { case 32000: j = 0; break; case 44100: j = 1; break; case 48000: j = 2; break; case 64000: j = 3; break; case 88200: j = 4; break; case 96000: j = 5; break; case 176400: j = 6; break; case 192000: j = 7; break; default: return -1; } reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCFG_REG); reg &= ~(0x0f << (6 + (index << 2))); reg |= ((asrc_process_table[i][j][0] << (6 + (index << 2))) | (asrc_process_table[i][j][1] << (8 + (index << 2)))); __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCFG_REG); return 0; }
static u32 ar231x_reset_readl(void) { return __raw_readl(reset_base); }
int asrc_config_pair(struct asrc_config *config) { int err = 0; int reg, tmp, channel_num; unsigned long lock_flags; /* Set the channel number */ reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCNCR_REG); spin_lock_irqsave(&data_lock, lock_flags); g_asrc_data->asrc_pair[config->pair].chn_num = config->channel_num; spin_unlock_irqrestore(&data_lock, lock_flags); reg &= ~((0xFFFFFFFF >> (32 - mxc_asrc_data->channel_bits)) << (mxc_asrc_data->channel_bits * config->pair)); if (mxc_asrc_data->channel_bits > 3) channel_num = config->channel_num; else channel_num = (config->channel_num + 1) / 2; tmp = channel_num << (mxc_asrc_data->channel_bits * config->pair); reg |= tmp; __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCNCR_REG); /* Set the clock source */ reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCSR_REG); tmp = ~(0x0f << (config->pair << 2)); reg &= tmp; tmp = ~(0x0f << (12 + (config->pair << 2))); reg &= tmp; reg |= ((config->inclk << (config->pair << 2)) | (config-> outclk << (12 + (config-> pair << 2)))); __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCSR_REG); /* default setting */ /* automatic selection for processing mode */ reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); reg |= (1 << (20 + config->pair)); reg &= ~(1 << (14 + (config->pair << 1))); __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRRA_REG); reg &= 0xffbfffff; __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRRA_REG); reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); reg = reg & (~(1 << 23)); __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); /* Default Clock Divider Setting */ reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); if (config->pair == ASRC_PAIR_A) { reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); reg &= 0xfc0fc0; /* Input Part */ if ((config->inclk & 0x0f) == INCLK_SPDIF_RX) reg |= 7 << AICPA; else if ((config->inclk & 0x0f) == INCLK_SPDIF_TX) reg |= 6 << AICPA; else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) { tmp = asrc_get_asrck_clock_divider(config-> input_sample_rate); reg |= tmp << AICPA; } else { if (config->word_width == 16 || config->word_width == 8) reg |= 5 << AICPA; else if (config->word_width == 32 || config->word_width == 24) reg |= 6 << AICPA; else err = -EFAULT; } /* Output Part */ if ((config->outclk & 0x0f) == OUTCLK_SPDIF_RX) reg |= 7 << AOCPA; else if ((config->outclk & 0x0f) == OUTCLK_SPDIF_TX) reg |= 6 << AOCPA; else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) { tmp = asrc_get_asrck_clock_divider(config-> output_sample_rate); reg |= tmp << AOCPA; } else { if (config->word_width == 16 || config->word_width == 8) reg |= 5 << AOCPA; else if (config->word_width == 32 || config->word_width == 24) reg |= 6 << AOCPA; else err = -EFAULT; } __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR1_REG); } else if (config->pair == ASRC_PAIR_B) { reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR1_REG); reg &= 0x03f03f; /* Input Part */ if ((config->inclk & 0x0f) == INCLK_SPDIF_RX) reg |= 7 << AICPB; else if ((config->inclk & 0x0f) == INCLK_SPDIF_TX) reg |= 6 << AICPB; else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) { tmp = asrc_get_asrck_clock_divider(config-> input_sample_rate); reg |= tmp << AICPB; } else { if (config->word_width == 16 || config->word_width == 8) reg |= 5 << AICPB; else if (config->word_width == 32 || config->word_width == 24) reg |= 6 << AICPB; else err = -EFAULT; } /* Output Part */ if ((config->outclk & 0x0f) == OUTCLK_SPDIF_RX) reg |= 7 << AOCPB; else if ((config->outclk & 0x0f) == OUTCLK_SPDIF_TX) reg |= 6 << AOCPB; else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) { tmp = asrc_get_asrck_clock_divider(config-> output_sample_rate); reg |= tmp << AOCPB; } else { if (config->word_width == 16 || config->word_width == 8) reg |= 5 << AOCPB; else if (config->word_width == 32 || config->word_width == 24) reg |= 6 << AOCPB; else err = -EFAULT; } __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR1_REG); } else { reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCDR2_REG); reg &= 0; /* Input Part */ if ((config->inclk & 0x0f) == INCLK_SPDIF_RX) reg |= 7 << AICPC; else if ((config->inclk & 0x0f) == INCLK_SPDIF_TX) reg |= 6 << AICPC; else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) { tmp = asrc_get_asrck_clock_divider(config-> input_sample_rate); reg |= tmp << AICPC; } else { if (config->word_width == 16 || config->word_width == 8) reg |= 5 << AICPC; else if (config->word_width == 32 || config->word_width == 24) reg |= 6 << AICPC; else err = -EFAULT; } /* Output Part */ if ((config->outclk & 0x0f) == OUTCLK_SPDIF_RX) reg |= 7 << AOCPC; else if ((config->outclk & 0x0f) == OUTCLK_SPDIF_TX) reg |= 6 << AOCPC; else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) { tmp = asrc_get_asrck_clock_divider(config-> output_sample_rate); reg |= tmp << AOCPC; } else { if (config->word_width == 16 || config->word_width == 8) reg |= 5 << AOCPC; else if (config->word_width == 32 || config->word_width == 24) reg |= 6 << AOCPC; else err = -EFAULT; } __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCDR2_REG); } /* check whether ideal ratio is a must */ if ((config->inclk & 0x0f) == INCLK_NONE) { reg = __raw_readl(asrc_vrt_base_addr + ASRC_ASRCTR_REG); reg &= ~(1 << (20 + config->pair)); reg |= (0x03 << (13 + (config->pair << 1))); __raw_writel(reg, asrc_vrt_base_addr + ASRC_ASRCTR_REG); err = asrc_set_clock_ratio(config->pair, config->input_sample_rate, config->output_sample_rate); if (err < 0) return err; err = asrc_set_process_configuration(config->pair, config->input_sample_rate, config-> output_sample_rate); if (err < 0) return err; } else if ((config->inclk & 0x0f) == INCLK_ASRCK1_CLK) { if (config->input_sample_rate == 44100 || config->input_sample_rate == 88200) { pr_info ("ASRC core clock cann't support sample rate %d\n", config->input_sample_rate); err = -EFAULT; } } else if ((config->outclk & 0x0f) == OUTCLK_ASRCK1_CLK) { if (config->output_sample_rate == 44100 || config->output_sample_rate == 88200) { pr_info ("ASRC core clock cann't support sample rate %d\n", config->input_sample_rate); err = -EFAULT; } } return err; }
static int dryice_rtc_probe(struct platform_device *pdev) { struct resource *res; struct imxdi_dev *imxdi; int rc; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -ENODEV; imxdi = devm_kzalloc(&pdev->dev, sizeof(*imxdi), GFP_KERNEL); if (!imxdi) return -ENOMEM; imxdi->pdev = pdev; if (!devm_request_mem_region(&pdev->dev, res->start, resource_size(res), pdev->name)) return -EBUSY; imxdi->ioaddr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); if (imxdi->ioaddr == NULL) return -ENOMEM; imxdi->irq = platform_get_irq(pdev, 0); if (imxdi->irq < 0) return imxdi->irq; init_waitqueue_head(&imxdi->write_wait); INIT_WORK(&imxdi->work, dryice_work); mutex_init(&imxdi->write_mutex); imxdi->clk = clk_get(&pdev->dev, NULL); if (IS_ERR(imxdi->clk)) return PTR_ERR(imxdi->clk); clk_enable(imxdi->clk); __raw_writel(0, imxdi->ioaddr + DIER); rc = devm_request_irq(&pdev->dev, imxdi->irq, dryice_norm_irq, IRQF_SHARED, pdev->name, imxdi); if (rc) { dev_warn(&pdev->dev, "interrupt not available.\n"); goto err; } if (__raw_readl(imxdi->ioaddr + DSR) & DSR_NVF) { rc = di_write_wait(imxdi, DSR_NVF | DSR_SVF, DSR); if (rc) goto err; } rc = di_write_wait(imxdi, DCAMR_UNSET, DCAMR); if (rc) goto err; rc = di_write_wait(imxdi, 0, DCALR); if (rc) goto err; if (__raw_readl(imxdi->ioaddr + DSR) & DSR_CAF) { rc = di_write_wait(imxdi, DSR_CAF, DSR); if (rc) goto err; } /* the timer won't count if it has never been written to */ if (__raw_readl(imxdi->ioaddr + DTCMR) == 0) { rc = di_write_wait(imxdi, 0, DTCMR); if (rc) goto err; } if (!(__raw_readl(imxdi->ioaddr + DCR) & DCR_TCE)) { rc = di_write_wait(imxdi, __raw_readl(imxdi->ioaddr + DCR) | DCR_TCE, DCR); if (rc) goto err; } platform_set_drvdata(pdev, imxdi); imxdi->rtc = rtc_device_register(pdev->name, &pdev->dev, &dryice_rtc_ops, THIS_MODULE); if (IS_ERR(imxdi->rtc)) { rc = PTR_ERR(imxdi->rtc); goto err; } return 0; err: clk_disable(imxdi->clk); clk_put(imxdi->clk); return rc; }
static inline u32 __omap_prcm_read(void __iomem *base, s16 module, u16 reg) { BUG_ON(!base); return __raw_readl(base + module + reg); }