void __init plat_mem_setup(void)
{
char **envp = (char **) KSEG1ADDR(fw_arg2);
ioport_resource.start = IOPORT_RESOURCE_START;
ioport_resource.end = IOPORT_RESOURCE_END;
iomem_resource.start = IOMEM_RESOURCE_START;
iomem_resource.end = IOMEM_RESOURCE_END;
set_io_port_base((unsigned long) KSEG1);
while (*envp) {
char *e = (char *)KSEG1ADDR(*envp);
if (!strncmp(e, "memsize=", 8)) {
e += 8;
if (strict_strtoul(e, 0, &physical_memsize))
pr_warn("bad memsize specified\n");
}
envp++;
}
physical_memsize *= 1024 * 1024;
add_memory_region(0x00000000, physical_memsize, BOOT_MEM_RAM);
}
void __init prom_init(void)
{
int argc = fw_arg0;
char **argv = (char **) fw_arg1;
setup_prom_vectors();
if (current_cpu_data.cputype == CPU_R5000) {
printk(KERN_INFO "LASAT 200 board\n");
mips_machtype = MACH_LASAT_200;
lasat_ndelay_divider = LASAT_200_DIVIDER;
} else {
printk(KERN_INFO "LASAT 100 board\n");
mips_machtype = MACH_LASAT_100;
lasat_ndelay_divider = LASAT_100_DIVIDER;
}
at93c = &at93c_defs[mips_machtype];
lasat_init_board_info(); /* Read info from EEPROM */
/* Get the command line */
if (argc > 0) {
strncpy(arcs_cmdline, argv[0], CL_SIZE-1);
arcs_cmdline[CL_SIZE-1] = '\0';
}
/* Set the I/O base address */
set_io_port_base(KSEG1);
/* Set memory regions */
ioport_resource.start = 0;
ioport_resource.end = 0xffffffff; /* Wrong, fixme. */
add_memory_region(0, lasat_board_info.li_memsize, BOOT_MEM_RAM);
}
void __init prom_init(void)
{
struct ddr_ram __iomem *ddr;
phys_t memsize;
phys_t ddrbase;
ddr = ioremap_nocache(ddr_reg[0].start,
ddr_reg[0].end - ddr_reg[0].start);
if (!ddr) {
printk(KERN_ERR "Unable to remap DDR register\n");
return;
}
ddrbase = (phys_t)&ddr->ddrbase;
memsize = (phys_t)&ddr->ddrmask;
memsize = 0 - memsize;
prom_setup_cmdline();
/* give all RAM to boot allocator,
* except for the first 0x400 and the last 0x200 bytes */
add_memory_region(ddrbase + 0x400, memsize - 0x600, BOOT_MEM_RAM);
}
void __init plat_mem_setup(void)
{
volatile u32 * const boot_ocd_base = (u32 *) 0xbf7fc000;
/* Announce RAM to system */
add_memory_region(0x00000000, memsize, BOOT_MEM_RAM);
/* Set up the peripheral address map */
*(boot_ocd_base + (LKB9 / sizeof(u32))) = 0;
*(boot_ocd_base + (LKB10 / sizeof(u32))) = 0;
*(boot_ocd_base + (LKB11 / sizeof(u32))) = 0;
*(boot_ocd_base + (LKB12 / sizeof(u32))) = 0;
wmb();
*(boot_ocd_base + (LKB0 / sizeof(u32))) = EXCITE_PHYS_OCD >> 4;
wmb();
ocd_writel((EXCITE_PHYS_TITAN >> 4) | 0x1UL, LKB5);
ocd_writel(((EXCITE_SIZE_TITAN >> 4) & 0x7fffff00) - 0x100, LKM5);
ocd_writel((EXCITE_PHYS_SCRAM >> 4) | 0x1UL, LKB13);
ocd_writel(((EXCITE_SIZE_SCRAM >> 4) & 0xffffff00) - 0x100, LKM13);
/* Local bus slot #0 */
ocd_writel(0x00040510, LDP0);
ocd_writel((EXCITE_PHYS_BOOTROM >> 4) | 0x1UL, LKB9);
ocd_writel(((EXCITE_SIZE_BOOTROM >> 4) & 0x03ffff00) - 0x100, LKM9);
/* Local bus slot #2 */
ocd_writel(0x00000330, LDP2);
ocd_writel((EXCITE_PHYS_FPGA >> 4) | 0x1, LKB11);
ocd_writel(((EXCITE_SIZE_FPGA >> 4) - 0x100) & 0x03ffff00, LKM11);
/* Local bus slot #3 */
ocd_writel(0x00123413, LDP3);
ocd_writel((EXCITE_PHYS_NAND >> 4) | 0x1, LKB12);
ocd_writel(((EXCITE_SIZE_NAND >> 4) - 0x100) & 0x03ffff00, LKM12);
}
char * __init machine_specific_memory_setup(void)
{
char *who;
who = "NOT VOYAGER";
if(voyager_level == 5) {
__u32 addr, length;
int i;
who = "Voyager-SUS";
e820.nr_map = 0;
for(i=0; voyager_memory_detect(i, &addr, &length); i++) {
add_memory_region(addr, length, E820_RAM);
}
return who;
} else if(voyager_level == 4) {
__u32 tom;
__u16 catbase = inb(VOYAGER_SSPB_RELOCATION_PORT)<<8;
/* select the DINO config space */
outb(VOYAGER_DINO, VOYAGER_CAT_CONFIG_PORT);
/* Read DINO top of memory register */
tom = ((inb(catbase + 0x4) & 0xf0) << 16)
+ ((inb(catbase + 0x5) & 0x7f) << 24);
if(inb(catbase) != VOYAGER_DINO) {
printk(KERN_ERR "Voyager: Failed to get DINO for L4, setting tom to EXT_MEM_K\n");
tom = (EXT_MEM_K)<<10;
}
who = "Voyager-TOM";
add_memory_region(0, 0x9f000, E820_RAM);
/* map from 1M to top of memory */
add_memory_region(1*1024*1024, tom - 1*1024*1024, E820_RAM);
/* FIXME: Should check the ASICs to see if I need to
* take out the 8M window. Just do it at the moment
* */
add_memory_region(8*1024*1024, 8*1024*1024, E820_RESERVED);
return who;
}
who = "BIOS-e820";
/*
* Try to copy the BIOS-supplied E820-map.
*
* Otherwise fake a memory map; one section from 0k->640k,
* the next section from 1mb->appropriate_mem_k
*/
sanitize_e820_map(E820_MAP, &E820_MAP_NR);
if (copy_e820_map(E820_MAP, E820_MAP_NR) < 0) {
unsigned long mem_size;
/* compare results from other methods and take the greater */
if (ALT_MEM_K < EXT_MEM_K) {
mem_size = EXT_MEM_K;
who = "BIOS-88";
} else {
mem_size = ALT_MEM_K;
who = "BIOS-e801";
}
e820.nr_map = 0;
add_memory_region(0, LOWMEMSIZE(), E820_RAM);
add_memory_region(HIGH_MEMORY, mem_size << 10, E820_RAM);
}
return who;
}
void __init momenco_ocelot_c_setup(void)
{
unsigned int tmpword;
board_time_init = momenco_time_init;
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
_machine_power_off = momenco_ocelot_power_off;
/*
* initrd_start = (ulong)ocelot_initrd_start;
* initrd_end = (ulong)ocelot_initrd_start + (ulong)ocelot_initrd_size;
* initrd_below_start_ok = 1;
*/
/* do handoff reconfiguration */
PMON_v2_setup();
/* shut down ethernet ports, just to be sure our memory doesn't get
* corrupted by random ethernet traffic.
*/
MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
do {}
while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
while (MV_READ_DATA(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
do {}
while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
while (MV_READ_DATA(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1), MV_READ_DATA(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
/* Turn off the Bit-Error LED */
OCELOT_FPGA_WRITE(0x80, CLR);
tmpword = OCELOT_FPGA_READ(BOARDREV);
#ifdef CONFIG_CPU_SR71000
if (tmpword < 26)
printk("Momenco Ocelot-CS: Board Assembly Rev. %c\n",
'A'+tmpword);
else
printk("Momenco Ocelot-CS: Board Assembly Revision #0x%x\n",
tmpword);
#else
if (tmpword < 26)
printk("Momenco Ocelot-C: Board Assembly Rev. %c\n",
'A'+tmpword);
else
printk("Momenco Ocelot-C: Board Assembly Revision #0x%x\n",
tmpword);
#endif
tmpword = OCELOT_FPGA_READ(FPGA_REV);
printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
tmpword = OCELOT_FPGA_READ(RESET_STATUS);
printk("Reset reason: 0x%x\n", tmpword);
switch (tmpword) {
case 0x1:
printk(" - Power-up reset\n");
break;
case 0x2:
printk(" - Push-button reset\n");
break;
case 0x4:
printk(" - cPCI bus reset\n");
break;
case 0x8:
printk(" - Watchdog reset\n");
break;
case 0x10:
printk(" - Software reset\n");
break;
default:
printk(" - Unknown reset cause\n");
}
reset_reason = tmpword;
OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
tmpword = OCELOT_FPGA_READ(CPCI_ID);
printk("cPCI ID register: 0x%02x\n", tmpword);
printk(" - Slot number: %d\n", tmpword & 0x1f);
printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
printk("Board Status register: 0x%02x\n", tmpword);
printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
printk(" - L3 Cache size: %d MiB\n", (1<<((tmpword&12) >> 2))&~1);
printk(" - SDRAM size: %d MiB\n", 1<<(6+(tmpword&3)));
switch(tmpword &3) {
case 3:
/* 512MiB */
add_memory_region(0x0, 0x200<<20, BOOT_MEM_RAM);
break;
case 2:
/* 256MiB */
add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
break;
case 1:
/* 128MiB */
add_memory_region(0x0, 0x80<<20, BOOT_MEM_RAM);
break;
case 0:
/* 1GiB -- needs CONFIG_HIGHMEM */
add_memory_region(0x0, 0x400<<20, BOOT_MEM_RAM);
break;
}
}
/* Do basic initialization */
void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec)
{
unsigned long mem_size,reg_mem;
int cnt=1;
unsigned long mempos;
unsigned long memmeg;
unsigned short save_dword;
unsigned long flags;
#ifdef CONFIG_RTK_MTD_ROOT
#ifdef CONFIG_INIT_SINGLE
strcat(arcs_cmdline,"root=/dev/mtd1 console=0 single noisapnp pci=nobios");
#else
strcat(arcs_cmdline,"root=/dev/mtd1 console=0 noisapnp pci=nobios");
#endif
#else
#ifdef CONFIG_INIT_SINGLE
strcat(arcs_cmdline,"root=/dev/ram console=0 ramdisk_start=0 single noisapnp pci=nobios");
#else
strcat(arcs_cmdline,"root=/dev/ram console=0 ramdisk_start=0 noisapnp pci=nobios");
#endif
#endif
mips_machgroup = MACH_GROUP_PHILIPS;
mips_machtype = MACH_PHILIPS_NINO;
local_irq_save(flags);
//Check for maximum RAM openned in MCR
reg_mem = (*( volatile unsigned long*) 0xbd011000) & 0x30000000;
reg_mem >>=24;
detect_ram_sequence[0] = reg_mem;
//If nothing in MCR we assume max available SDRAM
if (!reg_mem)reg_mem=64;
detect_ram_sequence[1] = reg_mem;
//Special test to be sure in RAM capacity (in some situations there's 16M in MCR and 8M real RAM)
for(memmeg=4;memmeg<reg_mem;memmeg+=4){
mempos = 0xa0000000L + memmeg * 0x100000;
save_dword = *(volatile unsigned short *)mempos;
*(volatile unsigned short *)mempos = (unsigned short)0xABCD;
if (*(volatile unsigned short *)mempos != (unsigned short)0xABCD){
*(volatile unsigned short *)mempos = save_dword;
break;
}
*(volatile unsigned short *)mempos = (unsigned short)0xDCBA;
if (*(volatile unsigned short *)mempos != (unsigned short)0xDCBA){
*(volatile unsigned short *)mempos = save_dword;
break;
}
*(volatile unsigned short *)mempos = save_dword;
}
mem_size = memmeg << 20;
//workaround for non correct memory sizes detect for some devices
if (reg_mem != memmeg)
{
printk("Workaround for:");
//workaround for 16bit 16Mbyte RAM devices (Zyxel P330W)
if (reg_mem == 32 && memmeg == 20)
{
printk("Zyxel P330W v.2 and others 16RAM 16Bit devices");
reg_mem = 16;
memmeg = 16;
mem_size = 16777216;
}
}
detect_ram_sequence[2] = memmeg;
detect_ram_sequence[3] = mem_size;
local_irq_restore(flags);
totall_system_memory_detected = memmeg;
add_memory_region(0, mem_size, BOOT_MEM_RAM);
}
void __init prom_meminit(void)
{
add_memory_region(NVT_72558_MBASE, 0x4000000, BOOT_MEM_RAM);
}
void __init early_init_dt_add_memory_arch(u64 base, u64 size)
{
return add_memory_region(base, size, BOOT_MEM_RAM);
}
/*
* Make a e820 memory map
*/
void
e820_map_from_efi_map (struct e820_entry *e820_map,
int *e820_nr_map,
grub_efi_memory_descriptor_t *memory_map,
grub_efi_uintn_t desc_size,
grub_efi_uintn_t memory_map_size)
{
grub_efi_memory_descriptor_t *desc;
unsigned long long start = 0;
unsigned long long end = 0;
unsigned long long size = 0;
grub_efi_memory_descriptor_t *memory_map_end;
memory_map_end = NEXT_MEMORY_DESCRIPTOR (memory_map, memory_map_size);
*e820_nr_map = 0;
for (desc = memory_map;
desc < memory_map_end;
desc = NEXT_MEMORY_DESCRIPTOR (desc, desc_size))
{
switch (desc->type)
{
case GRUB_EFI_ACPI_RECLAIM_MEMORY:
add_memory_region (e820_map, e820_nr_map,
desc->physical_start, desc->num_pages << 12,
E820_ACPI);
break;
case GRUB_EFI_RUNTIME_SERVICES_CODE:
case GRUB_EFI_RUNTIME_SERVICES_DATA:
case GRUB_EFI_RESERVED_MEMORY_TYPE:
case GRUB_EFI_MEMORY_MAPPED_IO:
case GRUB_EFI_MEMORY_MAPPED_IO_PORT_SPACE:
case GRUB_EFI_UNUSABLE_MEMORY:
case GRUB_EFI_PAL_CODE:
add_memory_region (e820_map, e820_nr_map,
desc->physical_start, desc->num_pages << 12,
E820_RESERVED);
break;
case GRUB_EFI_LOADER_CODE:
case GRUB_EFI_LOADER_DATA:
case GRUB_EFI_BOOT_SERVICES_CODE:
case GRUB_EFI_BOOT_SERVICES_DATA:
case GRUB_EFI_CONVENTIONAL_MEMORY:
start = desc->physical_start;
size = desc->num_pages << 12;
end = start + size;
if (start < 0x100000ULL && end > 0xA0000ULL)
{
if (start < 0xA0000ULL)
add_memory_region (e820_map, e820_nr_map,
start, 0xA0000ULL-start,
E820_RAM);
if (end <= 0x100000ULL)
continue;
start = 0x100000ULL;
size = end - start;
}
add_memory_region (e820_map, e820_nr_map,
start, size, E820_RAM);
break;
case GRUB_EFI_ACPI_MEMORY_NVS:
add_memory_region (e820_map, e820_nr_map,
desc->physical_start, desc->num_pages << 12,
E820_NVS);
break;
}
}
}
void __init plat_setup(void)
{
unsigned int tmpword;
board_time_init = momenco_time_init;
_machine_restart = momenco_jaguar_restart;
_machine_halt = momenco_jaguar_halt;
_machine_power_off = momenco_jaguar_power_off;
/*
* initrd_start = (ulong)jaguar_initrd_start;
* initrd_end = (ulong)jaguar_initrd_start + (ulong)jaguar_initrd_size;
* initrd_below_start_ok = 1;
*/
wire_stupidity_into_tlb();
/*
* shut down ethernet ports, just to be sure our memory doesn't get
* corrupted by random ethernet traffic.
*/
MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2), 0xff << 8);
MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2), 0xff << 8);
while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(2)) & 0xff);
while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(2)) & 0xff);
MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2),
MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(2)) & ~1);
/* Turn off the Bit-Error LED */
JAGUAR_FPGA_WRITE(0x80, CLR);
tmpword = JAGUAR_FPGA_READ(BOARDREV);
if (tmpword < 26)
printk("Momentum Jaguar-ATX: Board Assembly Rev. %c\n",
'A'+tmpword);
else
printk("Momentum Jaguar-ATX: Board Assembly Revision #0x%x\n",
tmpword);
tmpword = JAGUAR_FPGA_READ(FPGA_REV);
printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
tmpword = JAGUAR_FPGA_READ(RESET_STATUS);
printk("Reset reason: 0x%x\n", tmpword);
switch (tmpword) {
case 0x1:
printk(" - Power-up reset\n");
break;
case 0x2:
printk(" - Push-button reset\n");
break;
case 0x8:
printk(" - Watchdog reset\n");
break;
case 0x10:
printk(" - JTAG reset\n");
break;
default:
printk(" - Unknown reset cause\n");
}
reset_reason = tmpword;
JAGUAR_FPGA_WRITE(0xff, RESET_STATUS);
tmpword = JAGUAR_FPGA_READ(BOARD_STATUS);
printk("Board Status register: 0x%02x\n", tmpword);
printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
/* 256MiB of RM9000x2 DDR */
// add_memory_region(0x0, 0x100<<20, BOOT_MEM_RAM);
/* 128MiB of MV-64340 DDR */
// add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
/* XXX Memory configuration should be picked up from PMON2k */
#ifdef CONFIG_JAGUAR_DMALOW
printk("Jaguar ATX DMA-low mode set\n");
add_memory_region(0x00000000, 0x08000000, BOOT_MEM_RAM);
add_memory_region(0x08000000, 0x10000000, BOOT_MEM_RAM);
#else
/* 128MiB of MV-64340 DDR RAM */
printk("Jaguar ATX DMA-low mode is not set\n");
add_memory_region(0x100<<20, 0x80<<20, BOOT_MEM_RAM);
#endif
#ifdef GEMDEBUG_TRACEBUFFER
{
unsigned int tbControl;
tbControl =
0 << 26 | /* post trigger delay 0 */
0x2 << 16 | /* sequential trace mode */
// 0x0 << 16 | /* non-sequential trace mode */
// 0xf << 4 | /* watchpoints disabled */
2 << 2 | /* armed */
2 ; /* interrupt disabled */
printk ("setting tbControl = %08lx\n", tbControl);
write_32bit_cp0_set1_register($22, tbControl);
__asm__ __volatile__(".set noreorder\n\t" \
"nop; nop; nop; nop; nop; nop;\n\t" \
"nop; nop; nop; nop; nop; nop;\n\t" \
".set reorder\n\t");
}
#endif
}
static inline void parse_cmdline_early(void)
{
char c = ' ', *to = command_line, *from = saved_command_line;
unsigned long start_at, mem_size;
int len = 0;
int usermem = 0;
#ifdef CONFIG_TANGOX
extern unsigned long em8xxx_kmem_start;
extern unsigned long em8xxx_kmem_size;
#ifdef CONFIG_TANGO3
extern unsigned long max_remap_size;
#endif
#endif
printk("Determined physical RAM map:\n");
print_memory_map();
for (;;) {
/*
* "mem=XXX[kKmM]" defines a memory region from
* 0 to <XXX>, overriding the determined size.
* "mem=XXX[KkmM]@YYY[KkmM]" defines a memory region from
* <YYY> to <YYY>+<XXX>, overriding the determined size.
*/
if (c == ' ' && !memcmp(from, "mem=", 4)) {
if (to != command_line)
to--;
/*
* If a user specifies memory size, we
* blow away any automatically generated
* size.
*/
if (usermem == 0) {
boot_mem_map.nr_map = 0;
usermem = 1;
}
mem_size = memparse(from + 4, &from);
if (*from == '@')
start_at = memparse(from + 1, &from);
else {
#ifdef CONFIG_TANGOX
start_at = CPHYSADDR(em8xxx_kmem_start);
#else
start_at = 0;
#endif
}
#ifdef CONFIG_TANGOX
if (start_at == CPHYSADDR(em8xxx_kmem_start)) {
unsigned long em8xxx_kmem_end;
#ifdef CONFIG_TANGO3
em8xxx_kmem_size = ((mem_size + em8xxx_kmem_start) & 0xfff00000) - em8xxx_kmem_start;
if (em8xxx_kmem_size > max_remap_size)
em8xxx_kmem_size = max_remap_size;
add_memory_region(start_at, em8xxx_kmem_size, BOOT_MEM_RAM);
em8xxx_kmem_end = KSEG1ADDR(em8xxx_kmem_start + em8xxx_kmem_size) - KSEG1ADDR(CPU_REMAP_SPACE);
/* Update information into LR_XENV2_RW */
xenv_set((void *)KSEG1ADDR(REG_BASE_cpu_block + LR_XENV2_RW), MAX_LR_XENV2_RW, XENV_LRRW_KERNEL_END, &em8xxx_kmem_end, 0, sizeof(em8xxx_kmem_end));
#else
memcfg_t *m = (memcfg_t *)KSEG1ADDR(MEM_BASE_dram_controller_0_alias + FM_MEMCFG);
em8xxx_kmem_size = ((mem_size + em8xxx_kmem_start) & 0xfff00000) - em8xxx_kmem_start;
add_memory_region(start_at, em8xxx_kmem_size, BOOT_MEM_RAM);
em8xxx_kmem_end = KSEG1ADDR(em8xxx_kmem_start + em8xxx_kmem_size) - KSEG1ADDR(MEM_BASE_dram_controller_0_alias);
m->kernel_end = em8xxx_kmem_end;
gen_memcfg_checksum(m);
#endif
} else {
/* We just add this blindly as the alignment can be wrong, use it as own risk */
add_memory_region(start_at, mem_size, BOOT_MEM_RAM);
}
#else
add_memory_region(start_at, mem_size, BOOT_MEM_RAM);
#endif
}
c = *(from++);
if (!c)
break;
if (CL_SIZE <= ++len)
break;
*(to++) = c;
}
*to = '\0';
if (usermem) {
printk("User-defined physical RAM map:\n");
print_memory_map();
}
}
void plat_mem_setup(void)
{
unsigned int ramsize = fw_arg1;
add_memory_region(0x0, ramsize, BOOT_MEM_RAM);
}
void __init plat_mem_setup(void)
{
add_memory_region(CM_SDRAM_BASE, (getMemorySize() - ADSL_SDRAM_IMAGE_SIZE), BOOT_MEM_RAM);
}
void __init plat_mem_setup(void)
{
add_memory_region(0x0, (memsize << 20), BOOT_MEM_RAM);
}
void __init
prom_init(void)
{
unsigned long mem, extmem = 0, off, data;
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BCM947XX;
off = (unsigned long)prom_init;
data = *(unsigned long *)prom_init;
/* Figure out memory size by finding aliases */
for (mem = (1 MB); mem < (128 MB); mem <<= 1) {
if (*(unsigned long *)(off + mem) == data)
break;
}
#if CONFIG_RAM_SIZE
{
unsigned long config_mem;
config_mem = CONFIG_RAM_SIZE * 0x100000;
if (config_mem < mem)
mem = config_mem;
}
#endif
#ifdef CONFIG_HIGHMEM
if (mem == 128 MB) {
early_tlb_init();
/* Add one temporary TLB entries to map SDRAM Region 2.
* Physical Virtual
* 0x80000000 0xc0000000 (1st: 256MB)
* 0x90000000 0xd0000000 (2nd: 256MB)
*/
add_tmptlb_entry(ENTRYLO(SI_SDRAM_R2),
ENTRYLO(SI_SDRAM_R2 + (256 MB)),
EXTVBASE, PM_256M);
off = EXTVBASE + __pa(off);
for (extmem = (128 MB); extmem < (512 MB); extmem <<= 1) {
if (*(unsigned long *)(off + extmem) == data)
break;
}
extmem -= mem;
/* Keep tlb entries back in consistent state */
early_tlb_init();
}
#endif /* CONFIG_HIGHMEM */
/* Ignoring the last page when ddr size is 128M. Cached
* accesses to last page is causing the processor to prefetch
* using address above 128M stepping out of the ddr address
* space.
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
mem -= 0x1000;
add_memory_region(SI_SDRAM_BASE, mem, BOOT_MEM_RAM);
#ifdef CONFIG_HIGHMEM
if (extmem) {
/* We should deduct 0x1000 from the second memory
* region, because of the fact that processor does prefetch.
* Now that we are deducting a page from second memory
* region, we could add the earlier deducted 4KB (from first bank)
* to the second region (the fact that 0x80000000 -> 0x88000000
* shadows 0x0 -> 0x8000000)
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
extmem -= 0x1000;
add_memory_region(SI_SDRAM_R2 + (128 MB) - 0x1000, extmem, BOOT_MEM_RAM);
}
#endif /* CONFIG_HIGHMEM */
}
static __init void prom_meminit(void)
{
u64 addr, size, type; /* regardless of 64BIT_PHYS_ADDR */
int mem_flags = 0;
unsigned int idx;
int rd_flag;
#ifdef CONFIG_BLK_DEV_INITRD
unsigned long initrd_pstart;
unsigned long initrd_pend;
initrd_pstart = CPHYSADDR(initrd_start);
initrd_pend = CPHYSADDR(initrd_end);
if (initrd_start &&
((initrd_pstart > MAX_RAM_SIZE)
|| (initrd_pend > MAX_RAM_SIZE))) {
panic("initrd out of addressable memory");
}
#endif /* INITRD */
for (idx = 0; cfe_enummem(idx, mem_flags, &addr, &size, &type) != CFE_ERR_NOMORE;
idx++) {
rd_flag = 0;
if (type == CFE_MI_AVAILABLE) {
/*
* See if this block contains (any portion of) the
* ramdisk
*/
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start) {
if ((initrd_pstart > addr) &&
(initrd_pstart < (addr + size))) {
add_memory_region(addr,
initrd_pstart - addr,
BOOT_MEM_RAM);
rd_flag = 1;
}
if ((initrd_pend > addr) &&
(initrd_pend < (addr + size))) {
add_memory_region(initrd_pend,
(addr + size) - initrd_pend,
BOOT_MEM_RAM);
rd_flag = 1;
}
}
#endif
if (!rd_flag) {
if (addr > MAX_RAM_SIZE)
continue;
if (addr+size > MAX_RAM_SIZE)
size = MAX_RAM_SIZE - (addr+size) + 1;
/*
* memcpy/__copy_user prefetch, which
* will cause a bus error for
* KSEG/KUSEG addrs not backed by RAM.
* Hence, reserve some padding for the
* prefetch distance.
*/
if (size > 512)
size -= 512;
add_memory_region(addr, size, BOOT_MEM_RAM);
}
board_mem_region_addrs[board_mem_region_count] = addr;
board_mem_region_sizes[board_mem_region_count] = size;
board_mem_region_count++;
if (board_mem_region_count ==
SIBYTE_MAX_MEM_REGIONS) {
/*
* Too many regions. Need to configure more
*/
while(1);
}
}
}
#ifdef CONFIG_BLK_DEV_INITRD
if (initrd_start) {
add_memory_region(initrd_pstart, initrd_pend - initrd_pstart,
BOOT_MEM_RESERVED);
}
#endif
}
void __init rbtx4938_prom_init(void)
{
add_memory_region(0, tx4938_get_mem_size(), BOOT_MEM_RAM);
txx9_sio_putchar_init(TX4938_SIO_REG(0) & 0xfffffffffULL);
}
/* prom_init() is called just after the cpu type is determined, from
init_arch(). */
void __init prom_init(int argc, char **arg)
{
mips_machgroup = MACH_GROUP_COBALT;
add_memory_region(0x0, argc & 0x7fffffff, BOOT_MEM_RAM);
}
void __init prom_init(int argc, const char **arg)
{
int hasBootParms = 0;
char msg[500];
char pmon_kargs[CL_SIZE];
uart_init(27000000);
//uart_puts("Inside prom_init\r\n");
/* Fill in platform information */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BCM93730;
/* Boot arguments can be put here */
/* Browse memory region to see if the boot rom deposits an argument there */
{
unsigned long sigAddr = KSEG1ADDR(LOAD_ADDRESS - BOOT_OPT_SIZE);
unsigned long mapAddr = (sigAddr & 0xFFFFF000);
unsigned long offset = sigAddr - mapAddr;
char* pMap;
char* p; /* Start address of bootParms including signature */
char* pBootParms; /* Actual start address of bootParms */
int len = 0;
int* plen;
//uart_puts( "Before ioremap\n");
//pMap = ioremap_nocache(mapAddr, 4096);
pMap = (char*) mapAddr;
p = &pMap[offset];
//uart_puts("After ioremap\n");
#ifdef DEBUG_PROM
sprintf(msg,"prom_init, mapped address %08lx at %08lx, pSig1=%08lx, sigAddr=%08lx\n",
mapAddr, (unsigned long) pMap, (unsigned long) p, sigAddr);
uart_puts(msg);
printBootArgRegion(p);
#endif
if (0 == memcmp(p, BOOT_OPT_SIG, 1+strlen(BOOT_OPT_SIG))) {
len += BOOT_OPT_LEN_OFFSET;
/* Rely on BOOT_OPT_LEN_OFFSET to place it at boundary */
plen = (int*) &p[len];
pBootParms = &p[len + sizeof(int)];
/* Making sure that we don't run over any bounds as there is no guarantee
* that COMMAND_LINE_SIZE <= BOOT_OPT_SIZE minus the sig
*/
if (*plen <= COMMAND_LINE_SIZE && *plen <= (BOOT_OPT_SIZE - 2*BOOT_OPT_LEN_OFFSET)) {
len += *plen + sizeof(int);
if (0 == memcmp(&p[len], BOOT_OPT_SIG, 1+strlen(BOOT_OPT_SIG))) {
hasBootParms = 1;
printBootArgRegion(p); /* Force it to include the next line in the log */
sprintf(msg, "Found bootargs=<%s>,%d bytes\n", pBootParms, *plen);
uart_puts(msg);
strncpy(pmon_kargs, pBootParms, *plen);
/* Wipe out boot parameter, so that subsequent reboot would not have it */
memset(p, 0, 1+strlen(BOOT_OPT_SIG) + *plen);
}
else {
sprintf(msg, "2nd Signature do not match @%08x, ignoring kernel boot parameters\n", &p[len]);
uart_puts(msg);
printBootArgRegion(p);
}
}
else {
sprintf(msg, "Length %d of kernel parameter is larger than allowed min(%d,%d)\n",
*plen, COMMAND_LINE_SIZE, (BOOT_OPT_SIZE - 2*BOOT_OPT_LEN_OFFSET));
uart_puts(msg);
printBootArgRegion(p);
}
}
else {
printk(KERN_INFO "1st Signature do not match, ignoring kernel boot parameters\n");
printBootArgRegion(p);
}
}
/* Use default if we don't see a valid boot prom */
/* We may use a more sophisticated scheme in filling out the parameters later, but for now
* just require that the boot loader procedure must provide the full command. Ugly but
* better than nothing.
*/
if (hasBootParms && isRootSpecified(pmon_kargs)) {
strcpy(arcs_cmdline, pmon_kargs);
appendConsoleArg(arcs_cmdline);
}
else {
/* Kernel default arguments */
#ifdef CONFIG_BLK_DEV_INITRD
strcpy(arcs_cmdline, "rw console=ttyS0,115200");
#elif defined(CONFIG_CMDLINE)
char* p;
char msg[256];
strcpy(arcs_cmdline, CONFIG_CMDLINE);
sprintf(msg, "Default command line = \'%s\'\n", CONFIG_CMDLINE);
uart_puts(msg);
p = &arcs_cmdline[0];
while (p != NULL && *p != '\0') {
if (!isspace(*p))
break;
p++;
}
if (p == NULL || *p == '\0') {
sprintf(msg, "Defaulting to boot from HD\n", CONFIG_CMDLINE);
uart_puts(msg);
/* Default is to boot from HD */
strcpy(arcs_cmdline,
"root=/dev/hda1 rw console=tty0 console=ttyS0,115200");
}
else {
/* Make sure that the boot params specify a console */
appendConsoleArg(arcs_cmdline);
}
#else /* No CONFIG_CMDLINE, and not Initrd */
/* Default is to boot from HD */
strcpy(arcs_cmdline,
"root=/dev/hda1 rw console=tty0 console=ttyS0,115200");
#endif /* No CONFIG_CMDLINE */
/*
* if root= is not on the command line, but user specified something else, tag it on
*/
if (hasBootParms && !isRootSpecified(pmon_kargs)) {
strcat(arcs_cmdline, " ");
strcat(arcs_cmdline, pmon_kargs);
}
} /* End else no root= option is specified */
uart_puts("Kernel boot options: ");
uart_puts(arcs_cmdline);
uart_puts("\r\n");
{
/*
* Support mem=nn[KMG] on command line
*/
const char* p = (const char*) arcs_cmdline;
const char* q = NULL;
const char* sizep = NULL;
int i, foundKeyword = 0, foundNumber = 0, foundUnit = 0, done = 0;
unsigned int size = 0, unitShift = 0;
unsigned int ramSizeMB;
for (i = 0; i < strlen(p) - 6 && !done; i++) {
//sprintf(msg, "i=%d\n", i);
//uart_puts(msg);
if (0 == strncmp(&p[i], "mem=", 4)) {
/* Found key, now read in value */
foundKeyword = 1;
//uart_puts("while\n");
for (sizep = q = &p[i+4];*q != '\0' && !done; q++) {
if (isdigit(*q)) {
foundNumber = 1;
continue;
}
if (foundNumber) {
//uart_puts("found number\n");
switch (*q) {
case 'k':
case 'K':
unitShift = 10; /* KB shift value*/
foundUnit = 1;
done = 1;
break;
case 'm':
case 'M':
unitShift = 20; /* MB shift value */
foundUnit = 1;
done = 1;
//uart_puts("found unit M\n");
//sprintf(msg, "q=%x\n", q);
//uart_puts(msg);
break;
case 'g':
case 'G':
/* Probably too big */
unitShift = 30; /* GB shift value */
foundUnit = 1;
done = 1;
break;
default:
done = 1;
break;
}
}
}
}
}
if (foundNumber) {
if (foundUnit) {
//uart_puts("Size=");
//uart_puts(sizep);
//uart_puts("\n");
size = bcm_atoi(sizep);
//sprintf(msg, "q=%x\n", q);
//uart_puts(msg);
sprintf(msg, "Using %d %cB for memory\n", size, *(q-1));
uart_puts(msg);
}
else {
uart_puts("Syntax: mem=nn[KMG] Option ignored : No unit specified\n");
}
}
else if (foundKeyword) {
uart_puts("Syntax: mem=nn[KMG] Option ignored : No size specified\n");
}
g_board_RAM_size = get_RAM_size();
ramSizeMB = g_board_RAM_size >> 20;
{
/*
* Kernels on STBs with larger than 32MB, we only use 32MB RAM for the kernel
*/
if (foundNumber && foundUnit) {
if (size <= ramSizeMB && size > 0) {
/* Already output size above */
}
else {
uart_puts("Invalid size ignored, using default value of 32MB\n");
size = 32;
unitShift = 20;
}
}
/* No mem=xxU specified, give the kernel 32MB of memory */
else {
uart_puts("Using 32MB for memory, overwrite by passing mem=xx\n");
size = 32;
unitShift = 20;
}
}
/* Assert size and unit not 0 */
add_memory_region(0, size << unitShift, BOOT_MEM_RAM);
/* Register the reserved upper memory, in order to allow kernel to cache them */
if (size < ramSizeMB) {
add_memory_region(size << unitShift, (ramSizeMB-size) << unitShift, BOOT_MEM_RAM);
}
}
}
/* Do basic initialization */
void __init prom_init(int argc, char **argv, unsigned long magic, int *prom_vec)
{
unsigned long mem_size;
//strcpy(arcs_cmdline, "console=tty0 console=ttyS0,115200");
#ifdef CONFIG_RTK_MTD_ROOT
strcat(arcs_cmdline,"root=/dev/mtdblock1 console=0 single");
#else
strcat(arcs_cmdline,"root=/dev/ram console=0 ramdisk_start=0 single");
#endif
mips_machgroup = MACH_GROUP_PHILIPS;
mips_machtype = MACH_PHILIPS_NINO;
#ifdef CONFIG_RTL_EB8186
#ifdef CONFIG_NINO_4MB
mem_size = 4 << 20;
#elif CONFIG_NINO_8MB
mem_size = 8 << 20;
#elif CONFIG_NINO_16MB
mem_size = 16 << 20;
#elif CONFIG_NINO_32MB
mem_size = 32 << 20;
#endif
#endif
#ifdef CONFIG_RTL865X
unsigned int MCRsdram;
switch ( MCRsdram = ( REG32( MCR ) & 0x1C100010 ) )
{
/* SDRAM 16-bit mode */
case 0x00000000:
mem_size = 2<<20;
break;
case 0x04000000:
mem_size = 4<<20;
break;
case 0x08000000:
mem_size = 8<<20;
break;
case 0x0C000000:
mem_size = 16<<20;
break;
case 0x10000000:
mem_size = 32<<20;
break;
case 0x14000000:
mem_size = 64<<20;
break;
/* SDRAM 16-bit mode - 2 chip select */
case 0x00000010:
mem_size = 4<<20;
break;
case 0x04000010:
mem_size = 8<<20;
break;
case 0x08000010:
mem_size = 16<<20;
break;
case 0x0C000010:
mem_size = 32<<20;
break;
case 0x10000010:
mem_size = 64<<20;
break;
case 0x14000010:
mem_size = 128<<20;
break;
/* SDRAM 32-bit mode */
case 0x00100000:
mem_size = 4<<20;
break;
case 0x04100000:
mem_size = 8<<20;
break;
case 0x08100000:
mem_size = 16<<20;
break;
case 0x0C100000:
mem_size = 32<<20;
break;
case 0x10100000:
mem_size = 64<<20;
break;
case 0x14100000:
mem_size =128<<20;
break;
/* SDRAM 32-bit mode - 2 chip select */
case 0x00100010:
mem_size = 8<<20;
break;
case 0x04100010:
mem_size = 16<<20;
break;
case 0x08100010:
mem_size = 32<<20;
break;
case 0x0C100010:
mem_size = 64<<20;
break;
case 0x10100010:
mem_size =128<<20;
break;
/*
case 0x14100010: mem_size =256<<20; break;
*/
default:
printk( "SDRAM unknown(0x%08X)", MCRsdram );
mem_size = 0;
break;
}
#endif
//mem_size = 16 << 20;
add_memory_region(0, mem_size, BOOT_MEM_RAM);
}
void __init plat_setup(void)
{
unsigned int tmpword;
board_time_init = momenco_time_init;
_machine_restart = momenco_ocelot_restart;
_machine_halt = momenco_ocelot_halt;
pm_power_off = momenco_ocelot_power_off;
/* Wired TLB entries */
setup_wired_tlb_entries();
/* shut down ethernet ports, just to be sure our memory doesn't get
* corrupted by random ethernet traffic.
*/
MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1), 0xff << 8);
MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0), 0xff << 8);
MV_WRITE(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1), 0xff << 8);
do {}
while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
while (MV_READ(MV64340_ETH_RECEIVE_QUEUE_COMMAND_REG(1)) & 0xff);
do {}
while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(0)) & 0xff);
do {}
while (MV_READ(MV64340_ETH_TRANSMIT_QUEUE_COMMAND_REG(1)) & 0xff);
MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0),
MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(0)) & ~1);
MV_WRITE(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1),
MV_READ(MV64340_ETH_PORT_SERIAL_CONTROL_REG(1)) & ~1);
/* Turn off the Bit-Error LED */
OCELOT_FPGA_WRITE(0x80, CLR);
tmpword = OCELOT_FPGA_READ(BOARDREV);
if (tmpword < 26)
printk("Momenco Ocelot-3: Board Assembly Rev. %c\n",
'A'+tmpword);
else
printk("Momenco Ocelot-3: Board Assembly Revision #0x%x\n",
tmpword);
tmpword = OCELOT_FPGA_READ(FPGA_REV);
printk("FPGA Rev: %d.%d\n", tmpword>>4, tmpword&15);
tmpword = OCELOT_FPGA_READ(RESET_STATUS);
printk("Reset reason: 0x%x\n", tmpword);
switch (tmpword) {
case 0x1:
printk(" - Power-up reset\n");
break;
case 0x2:
printk(" - Push-button reset\n");
break;
case 0x4:
printk(" - cPCI bus reset\n");
break;
case 0x8:
printk(" - Watchdog reset\n");
break;
case 0x10:
printk(" - Software reset\n");
break;
default:
printk(" - Unknown reset cause\n");
}
reset_reason = tmpword;
OCELOT_FPGA_WRITE(0xff, RESET_STATUS);
tmpword = OCELOT_FPGA_READ(CPCI_ID);
printk("cPCI ID register: 0x%02x\n", tmpword);
printk(" - Slot number: %d\n", tmpword & 0x1f);
printk(" - PCI bus present: %s\n", tmpword & 0x40 ? "yes" : "no");
printk(" - System Slot: %s\n", tmpword & 0x20 ? "yes" : "no");
tmpword = OCELOT_FPGA_READ(BOARD_STATUS);
printk("Board Status register: 0x%02x\n", tmpword);
printk(" - User jumper: %s\n", (tmpword & 0x80)?"installed":"absent");
printk(" - Boot flash write jumper: %s\n", (tmpword&0x40)?"installed":"absent");
printk(" - L3 cache size: %d MB\n", (1<<((tmpword&12) >> 2))&~1);
/* Support for 128 MB memory */
add_memory_region(0x0, 0x08000000, BOOT_MEM_RAM);
}
void __init
prom_init(void)
{
unsigned long extmem = 0, off, data;
static unsigned long mem;
unsigned long off1, data1;
struct nvram_header *header;
#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,36)
/* These are not really being used anywhere - LR */
mips_machgroup = MACH_GROUP_BRCM;
mips_machtype = MACH_BCM947XX;
#endif
off = (unsigned long)prom_init;
data = *(unsigned long *)prom_init;
off1 = off + 4;
data1 = *(unsigned long *)off1;
/* Figure out memory size by finding aliases */
for (mem = (1 MB); mem < (128 MB); mem <<= 1) {
if ((*(unsigned long *)(off + mem) == data) &&
(*(unsigned long *)(off1 + mem) == data1))
break;
}
detectmem = mem;
#if 0// defined(CONFIG_HIGHMEM) && !defined(CONFIG_BCM80211AC)
if (mem == 128 MB) {
early_tlb_init();
/* Add one temporary TLB entries to map SDRAM Region 2.
* Physical Virtual
* 0x80000000 0xc0000000 (1st: 256MB)
* 0x90000000 0xd0000000 (2nd: 256MB)
*/
add_tmptlb_entry(ENTRYLO(SI_SDRAM_R2),
ENTRYLO(SI_SDRAM_R2 + (256 MB)),
EXTVBASE, PM_256M);
off = EXTVBASE + __pa(off);
for (extmem = (128 MB); extmem < (512 MB); extmem <<= 1) {
if (*(unsigned long *)(off + extmem) == data)
break;
}
extmem -= mem;
/* Keep tlb entries back in consistent state */
early_tlb_init();
}
#endif /* CONFIG_HIGHMEM */
/* Ignoring the last page when ddr size is 128M. Cached
* accesses to last page is causing the processor to prefetch
* using address above 128M stepping out of the ddr address
* space.
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
mem -= 0x1000;
/* CFE could have loaded nvram during netboot
* to top 32KB of RAM, Just check for nvram signature
* and copy it to nvram space embedded in linux
* image for later use by nvram driver.
*/
header = (struct nvram_header *)(KSEG0ADDR(mem - NVRAM_SPACE));
if (ltoh32(header->magic) == NVRAM_MAGIC) {
uint32 *src = (uint32 *)header;
uint32 *dst = (uint32 *)ram_nvram_buf;
uint32 i;
printk("Copying NVRAM bytes: %d from: 0x%p To: 0x%p\n", ltoh32(header->len),
src, dst);
for (i = 0; i < ltoh32(header->len) && i < NVRAM_SPACE; i += 4)
*dst++ = ltoh32(*src++);
}
add_memory_region(SI_SDRAM_BASE, mem, BOOT_MEM_RAM);
#if 0// defined(CONFIG_HIGHMEM) && !defined(CONFIG_BCM80211AC)
if (extmem) {
/* We should deduct 0x1000 from the second memory
* region, because of the fact that processor does prefetch.
* Now that we are deducting a page from second memory
* region, we could add the earlier deducted 4KB (from first bank)
* to the second region (the fact that 0x80000000 -> 0x88000000
* shadows 0x0 -> 0x8000000)
*/
if (MIPS74K(current_cpu_data.processor_id) && (mem == (128 MB)))
extmem -= 0x1000;
add_memory_region(SI_SDRAM_R2 + (128 MB) - 0x1000, extmem, BOOT_MEM_RAM);
}
#endif /* CONFIG_HIGHMEM */
}
static void __init arch_mem_init(char **cmdline_p)
{
phys_t init_mem, init_end, init_size;
extern void plat_mem_setup(void);
/* call board setup routine */
plat_mem_setup();
init_mem = PFN_UP(__pa_symbol(&__init_begin)) << PAGE_SHIFT;
init_end = PFN_DOWN(__pa_symbol(&__init_end)) << PAGE_SHIFT;
init_size = init_end - init_mem;
if (init_size) {
/* Make sure it is in the boot_mem_map */
int i, found;
found = 0;
for (i = 0; i < boot_mem_map.nr_map; i++) {
if (init_mem >= boot_mem_map.map[i].addr &&
init_mem < (boot_mem_map.map[i].addr +
boot_mem_map.map[i].size)) {
found = 1;
break;
}
}
if (!found)
add_memory_region(init_mem, init_size,
BOOT_MEM_INIT_RAM);
}
pr_info("Determined physical RAM map:\n");
print_memory_map();
#ifdef CONFIG_CMDLINE_BOOL
#ifdef CONFIG_CMDLINE_OVERRIDE
strlcpy(boot_command_line, builtin_cmdline, COMMAND_LINE_SIZE);
#else
if (builtin_cmdline[0]) {
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
}
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
#endif
#else
strlcpy(boot_command_line, arcs_cmdline, COMMAND_LINE_SIZE);
#endif
strlcpy(command_line, boot_command_line, COMMAND_LINE_SIZE);
*cmdline_p = command_line;
parse_early_param();
if (usermem) {
pr_info("User-defined physical RAM map:\n");
print_memory_map();
}
bootmem_init();
device_tree_init();
sparse_init();
plat_swiotlb_setup();
paging_init();
}
int __init early_init_dt_reserve_memory_arch(phys_addr_t base,
phys_addr_t size, bool nomap)
{
add_memory_region(base, size, BOOT_MEM_RESERVED);
return 0;
}
void __init prom_init(void)
{
char *ptr;
cfe_init(cfe_handle, cfe_entry);
bchip_check_compat();
board_pinmux_setup();
bchip_mips_setup();
set_board_nmi_handler();
/* default to SATA (where available) or MTD rootfs */
#ifdef CONFIG_BRCM_HAS_SATA
ROOT_DEV = Root_SDA1;
#else
ROOT_DEV = MKDEV(MTD_BLOCK_MAJOR, 0);
#endif
root_mountflags &= ~MS_RDONLY;
bchip_set_features();
#if defined(CONFIG_BRCM_IKOS_DEBUG)
strcpy(arcs_cmdline, "debug initcall_debug");
#elif !defined(CONFIG_BRCM_IKOS)
cfe_read_configuration();
#endif
brcm_setup_early_printk();
#ifdef CONFIG_CMDLINE_BOOL
#ifdef CONFIG_CMDLINE_OVERRIDE
strlcpy(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
#else
if (builtin_cmdline[0]) {
strlcat(arcs_cmdline, " ", COMMAND_LINE_SIZE);
strlcat(arcs_cmdline, builtin_cmdline, COMMAND_LINE_SIZE);
}
#endif
#endif
/* provide "ubiroot" alias to reduce typing */
if (strstr(arcs_cmdline, "ubiroot"))
strcat(arcs_cmdline, " ubi.mtd=rootfs rootfstype=ubifs "
"root=ubi0:rootfs");
ptr = strstr(arcs_cmdline, "memc1=");
if (ptr)
brcm_dram1_linux_mb = memparse(ptr + 6, &ptr) >> 20;
printk(KERN_INFO "Options: enet_en=%d enet0_mii=%d enet_no_mdio=%d "
"enet1_en=%d moca=%d\n",
brcm_enet_enabled, brcm_enet0_force_ext_mii,
brcm_enet_no_mdio, brcm_enet1_enabled, brcm_moca_enabled);
printk(KERN_INFO " sata=%d docsis=%d pci=%d pcie=%d smp=%d "
"usb=%d\n",
brcm_sata_enabled, brcm_docsis_platform, brcm_pci_enabled,
brcm_pcie_enabled, brcm_smp_enabled, brcm_usb_enabled);
bchip_early_setup();
board_get_ram_size(&brcm_dram0_size_mb, &brcm_dram1_size_mb);
do {
unsigned long dram0_mb = brcm_dram0_size_mb, mb;
mb = min(dram0_mb, BRCM_MAX_LOWER_MB);
dram0_mb -= mb;
add_memory_region(0, mb << 20, BOOT_MEM_RAM);
if (!dram0_mb)
break;
#ifdef CONFIG_BRCM_UPPER_MEMORY
mb = min(dram0_mb, BRCM_MAX_UPPER_MB);
dram0_mb -= mb;
brcm_upper_tlb_setup();
add_memory_region(UPPERMEM_START, mb << 20, BOOT_MEM_RAM);
if (!dram0_mb)
break;
#endif
#if defined(CONFIG_HIGHMEM)
add_memory_region(HIGHMEM_START, dram0_mb << 20, BOOT_MEM_RAM);
break;
#endif
/*
* We wound up here because the chip's architecture cannot
* make use of all MEMC0 RAM in Linux. i.e. no suitable
* HIGHMEM or upper memory options are supported by the CPU.
*
* But we can still report the excess memory as a "bonus"
* reserved (bmem) region, so the application can manage it.
*/
mb = brcm_dram0_size_mb - dram0_mb; /* Linux memory */
if (!brcm_dram1_size_mb && mb == 256) {
printk(KERN_INFO "MEMC0 split: %lu MB -> Linux; "
"%lu MB -> extra bmem\n", mb, dram0_mb);
brcm_dram1_size_mb = dram0_mb;
brcm_dram1_start = UPPERMEM_START;
}
} while (0);
#if defined(CONFIG_HIGHMEM) && defined(CONFIG_BRCM_HAS_1GB_MEMC1)
if (brcm_dram1_linux_mb > brcm_dram1_size_mb) {
printk(KERN_WARNING "warning: 'memc1=%luM' exceeds "
"available memory (%lu MB); ignoring\n",
brcm_dram1_linux_mb, brcm_dram1_size_mb);
brcm_dram1_linux_mb = 0;
} else if (brcm_dram1_linux_mb) {
/* Since the bootloader can only map the first 256M of memc1
* when it boots, if we get memc1= request from bootloader, we
* should try to pull the memory from the end to avoid crossing
* over the memory that is allocated for boot logo image by
* bootloader.
*/
unsigned long start_mb, start_b, size, splash_bound = 0;
if (0 == parse_splash_mem(arcs_cmdline, &splash_bound, &size)) {
splash_bound += size;
}
start_mb = brcm_dram1_size_mb - brcm_dram1_linux_mb;
start_b = start_mb << 20;
if (splash_bound > start_b) {
unsigned long orig_dram1 = brcm_dram1_linux_mb;
start_mb = (splash_bound + 0x000FFFFF) >> 20;
start_b = start_mb << 20;
brcm_dram1_linux_mb = brcm_dram1_size_mb - start_mb;
printk(KERN_WARNING "warning: 'memc1=%luM' starts "
" before splash memory bound (0x%lx);"
" adjusting to (memc1=%luM)\n",
orig_dram1, splash_bound, brcm_dram1_linux_mb);
}
printk(KERN_INFO "memc1: adding %luMB at %luMB "
"(0x%08lx@0x%08lx)",
brcm_dram1_linux_mb, (MEMC1_START >> 20) + start_mb,
brcm_dram1_linux_mb << 20, MEMC1_START + start_b);
add_memory_region(MEMC1_START + start_b,
brcm_dram1_linux_mb << 20,
BOOT_MEM_RAM);
}
