void pkt_retune2_init() { reset_queue(&rx_queue); reset_queue(&tx_queue); #ifndef BLADERF_NIOS_PC_SIMULATION /* Register RX Time Tamer ISR */ alt_ic_isr_register( RX_TAMER_IRQ_INTERRUPT_CONTROLLER_ID, RX_TAMER_IRQ, retune_rx, NULL, NULL ) ; /* Register TX Time Tamer ISR */ alt_ic_isr_register( TX_TAMER_IRQ_INTERRUPT_CONTROLLER_ID, TX_TAMER_IRQ, retune_tx, NULL, NULL ) ; #endif }
static void init_dma0() { /* initialize interrupt context */ if ((dma_context->txchan = alt_dma_txchan_open("/dev/dma_0")) == NULL) { printf ("Failed to open transmit channel\n"); exit (1); } if ((dma_context->rxchan = alt_dma_rxchan_open("/dev/dma_0")) == NULL) { printf ("Failed to open receive channel\n"); exit (1); } dma_context->src = DMA_0_READ_MASTER_SRC_ON_CHIP_BASE; dma_context->dst = DMA_0_WRITE_MASTER_DST_ON_CHIP_BASE; //dma_context->len = (1 << (DMA_0_LENGTHWIDTH - 1)) - 1; // 32KB dma_context->len = 32; // 32KB dma_context->dma_done = 0; dma_context->done_callback = dma_done_func; /* Halt any current transactions (reset the device) */ //IOWR_ALTERA_AVALON_DMA_CONTROL (DMA_0_BASE, ALTERA_AVALON_DMA_CONTROL_SOFTWARERESET_MSK); IOWR_ALTERA_AVALON_DMA_CONTROL (DMA_0_BASE, ALTERA_AVALON_DMA_CONTROL_SOFTWARERESET_MSK); /* Set the default mode of the device (32 bit block reads and writes from/to memory). */ IOWR_ALTERA_AVALON_DMA_CONTROL (DMA_0_BASE, ALTERA_AVALON_DMA_CONTROL_WORD_MSK | ALTERA_AVALON_DMA_CONTROL_GO_MSK | ALTERA_AVALON_DMA_CONTROL_I_EN_MSK | ALTERA_AVALON_DMA_CONTROL_REEN_MSK | ALTERA_AVALON_DMA_CONTROL_WEEN_MSK | ALTERA_AVALON_DMA_CONTROL_LEEN_MSK); /* Clear any pending interrupts and the DONE flag */ IOWR_ALTERA_AVALON_DMA_STATUS (DMA_0_BASE, 0); /* kick off the transfer */ if(alt_dma_txchan_send(dma_context->txchan, (void *)dma_context->src, dma_context->len, NULL, NULL) < 0) printf("dma tx channel open error\n"); if(alt_dma_rxchan_prepare(dma_context->rxchan, (void *)dma_context->dst, dma_context->len, dma_context->done_callback, NULL) < 0) printf("dma rx channel open error\n"); /* Register the ISR. */ alt_ic_isr_register(DMA_0_IRQ_INTERRUPT_CONTROLLER_ID, DMA_0_IRQ, handle_dma0_interrupt, (void*)dma_context, 0x0); }
//------------------------------------------------------------------------------ tOplkError openmac_isrReg(tOpenmacIrqSource irqSource_p, tOpenmacIrqCb pfnIsrCb_p, void* pArg_p) { tOplkError ret = kErrorOk; UINT32 irqId; UINT32 icId; icId = OPENMAC_IRQ_IC_ID; switch (irqSource_p) { case kOpenmacIrqSync: irqId = OPENMAC_SYNC_IRQ; break; case kOpenmacIrqTxRx: irqId = OPENMAC_TXRX_IRQ; break; default: ret = kErrorNoResource; goto Exit; } if (alt_ic_isr_register(icId, irqId, irqHandler, (void*)irqSource_p, NULL)) { return kErrorNoResource; } instance_l.pfnIrqCb[irqSource_p] = pfnIsrCb_p; instance_l.pIrqCbArg[irqSource_p] = pArg_p; Exit: return ret; }
int main(void){ int i; alt_u32 timerPeriod = 0; #ifdef ALT_MODULE_CLASS_timer_0 // calculate timer period for 2 seconds timerPeriod = 0.001 * TIMER_0_FREQ; // initialize timer interrupt vector // alt_irq_register(TIMER_0_BASE, (void*)0, timer_ISR); //use alt_ic_isr_register() instead of alt_irq_register(), because the ALT_ENHANCED_INTERRUPT_API_PRESENT is defined. alt_ic_isr_register(TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID, TIMER_0_IRQ, timer_ISR, NULL, NULL); //initialize timer period IOWR(TIMER_0_BASE, 2, (alt_u16)timerPeriod); IOWR(TIMER_0_BASE, 3, (alt_u16)(timerPeriod >> 16)); // clear timer interrupt bit in status register IOWR(TIMER_0_BASE, 0, 0x0); // initialize timer control - start timer, run continuously, enable interrupts IOWR(TIMER_0_BASE, 1, 0x7); init(1,8); for(i = 0; i < 100; i++){ while(count_flag == 0){} IOWR(PIO_RESPONSE_BASE, 0, 1); //set the count_flag back to 0 and start to count again count_flag = 0; background(5); while(count_flag == 0){} count_flag = 0; IOWR(PIO_RESPONSE_BASE, 0, 0); } finalize(); #endif return 1; }
tEplKernel PUBLIC EplTimerSynckDelInstance (void) { tEplKernel Ret = kEplSuccessful; EplTimerSynckDrvCompareInterruptDisable(); EplTimerSynckDrvSetCompareValue( 0 ); #ifdef EPL_TIMER_USE_COMPARE_PDI_INT EplTimerSynckDrvCompareTogPdiInterruptDisable(); EplTimerSynckDrvSetCompareTogPdiValue( 0 ); #endif //EPL_TIMER_USE_COMPARE_PDI_INT #ifdef __NIOS2__ alt_ic_isr_register(EPL_TIMER_SYNC_IRQ_IC_ID, EPL_TIMER_SYNC_IRQ, NULL, NULL, NULL); #elif defined(__MICROBLAZE__) XIntc_RegisterHandler(EPL_TIMER_INTC_BASE, EPL_TIMER_SYNC_IRQ, (XInterruptHandler)NULL, (void*)NULL); #else #error "Configuration unknown!" #endif EPL_MEMSET(&EplTimerSynckInstance_l, 0, sizeof (EplTimerSynckInstance_l)); return Ret; }
MTC_INFO* MTC_Init(alt_u32 MUTI_TOUCH_BASE, alt_u32 INT_IRQ_NUM) { int error; MTC_INFO *p; p = (MTC_INFO *)malloc(sizeof(MTC_INFO)); p->TOUCH_BASE = MUTI_TOUCH_BASE; p->INT_IRQ_NUM = INT_IRQ_NUM; p->pQueue = QUEUE_New(TOUCH_QUEUE_SIZE); // // enable interrupt IOWR_ALTERA_AVALON_PIO_IRQ_MASK(p->TOUCH_BASE, 0x01); // clear capture flag IOWR_ALTERA_AVALON_PIO_EDGE_CAP(p->TOUCH_BASE, 0); // register interrupt service routine error = alt_ic_isr_register(MULTI_TOUCH_IRQ_INTERRUPT_CONTROLLER_ID, MULTI_TOUCH_IRQ, mtc_ISR, p, NULL); if (error) { printf("failed to register touch irq\r\n"); MTC_UnInit(p); p = NULL; } return p; }
void InitUart() { void* context_uart0_ptr = (void*) &context_uart0; InitUart1(UART_0_NEW_BAUD); alt_ic_isr_register(UART_0_IRQ_INTERRUPT_CONTROLLER_ID, UART_0_IRQ, IsrUart1, context_uart0_ptr, 0x0); // install UART1 ISR alt_ic_irq_enable (UART_0_IRQ_INTERRUPT_CONTROLLER_ID, UART_0_IRQ); }
/* The main function creates the LCD task, registers the edge counter polling interrupt, * and starts the OS. */ int main(void) { int status; // Initialize components. queue_init(); // Create the IR task. OSTaskCreateExt(ir_task, NULL, &ir_task_stk[TASK_STACKSIZE - 1], IR_TASK_PRIORITY, IR_TASK_PRIORITY, ir_task_stk, TASK_STACKSIZE, NULL, 0); // Create the Wifi task. OSTaskCreateExt(wifi_task, NULL, &wifi_task_stk[TASK_STACKSIZE - 1], WIFI_TASK_PRIORITY, WIFI_TASK_PRIORITY, wifi_task_stk, TASK_STACKSIZE, NULL, 0); // Create the MC task. OSTaskCreateExt(mc_task, NULL, &mc_task_stk[TASK_STACKSIZE - 1], MC_TASK_PRIORITY, MC_TASK_PRIORITY, mc_task_stk, TASK_STACKSIZE, NULL, 0); // Register the IR pushbutton interrupt. status = alt_ic_isr_register(PIO_KEY_LEFT_IRQ_INTERRUPT_CONTROLLER_ID, PIO_KEY_LEFT_IRQ, isr_on_ir_pushbutton, NULL, NULL); // Enable key interrupts. IOWR_ALTERA_AVALON_PIO_IRQ_MASK(PIO_KEY_LEFT_BASE, PIO_KEY_LEFT_CAPTURE); // Start. if (status == OK) { OSStart(); } return 0; }
//------------------------------------------------------------------------- // NAME: timer_init // // DESCRIPTION: Initializes registers and variables, and registers our // interrupt service routine. // ARGUMENTS: None // RETURNS: void //------------------------------------------------------------------------- void timer_init() { _time_remaining = 0; *(timer_reg + TIMER32_REG_STATUS) = 0x0; *(timer_reg + TIMER32_REG_CONTROL) = TIMER32_REG_CONTROL_STOP_MASK; alt_ic_isr_register(TIMER_GAME_1SEC_IRQ_INTERRUPT_CONTROLLER_ID, TIMER_GAME_1SEC_IRQ, _timer_isr, 0, 0); return; } /* timer_init */
static void disable_button_pio() { /* Disable interrupts from the button_pio PIO component. */ IOWR_ALTERA_AVALON_PIO_IRQ_MASK(BUTTON_PIO_BASE, 0x0); /* Un-register the IRQ handler by passing a null handler. */ #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT alt_ic_isr_register(BUTTON_PIO_IRQ_INTERRUPT_CONTROLLER_ID, BUTTON_PIO_IRQ, NULL, NULL, NULL); #else alt_irq_register( BUTTON_PIO_IRQ, NULL, NULL ); #endif }
int main() { initTimer(1); //1Hz //registra la interrupcion y ata a la funcion timer_isr alt_ic_isr_register(TIMER_ECE10243UPB2016_0_IRQ_INTERRUPT_CONTROLLER_ID,TIMER_ECE10243UPB2016_0_IRQ,timer_isr,(void*)NULL, 0); alt_ic_irq_enable (TIMER_ECE10243UPB2016_0_IRQ_INTERRUPT_CONTROLLER_ID,TIMER_ECE10243UPB2016_0_IRQ); while(1){ } return 0; }
int play_init(void) { const alt_u32 dev_pcm = PCM_BASE; IOWR(dev_pcm, 1, 0); IOWR(dev_pcm, 0, pcm_status_irqdisable | pcm_status_fiforst); g_wavsize = 0; g_playsize = 0; alt_ic_isr_register(PCM_IRQ_INTERRUPT_CONTROLLER_ID, PCM_IRQ, isr_handle_pcmfifofill, NULL, 0); return 0; }
int set_audio_interrupt(alt_up_audio_dev *audio, volatile int edge_capture_thing) { // Need to disable both audio interrupts before setting them up // otherwise you get stuck in them when they are setup alt_up_audio_disable_read_interrupt(audio); alt_up_audio_disable_write_interrupt(audio); void *edge_pointer = (void*)&edge_capture_thing; #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT return alt_ic_isr_register(AUDIO_CORE_IRQ_INTERRUPT_CONTROLLER_ID, AUDIO_CORE_IRQ, playMusicISR, edge_pointer, 0x0); #else return alt_irq_register(AUDIO_CORE_IRQ, edge_pointer, playMusicISR); #endif }
void altera_modular_adc_init(alt_modular_adc_dev* dev, alt_32 ic_id, alt_32 irq) { extern alt_llist altera_modular_adc_list; alt_dev_llist_insert((alt_dev_llist*) dev, &altera_modular_adc_list); if ((0 <= ic_id) && (0 <= irq)) { /* Install IRQ handler */ #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT alt_ic_isr_register(ic_id, irq, alt_adc_irq, dev, NULL); #else alt_irq_register(irq, dev, alt_adc_irq); #endif } }
/* Initialize the button_pio. */ static void init_button_pio() { /* Recast the edge_capture pointer to match the alt_irq_register() function prototype. */ void* edge_capture_ptr = (void*) &edge_capture; /* Enable all 4 button interrupts. */ IOWR_ALTERA_AVALON_PIO_IRQ_MASK(BUTTON_BASE, 0xf); /* Reset the edge capture register. */ IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTON_BASE, 0x0); /* Register the ISR. */ alt_ic_isr_register(BUTTON_IRQ_INTERRUPT_CONTROLLER_ID, BUTTON_IRQ, handle_button_interrupt, edge_capture_ptr, 0x0); }
/* The main function creates the LCD task, registers the edge counter polling interrupt, * and starts the OS. */ int main(void) { int status; // Initialize components. lcd_init(); queue_init(); // Create the LCD task. // OSTaskCreateExt(lcd_task, // NULL, // (void *)&lcd_task_stk[TASK_STACKSIZE - 1], // LCD_TASK_PRIORITY, // LCD_TASK_PRIORITY, // lcd_task_stk, // TASK_STACKSIZE, // NULL, // 0); // Create the IR task. OSTaskCreateExt(ir_task, NULL, (void *)&ir_task_stk[TASK_STACKSIZE - 1], IR_TASK_PRIORITY, IR_TASK_PRIORITY, ir_task_stk, TASK_STACKSIZE, NULL, 0); // Register the IR pushbutton interrupt. status = alt_ic_isr_register(IR_PUSHBUTTON_IRQ_INTERRUPT_CONTROLLER_ID, IR_PUSHBUTTON_IRQ, isr_on_ir_pushbutton, NULL, NULL); // Enable key interrupts. IOWR_ALTERA_AVALON_PIO_IRQ_MASK(IR_PUSHBUTTON_BASE, IR_PUSHBUTTON_CAPTURE); // Start. if (status == OK) { OSStart(); } return 0; }
static void init_button_pio() { /* Recast the edge_capture pointer to match the alt_irq_register() function * prototype. */ void* edge_capture_ptr = (void*) &edge_capture; /* Enable all 4 button interrupts. */ IOWR_ALTERA_AVALON_PIO_IRQ_MASK(BUTTON_PIO_BASE, 0xf); /* Reset the edge capture register. */ IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTON_PIO_BASE, 0x0); #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT alt_ic_isr_register(BUTTON_PIO_IRQ_INTERRUPT_CONTROLLER_ID, BUTTON_PIO_IRQ, handle_button_interrupts, edge_capture_ptr, 0x0); #else alt_irq_register( BUTTON_PIO_IRQ, edge_capture_ptr, handle_button_interrupts); #endif }
// Init interrupt void n2h_isr_init(N2H_isr_fifo* n2h_isr_fifo) { // Register N2H2 ISR if(alt_ic_isr_register(N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID, N2H2_CHAN_IRQ, n2h2_isr, (void*)n2h_isr_fifo, 0) != 0) { printf("CPU0: registering n2h2_isr failed!\n"); } // Enable interrupt on CPU side if(alt_ic_irq_enable(N2H2_CHAN_IRQ_INTERRUPT_CONTROLLER_ID, N2H2_CHAN_IRQ) != 0) { printf("CPU0: enabling n2h2 interrupt failed!\n"); } // Enable interrupts on N2H2 side IOWR(N2H2_CHAN_BASE, 4, (2 | (IORD(N2H2_CHAN_BASE,4)))); }
/* The main function creates the LCD task, registers the edge counter polling interrupt, * and starts the OS. */ int main(void) { int status; // Initialize components. lcd_init(); queue_init(); // Create the LCD task. OSTaskCreateExt(lcd_task, NULL, (void *)&lcd_task_stk[TASK_STACKSIZE - 1], LCD_TASK_PRIORITY, LCD_TASK_PRIORITY, lcd_task_stk, TASK_STACKSIZE, NULL, 0); // Create the LCD task. OSTaskCreateExt(ir_task, NULL, (void *)&ir_task_stk[TASK_STACKSIZE - 1], IR_TASK_PRIORITY, IR_TASK_PRIORITY, ir_task_stk, TASK_STACKSIZE, NULL, 0); // Register the IR pushbutton interrupt. status = alt_ic_isr_register(IR_PUSHBUTTON_IRQ_INTERRUPT_CONTROLLER_ID, IR_PUSHBUTTON_IRQ, isr_on_ir_pushbutton, NULL, NULL); // Start. if (status == OK) { OSStart(); } return 0; }
void alt_avalon_timer_sc_init (void* base, alt_u32 irq_controller_id, alt_u32 irq, alt_u32 freq) { /* set the system clock frequency */ alt_sysclk_init (freq); /* set to free running mode */ IOWR_ALTERA_AVALON_TIMER_CONTROL (base, ALTERA_AVALON_TIMER_CONTROL_ITO_MSK | ALTERA_AVALON_TIMER_CONTROL_CONT_MSK | ALTERA_AVALON_TIMER_CONTROL_START_MSK); /* register the interrupt handler, and enable the interrupt */ #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT alt_ic_isr_register(irq_controller_id, irq, alt_avalon_timer_sc_irq, base, NULL); #else alt_irq_register (irq, base, alt_avalon_timer_sc_irq); #endif }
void disable_tpad() { #ifdef ALT_VIP_VFR_0_BASE // Remove LCD display DMA activity Frame_Reader_init(); Frame_Reader_stop(1); #endif #ifdef FRAME_WRITER_0_BASE // Remove camera DMA activity alt_ic_irq_disable( 0, FRAME_WRITER_0_IRQ ); //Clear frame writer registers IOWR(FRAME_WRITER_0_BASE, 0/*FRAME_WRITER_CONTROL*/, 0x0); while(IORD(FRAME_WRITER_0_BASE, 3/*FRAME_WRITER_NEXT*/)); while(IORD(FRAME_WRITER_0_BASE, 2/*FRAME_WRITER_CURRENT*/)); while(IORD(FRAME_WRITER_0_BASE, 1/*FRAME_WRITER_LAST*/)); // NULL de-registers a pre-existing service routine and disables interrupt alt_ic_isr_register( 0, FRAME_WRITER_0_IRQ, NULL, (void *)(&frame_writer_isr_context), 0 ); #endif }
void fifoed_avalon_uart_init (fifoed_avalon_uart_state* sp,alt_u32 irq_controller_id, alt_u32 irq) { void* base = sp->base; int error; /* * Initialise the read and write flags and the semaphores used to * protect access to the circular buffers when running in a multi-threaded * environment. */ error = ALT_FLAG_CREATE (&sp->events, 0) || ALT_SEM_CREATE (&sp->read_lock, 1) || ALT_SEM_CREATE (&sp->write_lock, 1); if (!error) { /* enable interrupts at the device */ sp->ctrl = FIFOED_AVALON_UART_CONTROL_RTS_MSK | FIFOED_AVALON_UART_CONTROL_RRDY_MSK | FIFOED_AVALON_UART_CONTROL_DCTS_MSK; IOWR_FIFOED_AVALON_UART_CONTROL(base, sp->ctrl); /* register the interrupt handler */ // alt_irq_register (irq, sp, fifoed_avalon_uart_irq); #ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT alt_ic_isr_register(irq_controller_id, irq, fifoed_avalon_uart_irq, sp, 0x0); #else alt_irq_register (irq, sp, fifoed_avalon_uart_irq); #endif } }
static void init_cpu1_isr(void) { alt_ic_isr_register(PROCESSOR1_0_CPU_IRQ_0_IRQ_INTERRUPT_CONTROLLER_ID, PROCESSOR1_0_CPU_IRQ_0_IRQ, handle_cpu1_interrupt, (void*) NULL, (void*) NULL); }
tEplKernel PUBLIC EplTimerSynckAddInstance (void) { tEplKernel Ret = kEplSuccessful; EPL_MEMSET(&EplTimerSynckInstance_l, 0, sizeof (EplTimerSynckInstance_l)); EplTimerSynckDrvCompareInterruptDisable(); EplTimerSynckDrvSetCompareValue( 0 ); #ifdef EPL_TIMER_USE_COMPARE_PDI_INT EplTimerSynckDrvCompareTogPdiInterruptDisable(); EplTimerSynckDrvSetCompareTogPdiValue( 0 ); #endif //EPL_TIMER_USE_COMPARE_PDI_INT #ifdef __NIOS2__ if (alt_ic_isr_register(EPL_TIMER_SYNC_IRQ_IC_ID, EPL_TIMER_SYNC_IRQ, EplTimerSynckDrvInterruptHandler, NULL, NULL)) { Ret = kEplNoResource; } #elif defined(__MICROBLAZE__) { DWORD curIntEn = TSYN_RD32(EPL_TIMER_INTC_BASE, XIN_IER_OFFSET); XIntc_RegisterHandler(EPL_TIMER_INTC_BASE, EPL_TIMER_SYNC_IRQ, (XInterruptHandler)EplTimerSynckDrvInterruptHandler, (void*)NULL); XIntc_EnableIntr(EPL_TIMER_INTC_BASE, EPL_TIMER_SYNC_IRQ_MASK | curIntEn); } #else #error"Configuration unknown!" #endif return Ret; }