Example #1
0
void imx5_cpu_lowlevel_init(void)
{
	arm_cpu_lowlevel_init();

	enable_arm_errata_709718_war();
	enable_arm_errata_cortexa8_enable_ibe();
}
Example #2
0
static noinline __noreturn void tqmls1046a_r_entry(unsigned long memsize)
{
	unsigned long membase = LS1046A_DDR_SDRAM_BASE;

	if (get_pc() >= membase) {
		if (memsize + membase >= 0x100000000)
			memsize = 0x100000000 - membase;

		barebox_arm_entry(membase, 0x80000000,
				  __dtb_fsl_tqmls1046a_mbls10xxa_start);
	}

	arm_cpu_lowlevel_init();
	debug_ll_init();
	ls1046a_init_lowlevel();

	memsize = fsl_ddr_sdram(&ls1046a_info);

	ls1046a_errata_post_ddr();

	ls1046a_esdhc_start_image(memsize, 0, 0);

	pr_err("Booting failed\n");

	while (1);
}
Example #3
0
void __naked barebox_arm_reset_vector(void)
{
	arm_cpu_lowlevel_init();

	beaglebone_board_init();

	barebox_arm_entry(0x80000000, SZ_256M, 0);
}
Example #4
0
ENTRY_FUNCTION(start_socfpga_socrates_xload, r0, r1, r2)
{
	arm_cpu_lowlevel_init();

	arm_setup_stack(0xffff0000 + SZ_64K - SZ_4K - 16);

	socrates_entry();
}
void __naked __bare_init barebox_arm_reset_vector(void)
{
	arm_cpu_lowlevel_init();

	arm_setup_stack(SAMA5D3_SRAM_BASE + SAMA5D3_SRAM_SIZE - 16);

	barebox_arm_entry(SAMA5_DDRCS, at91sama5_get_ddram_size(), 0);
}
void __naked __bare_init barebox_arm_reset_vector(void)
{
	arm_cpu_lowlevel_init();

	arm_setup_stack(AT91SAM9261_SRAM_BASE + AT91SAM9261_SRAM_SIZE - 16);

	at91sam9261_lowlevel_init();
}
Example #7
0
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
{
	arm_cpu_lowlevel_init();

	arm_setup_stack(AT91SAM9263_SRAM0_BASE + AT91SAM9263_SRAM0_SIZE - 16);

	usb_a9263_init();
}
Example #8
0
void __bare_init __naked barebox_arm_reset_vector(void)
{
	arm_cpu_lowlevel_init();

	/* Temporary stack location in internal SRAM */
	arm_setup_stack(MX31_IRAM_BASE_ADDR + MX31_IRAM_SIZE - 8);

	mx31moboard_startup();
}
Example #9
0
ENTRY_FUNCTION(start_imx6_gk802, r0, r1, r2)
{
	uint32_t fdt;

	arm_cpu_lowlevel_init();

	fdt = (uint32_t)__dtb_imx6q_gk802_start - get_runtime_offset();
	barebox_arm_entry(0x10000000, SZ_1G, fdt);
}
void __naked __bare_init barebox_arm_reset_vector(void)
{
	arm_cpu_lowlevel_init();

	arm_setup_stack(AT91SAM9G45_SRAM_BASE + AT91SAM9G45_SRAM_SIZE - 16);

	barebox_arm_entry(AT91_CHIPSELECT_6, at91sam9g45_get_ddram_size(1),
	                  NULL);
}
Example #11
0
ENTRY_FUNCTION(start_imx6dl_hummingboard, r0, r1, r2)
{
	uint32_t fdt;

	arm_cpu_lowlevel_init();

	fdt = (uint32_t)__dtb_imx6dl_hummingboard_start - get_runtime_offset();
	barebox_arm_entry(0x10000000, SZ_512M, fdt);
}
Example #12
0
void __naked __bare_init barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
{
	arm_cpu_lowlevel_init();

	arm_setup_stack(AT91SAM9N12_SRAM_BASE + AT91SAM9N12_SRAM_SIZE - 16);

	barebox_arm_entry(AT91_CHIPSELECT_1, at91sam9n12_get_ddram_size(),
	                  NULL);
}
Example #13
0
ENTRY_FUNCTION(start_imx51_babbage, r0, r1, r2)
{
	uint32_t fdt;

	arm_cpu_lowlevel_init();

	fdt = (uint32_t)__dtb_imx51_babbage_start - get_runtime_offset();

	imx51_barebox_entry(fdt);
}
Example #14
0
void __naked __bare_init barebox_arm_reset_vector(uint32_t *data)
{
	omap3_save_bootinfo(data);

	arm_cpu_lowlevel_init();

	omap3_evm_board_init();

	barebox_arm_entry(0x80000000, SZ_128M, 0);
}
Example #15
0
ENTRY_FUNCTION(start_socfpga_socrates, r0, r1, r2)
{
	uint32_t fdt;

	arm_cpu_lowlevel_init();

	fdt = (uint32_t)__dtb_socfpga_cyclone5_socrates_start - get_runtime_offset();

	barebox_arm_entry(0x0, SZ_1G, fdt);
}
Example #16
0
ENTRY_FUNCTION(start_usi_topkick, r0, r1, r2)
{
	void *fdt;

	arm_cpu_lowlevel_init();

	fdt = __dtb_kirkwood_topkick_bb_start + get_runtime_offset();

	kirkwood_barebox_entry(fdt);
}
void __naked __bare_init barebox_arm_reset_vector(void)
{
	arm_cpu_lowlevel_init();

	arm_setup_stack(AT91SAM9260_SRAM_BASE + AT91SAM9260_SRAM_SIZE - 16);

	barebox_arm_entry(AT91_CHIPSELECT_1,
			  at91_get_sdram_size(IOMEM(AT91SAM9260_BASE_SDRAMC)),
			  NULL);
}
Example #18
0
ENTRY_FUNCTION(start_solidrun_cubox, r0, r1, r2)
{
	void *fdt;

	arm_cpu_lowlevel_init();

	fdt = __dtb_dove_cubox_bb_start - get_runtime_offset();

	mvebu_barebox_entry(fdt);
}
Example #19
0
ENTRY_FUNCTION(start_globalscale_mirabox, r0, r1, r2)
{
    void *fdt;

    arm_cpu_lowlevel_init();

    fdt = __dtb_armada_370_mirabox_bb_start -
          get_runtime_offset();

    mvebu_barebox_entry(fdt);
}
Example #20
0
ENTRY_FUNCTION(start_globalscale_guruplug, r0, r1, r2)
{
	void *fdt;

	arm_cpu_lowlevel_init();

	fdt = __dtb_kirkwood_guruplug_server_plus_bb_start -
		get_runtime_offset();

	mvebu_barebox_entry(fdt);
}
Example #21
0
void imx6_cpu_lowlevel_init(void)
{
	arm_cpu_lowlevel_init();

	enable_arm_errata_742230_war();
	enable_arm_errata_743622_war();
	enable_arm_errata_751472_war();
	enable_arm_errata_761320_war();
	enable_arm_errata_794072_war();
	enable_arm_errata_845369_war();
}
Example #22
0
ENTRY_FUNCTION(start_netgear_rn104, r0, r1, r2)
{
	void *fdt;

	arm_cpu_lowlevel_init();

	fdt = __dtb_armada_370_rn104_bb_start -
		get_runtime_offset();

	mvebu_barebox_entry(fdt);
}
Example #23
0
void barebox_arm_reset_vector(void)
{
	arm_cpu_lowlevel_init();

	if (get_pc() > 0x80000000)
		goto out;

	arm_setup_stack(0x4030d000);

	pcm049_init_lowlevel();
out:
	barebox_arm_entry(0x80000000, SZ_512M, 0);
}
Example #24
0
ENTRY_FUNCTION(start_phytec_pbab01_4gib, r0, r1, r2)
{
	uint32_t fdt;

	__barebox_arm_head();

	arm_cpu_lowlevel_init();

	arm_setup_stack(0x00920000 - 8);

	fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset();

	barebox_arm_entry(0x10000000, 0xEFFFFFF8, fdt);
}
Example #25
0
ENTRY_FUNCTION(start_imx53_mba53_1gib, r0, r1, r2)
{
	uint32_t fdt;

	arm_cpu_lowlevel_init();

	arm_setup_stack(0xf8020000 - 8);

	imx53_init_lowlevel_early(800);

	fdt = (uint32_t)__dtb_imx53_mba53_start - get_runtime_offset();

	start_imx53_tqma53_common(fdt);
}
Example #26
0
void __bare_init __naked barebox_arm_reset_vector(uint32_t *data)
{
	omap4_save_bootinfo(data);

	arm_cpu_lowlevel_init();

	if (get_pc() > 0x80000000)
		goto out;

	arm_setup_stack(0x4030d000);

	pcaaxl2_init_lowlevel();
out:
	barebox_arm_entry(0x80000000, SZ_512M, 0);
}
Example #27
0
ENTRY_FUNCTION(start_variscite_custom, r0, r1, r2)
{
	uint32_t fdt;

	arm_cpu_lowlevel_init();

	arm_setup_stack(0x00920000 - 8);

	if (IS_ENABLED(CONFIG_DEBUG_LL))
	    setup_uart();

	fdt = (uint32_t)__dtb_imx6q_var_custom_start - get_runtime_offset();

	barebox_arm_entry(0x10000000, SZ_1G, fdt);
}
Example #28
0
ENTRY_FUNCTION(start_am33xx_phytec_phycore_sram, bootinfo, r1, r2)
{
	am33xx_save_bootinfo((void *)bootinfo);

	arm_cpu_lowlevel_init();

	/*
	 * Setup C environment, the board init code uses global variables.
	 * Stackpointer has already been initialized by the ROM code.
	 */
	relocate_to_current_adr();
	setup_c();

	pcm051_board_init();
}
Example #29
0
ENTRY_FUNCTION(start_phytec_pbab01_2gib, r0, r1, r2)
{
	uint32_t fdt;

	arm_cpu_lowlevel_init();

	arm_setup_stack(0x00920000 - 8);

	if (IS_ENABLED(CONFIG_DEBUG_LL))
		setup_uart();

	fdt = (uint32_t)__dtb_imx6q_phytec_pbab01_start - get_runtime_offset();

	barebox_arm_entry(0x10000000, SZ_2G, fdt);
}
Example #30
0
static void __noreturn start_imx6q_phytec_pbaa03_common(uint32_t size)
{
	void *fdt;

	arm_cpu_lowlevel_init();

	arm_setup_stack(0x00920000 - 8);

	if (IS_ENABLED(CONFIG_DEBUG_LL))
		setup_uart();

	fdt = __dtb_imx6q_phytec_pbaa03_start - get_runtime_offset();

	barebox_arm_entry(0x10000000, size, fdt);
}