void __init at91_add_device_spi(struct spi_board_info *devices, int nr_devices) { int i; unsigned long cs_pin; short enable_spi0 = 0; short enable_spi1 = 0; /* Choose SPI chip-selects */ for (i = 0; i < nr_devices; i++) { if (devices[i].controller_data) cs_pin = (unsigned long) devices[i].controller_data; else if (devices[i].bus_num == 0) cs_pin = spi0_standard_cs[devices[i].chip_select]; else cs_pin = spi1_standard_cs[devices[i].chip_select]; if (devices[i].bus_num == 0) enable_spi0 = 1; else enable_spi1 = 1; /* enable chip-select pin */ at91_set_gpio_output(cs_pin, 1); /* pass chip-select pin to driver */ devices[i].controller_data = (void *) cs_pin; } spi_register_board_info(devices, nr_devices); /* Configure SPI bus(es) */ if (enable_spi0) { at91_set_B_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ at91_set_B_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ at91_set_B_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ platform_device_register(&at91cap9_spi0_device); } if (enable_spi1) { at91_set_A_periph(AT91_PIN_PB12, 0); /* SPI1_MISO */ at91_set_A_periph(AT91_PIN_PB13, 0); /* SPI1_MOSI */ at91_set_A_periph(AT91_PIN_PB14, 0); /* SPI1_SPCK */ platform_device_register(&at91cap9_spi1_device); } }
void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data) { if (!data) return; /* input/irq */ if (data->det_pin) { at91_set_gpio_input(data->det_pin, 1); at91_set_deglitch(data->det_pin, 1); } if (data->wp_pin) at91_set_gpio_input(data->wp_pin, 1); if (data->vcc_pin) at91_set_gpio_output(data->vcc_pin, 0); /* CLK */ at91_set_A_periph(AT91_PIN_PA8, 0); if (data->slot_b) { /* CMD */ at91_set_B_periph(AT91_PIN_PA1, 1); /* DAT0, maybe DAT1..DAT3 */ at91_set_B_periph(AT91_PIN_PA0, 1); if (data->wire4) { at91_set_B_periph(AT91_PIN_PA5, 1); at91_set_B_periph(AT91_PIN_PA4, 1); at91_set_B_periph(AT91_PIN_PA3, 1); } } else { /* CMD */ at91_set_A_periph(AT91_PIN_PA7, 1); /* DAT0, maybe DAT1..DAT3 */ at91_set_A_periph(AT91_PIN_PA6, 1); if (data->wire4) { at91_set_A_periph(AT91_PIN_PA9, 1); at91_set_A_periph(AT91_PIN_PA10, 1); at91_set_A_periph(AT91_PIN_PA11, 1); } } mmc_data = *data; platform_device_register(&at91sam9260_mmc_device); }
void __init at91_add_device_pwm(u32 mask) { if (mask & (1 << AT91_PWM0)) at91_set_B_periph(AT91_PIN_PB7, 1); /* enable PWM0 */ if (mask & (1 << AT91_PWM1)) at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */ if (mask & (1 << AT91_PWM2)) at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */ if (mask & (1 << AT91_PWM3)) at91_set_B_periph(AT91_PIN_PB29, 1); /* enable PWM3 */ pwm_mask = mask; platform_device_register(&at91sam9263_pwm0_device); }
void __init at91_add_device_pwm(u32 mask) { if (mask & (1 << AT91_PWM0)) at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */ if (mask & (1 << AT91_PWM1)) at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */ if (mask & (1 << AT91_PWM2)) at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */ if (mask & (1 << AT91_PWM3)) at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */ pwm_mask = mask; platform_device_register(&at91sam9g45_pwm0_device); }
void __init at91_add_device_pwm(u32 mask) { if (mask & (1 << AT91_PWM0)) at91_set_B_periph(AT91_PIN_PB8, 1); /* */ if (mask & (1 << AT91_PWM1)) at91_set_B_periph(AT91_PIN_PB9, 1); /* */ if (mask & (1 << AT91_PWM2)) at91_set_B_periph(AT91_PIN_PD5, 1); /* */ if (mask & (1 << AT91_PWM3)) at91_set_B_periph(AT91_PIN_PD8, 1); /* */ pwm_mask = mask; platform_device_register(&at91sam9rl_pwm0_device); }
void __init at91_add_device_isi(void) { at91_set_A_periph(AT91_PIN_PE0, 0); /* ISI_D0 */ at91_set_A_periph(AT91_PIN_PE1, 0); /* ISI_D1 */ at91_set_A_periph(AT91_PIN_PE2, 0); /* ISI_D2 */ at91_set_A_periph(AT91_PIN_PE3, 0); /* ISI_D3 */ at91_set_A_periph(AT91_PIN_PE4, 0); /* ISI_D4 */ at91_set_A_periph(AT91_PIN_PE5, 0); /* ISI_D5 */ at91_set_A_periph(AT91_PIN_PE6, 0); /* ISI_D6 */ at91_set_A_periph(AT91_PIN_PE7, 0); /* ISI_D7 */ at91_set_A_periph(AT91_PIN_PE8, 0); /* ISI_PCK */ at91_set_A_periph(AT91_PIN_PE9, 0); /* ISI_HSYNC */ at91_set_A_periph(AT91_PIN_PE10, 0); /* ISI_VSYNC */ at91_set_B_periph(AT91_PIN_PE11, 0); /* ISI_MCK (PCK3) */ at91_set_B_periph(AT91_PIN_PE12, 0); /* ISI_PD8 */ at91_set_B_periph(AT91_PIN_PE13, 0); /* ISI_PD9 */ at91_set_B_periph(AT91_PIN_PE14, 0); /* ISI_PD10 */ at91_set_B_periph(AT91_PIN_PE15, 0); /* ISI_PD11 */ }
static void __init afeb9260_board_init(void) { /* Serial */ /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD | ATMEL_UART_RI); /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&afeb9260_usbh_data); /* USB Device */ at91_add_device_udc(&afeb9260_udc_data); /* SPI */ at91_add_device_spi(afeb9260_spi_devices, ARRAY_SIZE(afeb9260_spi_devices)); /* NAND */ at91_add_device_nand(&afeb9260_nand_data); /* Ethernet */ at91_add_device_eth(&afeb9260_macb_data); /* Standard function's pin assignments are not * appropriate for us and generic code provide * no API to configure these pins any other way */ at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */ at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */ /* MMC */ at91_add_device_mci(0, &afeb9260_mci0_data); /* I2C */ at91_add_device_i2c(afeb9260_i2c_devices, ARRAY_SIZE(afeb9260_i2c_devices)); /* Audio */ at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); /* IDE */ at91_add_device_cf(&afeb9260_cf_data); }
static void __init ek_add_device_ks8851(void) { /* Configure chip-select 2 (KS8851) */ sam9_smc_configure(0, 2, &ks8851_smc_config); /* Configure NCS signal */ at91_set_B_periph(AT91_PIN_PD19, 0); /* Configure Interrupt pin as input, no pull-up */ at91_set_gpio_input(AT91_PIN_PD21, 0); add_ks8851_device(DEVICE_ID_SINGLE, AT91_CHIPSELECT_2, AT91_CHIPSELECT_2 + 2, IORESOURCE_MEM_16BIT, NULL); }
static void at91sam9g20ek_spi_hw_init(void) { at91_set_A_periph(AT91_PIN_PA3, 0); /* SPI0_NPCS0 */ at91_set_B_periph(AT91_PIN_PC11, 0); /* SPI0_NPCS1 */ at91_set_A_periph(AT91_PIN_PA0, 0); /* SPI0_MISO */ at91_set_A_periph(AT91_PIN_PA1, 0); /* SPI0_MOSI */ at91_set_A_periph(AT91_PIN_PA2, 0); /* SPI0_SPCK */ /* Enable clock */ at91_sys_write(AT91_PMC_PCER, 1 << AT91SAM9260_ID_SPI0); }
void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) { if (!data) { return; } at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ lcdc_data = *data; platform_device_register(&at91_lcdc_device); }
static void at91sam9261ek_lcd_hw_init(void) { at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ at91_sys_write(AT91_PMC_SCER, AT91_PMC_HCK1); gd->fb_base = AT91SAM9261_SRAM_BASE; }
static void picosam9g45_lcd_hw_init(void) { struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC; at91_set_A_periph(AT91_PIN_PE0, 0); /* LCDDPWR */ at91_set_A_periph(AT91_PIN_PE2, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PE3, 0); /* LCDVSYNC */ at91_set_A_periph(AT91_PIN_PE4, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PE5, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PE7, 0); /* LCDD0 */ at91_set_A_periph(AT91_PIN_PE8, 0); /* LCDD1 */ at91_set_A_periph(AT91_PIN_PE9, 0); /* LCDD2 */ at91_set_A_periph(AT91_PIN_PE10, 0); /* LCDD3 */ at91_set_A_periph(AT91_PIN_PE11, 0); /* LCDD4 */ at91_set_A_periph(AT91_PIN_PE12, 0); /* LCDD5 */ at91_set_A_periph(AT91_PIN_PE13, 0); /* LCDD6 */ at91_set_A_periph(AT91_PIN_PE14, 0); /* LCDD7 */ at91_set_A_periph(AT91_PIN_PE15, 0); /* LCDD8 */ at91_set_A_periph(AT91_PIN_PE16, 0); /* LCDD9 */ at91_set_A_periph(AT91_PIN_PE17, 0); /* LCDD10 */ at91_set_A_periph(AT91_PIN_PE18, 0); /* LCDD11 */ at91_set_A_periph(AT91_PIN_PE19, 0); /* LCDD12 */ at91_set_B_periph(AT91_PIN_PE20, 0); /* LCDD13 */ at91_set_A_periph(AT91_PIN_PE21, 0); /* LCDD14 */ at91_set_A_periph(AT91_PIN_PE22, 0); /* LCDD15 */ at91_set_A_periph(AT91_PIN_PE23, 0); /* LCDD16 */ at91_set_A_periph(AT91_PIN_PE24, 0); /* LCDD17 */ at91_set_A_periph(AT91_PIN_PE25, 0); /* LCDD18 */ at91_set_A_periph(AT91_PIN_PE26, 0); /* LCDD19 */ at91_set_A_periph(AT91_PIN_PE27, 0); /* LCDD20 */ at91_set_B_periph(AT91_PIN_PE28, 0); /* LCDD21 */ at91_set_A_periph(AT91_PIN_PE29, 0); /* LCDD22 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* LCDD23 */ writel(1 << ATMEL_ID_LCDC, &pmc->pcer); gd->fb_base = CONFIG_AT91SAM9G45_LCD_BASE; }
void at91_add_device_spi(int spi_id, struct at91_spi_platform_data *pdata) { int i; int cs_pin; resource_size_t start = ~0; BUG_ON(spi_id > 1); if (!pdata) pdata = &spi_pdata[spi_id]; for (i = 0; i < pdata->num_chipselect; i++) { cs_pin = pdata->chipselect[i]; /* enable chip-select pin */ if (gpio_is_valid(cs_pin)) at91_set_gpio_output(cs_pin, 1); } /* Configure SPI bus(es) */ switch (spi_id) { case 0: start = SAMA5D3_BASE_SPI0; at91_set_A_periph(AT91_PIN_PD10, 0); /* SPI0_MISO */ at91_set_A_periph(AT91_PIN_PD11, 0); /* SPI0_MOSI */ at91_set_A_periph(AT91_PIN_PD12, 0); /* SPI0_SPCK */ break; case 1: start = SAMA5D3_BASE_SPI1; at91_set_B_periph(AT91_PIN_PC22, 0); /* SPI1_MISO */ at91_set_B_periph(AT91_PIN_PC23, 0); /* SPI1_MOSI */ at91_set_B_periph(AT91_PIN_PC24, 0); /* SPI1_SPCK */ break; } add_generic_device("atmel_spi", spi_id, NULL, start, SZ_16K, IORESOURCE_MEM, pdata); }
void __init at91_add_device_pwm(u32 mask) { if (mask & (1 << AT91_PWM0)) at91_set_B_periph(AT91_PIN_PD24, 1); /* enable PWM0 */ #if defined(CONFIG_MACH_LOPHILO_TABBY) if (mask & (1 << AT91_PWM1)) at91_set_B_periph(AT91_PIN_PD25, 1); /* enable PWM1 */ #else if (mask & (1 << AT91_PWM1)) at91_set_B_periph(AT91_PIN_PD31, 1); /* enable PWM1 */ #endif if (mask & (1 << AT91_PWM2)) at91_set_B_periph(AT91_PIN_PD26, 1); /* enable PWM2 */ if (mask & (1 << AT91_PWM3)) at91_set_B_periph(AT91_PIN_PD0, 1); /* enable PWM3 */ pwm_mask = mask; platform_device_register(&at91sam9g45_pwm0_device); }
void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data) { if (!data) { return; } #if defined(CONFIG_FB_ATMEL_STN) at91_set_A_periph(AT91_PIN_PB0, 0); /* LCDVSYNC */ at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PB5, 0); /* LCDD0 */ at91_set_A_periph(AT91_PIN_PB6, 0); /* LCDD1 */ at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ #else at91_set_A_periph(AT91_PIN_PB1, 0); /* LCDHSYNC */ at91_set_A_periph(AT91_PIN_PB2, 0); /* LCDDOTCK */ at91_set_A_periph(AT91_PIN_PB3, 0); /* LCDDEN */ at91_set_A_periph(AT91_PIN_PB4, 0); /* LCDCC */ at91_set_A_periph(AT91_PIN_PB7, 0); /* LCDD2 */ at91_set_A_periph(AT91_PIN_PB8, 0); /* LCDD3 */ at91_set_A_periph(AT91_PIN_PB9, 0); /* LCDD4 */ at91_set_A_periph(AT91_PIN_PB10, 0); /* LCDD5 */ at91_set_A_periph(AT91_PIN_PB11, 0); /* LCDD6 */ at91_set_A_periph(AT91_PIN_PB12, 0); /* LCDD7 */ at91_set_A_periph(AT91_PIN_PB15, 0); /* LCDD10 */ at91_set_A_periph(AT91_PIN_PB16, 0); /* LCDD11 */ at91_set_A_periph(AT91_PIN_PB17, 0); /* LCDD12 */ at91_set_A_periph(AT91_PIN_PB18, 0); /* LCDD13 */ at91_set_A_periph(AT91_PIN_PB19, 0); /* LCDD14 */ at91_set_A_periph(AT91_PIN_PB20, 0); /* LCDD15 */ at91_set_B_periph(AT91_PIN_PB23, 0); /* LCDD18 */ at91_set_B_periph(AT91_PIN_PB24, 0); /* LCDD19 */ at91_set_B_periph(AT91_PIN_PB25, 0); /* LCDD20 */ at91_set_B_periph(AT91_PIN_PB26, 0); /* LCDD21 */ at91_set_B_periph(AT91_PIN_PB27, 0); /* LCDD22 */ at91_set_B_periph(AT91_PIN_PB28, 0); /* LCDD23 */ #endif if (ARRAY_SIZE(lcdc_resources) > 2) { void __iomem *fb; struct resource *fb_res = &lcdc_resources[2]; size_t fb_len = fb_res->end - fb_res->start + 1; fb = ioremap(fb_res->start, fb_len); if (fb) { memset(fb, 0, fb_len); iounmap(fb); } } lcdc_data = *data; platform_device_register(&at91_lcdc_device); }
void at91_add_device_eth(int id, struct at91_ether_platform_data *data) { if (!data) return; /* Pins used for MII and RMII */ at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ if (!(data->flags & AT91SAM_ETHER_RMII)) { at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ if (data->flags & AT91SAM_ETX2_ETX3_ALTERNATIVE) { at91_set_B_periph(AT91_PIN_PA10, 0); /* ETX2 */ at91_set_B_periph(AT91_PIN_PA11, 0); /* ETX3 */ } else { at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ } at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ } add_generic_device("macb", 0, NULL, AT91SAM9260_BASE_EMAC, 0x1000, IORESOURCE_MEM, data); }
/* Consider only one slot : slot 0 */ void __init at91_add_device_mci(short mmc_id, struct atmel_mci_platform_data *data) { resource_size_t start = ~0; if (!data) return; /* Must have at least one usable slot */ if (!data->bus_width) return; /* input/irq */ if (gpio_is_valid(data->detect_pin)) { at91_set_gpio_input(data->detect_pin, 1); at91_set_deglitch(data->detect_pin, 1); } if (gpio_is_valid(data->wp_pin)) at91_set_gpio_input(data->wp_pin, 1); if (mmc_id == 0) { /* MCI0 */ start = AT91SAM9X5_BASE_MCI0; /* CLK */ at91_set_A_periph(AT91_PIN_PA17, 0); /* CMD */ at91_set_A_periph(AT91_PIN_PA16, 1); /* DAT0, maybe DAT1..DAT3 */ at91_set_A_periph(AT91_PIN_PA15, 1); if (data->bus_width == 4) { at91_set_A_periph(AT91_PIN_PA18, 1); at91_set_A_periph(AT91_PIN_PA19, 1); at91_set_A_periph(AT91_PIN_PA20, 1); } } else { /* MCI1 */ start = AT91SAM9X5_BASE_MCI1; /* CLK */ at91_set_B_periph(AT91_PIN_PA13, 0); /* CMD */ at91_set_B_periph(AT91_PIN_PA12, 1); /* DAT0, maybe DAT1..DAT3 */ at91_set_B_periph(AT91_PIN_PA11, 1); if (data->bus_width == 4) { at91_set_B_periph(AT91_PIN_PA2, 1); at91_set_B_periph(AT91_PIN_PA3, 1); at91_set_B_periph(AT91_PIN_PA4, 1); } } add_generic_device("atmel_mci", mmc_id, NULL, start, SZ_16K, IORESOURCE_MEM, data); }
static void __init at73c213_set_clk(struct at73c213_board_info *info) { struct clk *pck2; struct clk *plla; pck2 = clk_get(NULL, "pck2"); plla = clk_get(NULL, "plla"); /* AT73C213 MCK Clock */ at91_set_B_periph(AT91_PIN_PB31, 0); /* PCK2 */ clk_set_parent(pck2, plla); clk_put(plla); info->dac_clk = pck2; }
void __init at91_add_device_mmc(struct at91_mmc_data *data) { /* input/irq */ if (data->det_pin) { at91_set_gpio_direction(data->det_pin, 1, 1); at91_set_deglitch(data->det_pin, 1); } if (data->wp_pin) at91_set_gpio_direction(data->wp_pin, 1, 1); /* CLK */ at91_set_A_periph(AT91_PIN_PA27, 0); if (data->is_b) { /* CMD */ at91_set_B_periph(AT91_PIN_PA8, 0); /* DAT0, maybe DAT1..DAT3 */ at91_set_B_periph(AT91_PIN_PA9, 0); if (data->wire4) { at91_set_B_periph(AT91_PIN_PA10, 0); at91_set_B_periph(AT91_PIN_PA11, 0); at91_set_B_periph(AT91_PIN_PA12, 0); } } else { /* CMD */ at91_set_A_periph(AT91_PIN_PA28, 0); /* DAT0, maybe DAT1..DAT3 */ at91_set_A_periph(AT91_PIN_PA29, 0); if (data->wire4) { at91_set_B_periph(AT91_PIN_PB3, 0); at91_set_B_periph(AT91_PIN_PB4, 0); at91_set_B_periph(AT91_PIN_PB5, 0); } } mmc_data = *data; platform_device_register(&at91rm9200_mmc_device); }
static void __init ek_board_init(void) { /* Serial */ /* DBGU on ttyS0. (Rx & Tx only) */ at91_register_uart(0, 0, 0); /* USART0 on ttyS1. (Rx, Tx, CTS, RTS, DTR, DSR, DCD, RI) */ at91_register_uart(AT91SAM9260_ID_US0, 1, ATMEL_UART_CTS | ATMEL_UART_RTS | ATMEL_UART_DTR | ATMEL_UART_DSR | ATMEL_UART_DCD | ATMEL_UART_RI); /* USART1 on ttyS2. (Rx, Tx, RTS, CTS) */ at91_register_uart(AT91SAM9260_ID_US1, 2, ATMEL_UART_CTS | ATMEL_UART_RTS); at91_add_device_serial(); /* USB Host */ at91_add_device_usbh(&ek_usbh_data); /* USB Device */ at91_add_device_udc(&ek_udc_data); /* SPI */ at91_add_device_spi(ek_spi_devices, ARRAY_SIZE(ek_spi_devices)); /* NAND */ ek_add_device_nand(); /* Ethernet */ ek_add_device_macb(); /* Regulators */ ek_add_regulators(); /* MMC */ ek_add_device_mmc(); /* I2C */ at91_add_device_i2c(ek_i2c_devices, ARRAY_SIZE(ek_i2c_devices)); /* LEDs */ ek_add_device_gpio_leds(); /* Push Buttons */ ek_add_device_buttons(); /* ADCs */ at91_add_device_adc(&ek_adc_data); /* PCK0 provides MCLK to the WM8731 */ at91_set_B_periph(AT91_PIN_PC1, 0); /* SSC (for WM8731) */ at91_add_device_ssc(AT91SAM9260_ID_SSC, ATMEL_SSC_TX); ek_add_device_audio(); }
static void rdac_init_int(struct keypad_data_s *k) { struct rdac_ic *ic = k->private_data; unsigned long flags; u8 tmp; at91_set_B_periph(AT91_PIN_PC15, 0); at91_set_deglitch(AT91_PIN_PC15, 0); spin_lock_irqsave(&ic->lock, flags); ic->num_registered++; /* trigger on falling edge */ tmp = ioread8(ic->icr) | RDAC_IC_KEYPAD_TRIGGER_FALLING; iowrite8(tmp, ic->icr); iowrite8(RDAC_IC_KEYPAD, ic->isr); tmp = ioread8(ic->ier) | RDAC_IC_KEYPAD; iowrite8(tmp, ic->ier); spin_unlock_irqrestore(&ic->lock, flags); }
static inline void configure_ssc1_pins(unsigned pins) { if (pins & ATMEL_SSC_TF) at91_set_B_periph(AT91_PIN_PA29, 1); if (pins & ATMEL_SSC_TK) at91_set_B_periph(AT91_PIN_PA30, 1); if (pins & ATMEL_SSC_TD) at91_set_B_periph(AT91_PIN_PA13, 1); if (pins & ATMEL_SSC_RD) at91_set_B_periph(AT91_PIN_PA14, 1); if (pins & ATMEL_SSC_RK) at91_set_B_periph(AT91_PIN_PA9, 1); if (pins & ATMEL_SSC_RF) at91_set_B_periph(AT91_PIN_PA8, 1); }
static inline void configure_ssc0_pins(unsigned pins) { if (pins & ATMEL_SSC_TF) at91_set_B_periph(AT91_PIN_PB0, 1); if (pins & ATMEL_SSC_TK) at91_set_B_periph(AT91_PIN_PB1, 1); if (pins & ATMEL_SSC_TD) at91_set_B_periph(AT91_PIN_PB2, 1); if (pins & ATMEL_SSC_RD) at91_set_B_periph(AT91_PIN_PB3, 1); if (pins & ATMEL_SSC_RK) at91_set_B_periph(AT91_PIN_PB4, 1); if (pins & ATMEL_SSC_RF) at91_set_B_periph(AT91_PIN_PB5, 1); }
static inline void configure_ssc2_pins(unsigned pins) { if (pins & ATMEL_SSC_TF) at91_set_B_periph(AT91_PIN_PC25, 1); if (pins & ATMEL_SSC_TK) at91_set_B_periph(AT91_PIN_PC26, 1); if (pins & ATMEL_SSC_TD) at91_set_B_periph(AT91_PIN_PC27, 1); if (pins & ATMEL_SSC_RD) at91_set_B_periph(AT91_PIN_PC28, 1); if (pins & ATMEL_SSC_RK) at91_set_B_periph(AT91_PIN_PC29, 1); if (pins & ATMEL_SSC_RF) at91_set_B_periph(AT91_PIN_PC30, 1); }
static inline void configure_ssc1_pins(unsigned pins) { if (pins & ATMEL_SSC_TF) at91_set_B_periph(AT91_PIN_PA17, 1); if (pins & ATMEL_SSC_TK) at91_set_B_periph(AT91_PIN_PA18, 1); if (pins & ATMEL_SSC_TD) at91_set_B_periph(AT91_PIN_PA19, 1); if (pins & ATMEL_SSC_RD) at91_set_B_periph(AT91_PIN_PA20, 1); if (pins & ATMEL_SSC_RK) at91_set_B_periph(AT91_PIN_PA21, 1); if (pins & ATMEL_SSC_RF) at91_set_B_periph(AT91_PIN_PA22, 1); }
/* * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT * controller debugging * The ET1100 is located at physical address 0x70000000 * Its process memory is located at physical address 0x70001000 */ static void meesc_ethercat_hw_init(void) { /* Configure SMC EBI1_CS0 for EtherCAT */ at91_sys_write(AT91_SMC1_SETUP(0), AT91_SMC_NWESETUP_(0) | AT91_SMC_NCS_WRSETUP_(0) | AT91_SMC_NRDSETUP_(0) | AT91_SMC_NCS_RDSETUP_(0)); at91_sys_write(AT91_SMC1_PULSE(0), AT91_SMC_NWEPULSE_(4) | AT91_SMC_NCS_WRPULSE_(9) | AT91_SMC_NRDPULSE_(4) | AT91_SMC_NCS_RDPULSE_(9)); at91_sys_write(AT91_SMC1_CYCLE(0), AT91_SMC_NWECYCLE_(10) | AT91_SMC_NRDCYCLE_(5)); /* Configure behavior at external wait signal, byte-select mode, 16 bit data bus width, none data float wait states and TDF optimization */ at91_sys_write(AT91_SMC1_MODE(0), AT91_SMC_READMODE | AT91_SMC_EXNWMODE_READY | AT91_SMC_BAT_SELECT | AT91_SMC_DBW_16 | AT91_SMC_TDF_(0) | AT91_SMC_TDFMODE); /* Configure RDY/BSY */ at91_set_B_periph(AT91_PIN_PE20, 0); /* EBI1_NWAIT */ }
void at91_macb_hw_init(void) { at91_set_A_periph(AT91_PIN_PA17, 0); /* ETXCK_EREFCK */ at91_set_A_periph(AT91_PIN_PA15, 0); /* ERXDV */ at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ at91_set_A_periph(AT91_PIN_PA16, 0); /* ERXER */ at91_set_A_periph(AT91_PIN_PA14, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX0 */ at91_set_A_periph(AT91_PIN_PA11, 0); /* ETX1 */ at91_set_A_periph(AT91_PIN_PA19, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA18, 0); /* EMDC */ #ifndef CONFIG_RMII at91_set_B_periph(AT91_PIN_PA29, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PA30, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PA8, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PA9, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PA28, 0); /* ERXCK */ at91_set_B_periph(AT91_PIN_PA6, 0); /* ETX2 */ at91_set_B_periph(AT91_PIN_PA7, 0); /* ETX3 */ at91_set_B_periph(AT91_PIN_PA27, 0); /* ETXER */ #endif }
void __init at91_add_device_eth(struct macb_platform_data *data) { if (!data) return; if (gpio_is_valid(data->phy_irq_pin)) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } /* Pins used for MII and RMII */ at91_set_A_periph(AT91_PIN_PE21, 0); /* ETXCK_EREFCK */ at91_set_B_periph(AT91_PIN_PC25, 0); /* ERXDV */ at91_set_A_periph(AT91_PIN_PE25, 0); /* ERX0 */ at91_set_A_periph(AT91_PIN_PE26, 0); /* ERX1 */ at91_set_A_periph(AT91_PIN_PE27, 0); /* ERXER */ at91_set_A_periph(AT91_PIN_PE28, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PE23, 0); /* ETX0 */ at91_set_A_periph(AT91_PIN_PE24, 0); /* ETX1 */ at91_set_A_periph(AT91_PIN_PE30, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PE29, 0); /* EMDC */ if (!data->is_rmii) { at91_set_A_periph(AT91_PIN_PE22, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PC26, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PC22, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PC23, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PC27, 0); /* ERXCK */ at91_set_B_periph(AT91_PIN_PC20, 0); /* ETX2 */ at91_set_B_periph(AT91_PIN_PC21, 0); /* ETX3 */ at91_set_B_periph(AT91_PIN_PC24, 0); /* ETXER */ } eth_data = *data; platform_device_register(&at91sam9263_eth_device); }
void __init at91_add_device_eth(struct macb_platform_data *data) { if (!data) return; if (gpio_is_valid(data->phy_irq_pin)) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } /* Pins used for MII and RMII */ at91_set_A_periph(AT91_PIN_PA16, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA15, 0); /* EMDC */ at91_set_A_periph(AT91_PIN_PA14, 0); /* ERXER */ at91_set_A_periph(AT91_PIN_PA13, 0); /* ERX1 */ at91_set_A_periph(AT91_PIN_PA12, 0); /* ERX0 */ at91_set_A_periph(AT91_PIN_PA11, 0); /* ECRS_ECRSDV */ at91_set_A_periph(AT91_PIN_PA10, 0); /* ETX1 */ at91_set_A_periph(AT91_PIN_PA9, 0); /* ETX0 */ at91_set_A_periph(AT91_PIN_PA8, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PA7, 0); /* ETXCK_EREFCK */ if (!data->is_rmii) { at91_set_B_periph(AT91_PIN_PB19, 0); /* ERXCK */ at91_set_B_periph(AT91_PIN_PB18, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PB17, 0); /* ERXDV */ at91_set_B_periph(AT91_PIN_PB16, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PB15, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PB14, 0); /* ETXER */ at91_set_B_periph(AT91_PIN_PB13, 0); /* ETX3 */ at91_set_B_periph(AT91_PIN_PB12, 0); /* ETX2 */ } eth_data = *data; platform_device_register(&at91rm9200_eth_device); }
void __init at91_add_device_eth(struct at91_eth_data *data) { if (!data) return; if (data->phy_irq_pin) { at91_set_gpio_input(data->phy_irq_pin, 0); at91_set_deglitch(data->phy_irq_pin, 1); } /* Pins used for MII and RMII */ at91_set_A_periph(AT91_PIN_PA19, 0); /* ETXCK_EREFCK */ at91_set_A_periph(AT91_PIN_PA17, 0); /* ERXDV */ at91_set_A_periph(AT91_PIN_PA14, 0); /* ERX0 */ at91_set_A_periph(AT91_PIN_PA15, 0); /* ERX1 */ at91_set_A_periph(AT91_PIN_PA18, 0); /* ERXER */ at91_set_A_periph(AT91_PIN_PA16, 0); /* ETXEN */ at91_set_A_periph(AT91_PIN_PA12, 0); /* ETX0 */ at91_set_A_periph(AT91_PIN_PA13, 0); /* ETX1 */ at91_set_A_periph(AT91_PIN_PA21, 0); /* EMDIO */ at91_set_A_periph(AT91_PIN_PA20, 0); /* EMDC */ if (!data->is_rmii) { at91_set_B_periph(AT91_PIN_PA28, 0); /* ECRS */ at91_set_B_periph(AT91_PIN_PA29, 0); /* ECOL */ at91_set_B_periph(AT91_PIN_PA25, 0); /* ERX2 */ at91_set_B_periph(AT91_PIN_PA26, 0); /* ERX3 */ at91_set_B_periph(AT91_PIN_PA27, 0); /* ERXCK */ at91_set_B_periph(AT91_PIN_PA23, 0); /* ETX2 */ at91_set_B_periph(AT91_PIN_PA24, 0); /* ETX3 */ at91_set_B_periph(AT91_PIN_PA22, 0); /* ETXER */ } eth_data = *data; platform_device_register(&at91sam9260_eth_device); }