int ehci_hcd_init(int index, enum usb_init_type init, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct usb_ehci *ehci; /* The only user for this is efikamx-usb */ ehci_set_controller_priv(index, NULL, &mx5_ehci_ops); set_usboh3_clk(); enable_usboh3_clk(true); set_usb_phy_clk(); enable_usb_phy1_clk(true); enable_usb_phy2_clk(true); mdelay(1); /* Do board specific initialization */ board_ehci_hcd_init(CONFIG_MXC_USB_PORT); ehci = (struct usb_ehci *)(OTG_BASE_ADDR + (0x200 * CONFIG_MXC_USB_PORT)); *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); mdelay(10); /* Do board specific post-initialization */ board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); return 0; }
int ehci_hcd_init(void) { struct usb_ehci *ehci; #ifdef CONFIG_MX53 struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR; u32 reg; reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26); /* derive USB PHY clock multiplexer from PLL3 */ reg |= 1 << 26; __raw_writel(reg, &sc_regs->cscmr1); #endif set_usboh3_clk(); enable_usboh3_clk(1); set_usb_phy2_clk(); enable_usb_phy2_clk(1); mdelay(1); /* Do board specific initialization */ board_ehci_hcd_init(CONFIG_MXC_USB_PORT); ehci = (struct usb_ehci *)(OTG_BASE_ADDR + (0x200 * CONFIG_MXC_USB_PORT)); hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); hcor = (struct ehci_hcor *)((uint32_t)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS); mdelay(10); /* Do board specific post-initialization */ board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT); return 0; }
int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) { struct usb_ehci *ehci; u32 reg; #ifdef CONFIG_MX53 struct clkctl *sc_regs = (struct clkctl *)CCM_BASE_ADDR; reg = __raw_readl(&sc_regs->cscmr1) & ~(1 << 26); /* derive USB PHY clock multiplexer from PLL3 */ reg |= 1 << 26; __raw_writel(reg, &sc_regs->cscmr1); #endif if (clks_run == 0) { set_usboh3_clk(); enable_usboh3_clk(1); set_usb_phy_clk(); enable_usb_phy1_clk(1); enable_usb_phy2_clk(1); mdelay(1); clks_run = 1; } #ifndef CONFIG_MXC_USB_PORT1SC #define CONFIG_MXC_USB_PORT1SC (2 << 30) #define CONFIG_MXC_USB_FLAGS1 0 #endif #ifndef CONFIG_MXC_USB_PORT2SC #define CONFIG_MXC_USB_PORT2SC (2 << 30) #define CONFIG_MXC_USB_FLAGS2 0 #endif /* Do board specific initialization */ board_ehci_hcd_init(index); ehci = (struct usb_ehci *)(OTG_BASE_ADDR + (0x200 * index)); *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength); *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); setbits_le32(&ehci->usbmode, CM_HOST); switch (index) { case 0: __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mxc_set_usbcontrol(index, CONFIG_MXC_USB_FLAGS); break; case 1: __raw_writel(CONFIG_MXC_USB_PORT1SC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mxc_set_usbcontrol(index, CONFIG_MXC_USB_FLAGS1); break; case 2: __raw_writel(CONFIG_MXC_USB_PORT2SC, &ehci->portsc); setbits_le32(&ehci->portsc, USB_EN); mxc_set_usbcontrol(index, CONFIG_MXC_USB_FLAGS2); break; // case 3: // __raw_writel(CONFIG_MXC_USB_PORT3SC, &ehci->portsc); // setbits_le32(&ehci->portsc, USB_EN); // mxc_set_usbcontrol(index, CONFIG_MXC_USB_FLAGS3); // break; } /* Do board specific post-initialization */ board_ehci_hcd_postinit(ehci, index); return 0; }