static int ehci_atmel_enable_clk(struct udevice *dev) { struct clk clk; int ret; ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; ret = clk_enable(&clk); if (ret) return ret; ret = clk_get_by_index(dev, 1, &clk); if (ret) return -EINVAL; ret = clk_enable(&clk); if (ret) return ret; clk_free(&clk); return 0; }
static int rockchip_spi_ofdata_to_platdata(struct udevice *bus) { struct rockchip_spi_platdata *plat = bus->platdata; struct rockchip_spi_priv *priv = dev_get_priv(bus); const void *blob = gd->fdt_blob; int node = bus->of_offset; int ret; plat->base = dev_get_addr(bus); ret = clk_get_by_index(bus, 0, &priv->clk); if (ret < 0) { debug("%s: Could not get clock for %s: %d\n", __func__, bus->name, ret); return ret; } plat->frequency = fdtdec_get_int(blob, node, "spi-max-frequency", 50000000); plat->deactivate_delay_us = fdtdec_get_int(blob, node, "spi-deactivate-delay", 0); plat->activate_delay_us = fdtdec_get_int(blob, node, "spi-activate-delay", 0); debug("%s: base=%x, max-frequency=%d, deactivate_delay=%d\n", __func__, (uint)plat->base, plat->frequency, plat->deactivate_delay_us); return 0; }
static int sifive_serial_setbrg(struct udevice *dev, int baudrate) { int err; struct clk clk; struct sifive_uart_platdata *platdata = dev_get_platdata(dev); err = clk_get_by_index(dev, 0, &clk); if (!err) { err = clk_get_rate(&clk); if (!IS_ERR_VALUE(err)) platdata->clock = err; } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { debug("SiFive UART failed to get clock\n"); return err; } if (!platdata->clock) platdata->clock = dev_read_u32_default(dev, "clock-frequency", 0); if (!platdata->clock) { debug("SiFive UART clock not defined\n"); return -EINVAL; } _sifive_serial_setbrg(platdata->regs, platdata->clock, baudrate); return 0; }
static int pic32_uart_probe(struct udevice *dev) { struct pic32_uart_priv *priv = dev_get_priv(dev); struct clk clk; fdt_addr_t addr; fdt_size_t size; int ret; /* get address */ addr = fdtdec_get_addr_size(gd->fdt_blob, dev->of_offset, "reg", &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; priv->base = ioremap(addr, size); /* get clock rate */ ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) return ret; priv->uartclk = clk_get_rate(&clk); clk_free(&clk); /* initialize serial */ return pic32_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE); }
static int atmel_spi_enable_clk(struct udevice *bus) { struct atmel_spi_priv *priv = dev_get_priv(bus); struct clk clk; ulong clk_rate; int ret; ret = clk_get_by_index(bus, 0, &clk); if (ret) return -EINVAL; ret = clk_enable(&clk); if (ret) return ret; clk_rate = clk_get_rate(&clk); if (!clk_rate) return -EINVAL; priv->bus_clk_rate = clk_rate; clk_free(&clk); return 0; }
static int stm32_serial_probe(struct udevice *dev) { struct stm32x7_serial_platdata *plat = dev_get_platdata(dev); struct clk clk; int ret; plat->uart_info = (struct stm32_uart_info *)dev_get_driver_data(dev); ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) return ret; ret = clk_enable(&clk); if (ret) { dev_err(dev, "failed to enable clock\n"); return ret; } plat->clock_rate = clk_get_rate(&clk); if (plat->clock_rate < 0) { clk_disable(&clk); return plat->clock_rate; }; _stm32_serial_init(plat->base, plat->uart_info); return 0; }
static int at91_i2c_enable_clk(struct udevice *dev) { struct at91_i2c_bus *bus = dev_get_priv(dev); struct clk clk; ulong clk_rate; int ret; ret = clk_get_by_index(dev, 0, &clk); if (ret) return -EINVAL; ret = clk_enable(&clk); if (ret) return ret; clk_rate = clk_get_rate(&clk); if (!clk_rate) return -EINVAL; bus->bus_clk_rate = clk_rate; clk_free(&clk); return 0; }
int zynq_serial_setbrg(struct udevice *dev, int baudrate) { struct zynq_uart_priv *priv = dev_get_priv(dev); unsigned long clock; int ret; struct clk clk; ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) { dev_err(dev, "failed to get clock\n"); return ret; } clock = clk_get_rate(&clk); if (IS_ERR_VALUE(clock)) { dev_err(dev, "failed to get rate\n"); return clock; } debug("%s: CLK %ld\n", __func__, clock); ret = clk_enable(&clk); if (ret && ret != -ENOSYS) { dev_err(dev, "failed to enable clock\n"); return ret; } _uart_zynq_serial_setbrg(priv->regs, clock, baudrate); return 0; }
static int arasan_sdhci_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct rockchip_sdhc_plat *plat = dev_get_platdata(dev); struct rockchip_sdhc *prv = dev_get_priv(dev); struct sdhci_host *host = &prv->host; int max_frequency, ret; struct clk clk; max_frequency = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "max-frequency", 0); ret = clk_get_by_index(dev, 0, &clk); if (!ret) { ret = clk_set_rate(&clk, max_frequency); if (IS_ERR_VALUE(ret)) printf("%s clk set rate fail!\n", __func__); } else { printf("%s fail to get clk\n", __func__); } host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD; host->max_clk = max_frequency; ret = sdhci_setup_cfg(&plat->cfg, host, 0, EMMC_MIN_FREQ); host->mmc = &plat->mmc; if (ret) return ret; host->mmc->priv = &prv->host; host->mmc->dev = dev; upriv->mmc = host->mmc; return sdhci_probe(dev); }
static int atmel_serial_enable_clk(struct udevice *dev) { struct atmel_serial_priv *priv = dev_get_priv(dev); struct clk clk; ulong clk_rate; int ret; ret = clk_get_by_index(dev, 0, &clk); if (ret) return -EINVAL; if (dev_get_driver_data(dev) == CLK_TYPE_NORMAL) { ret = clk_enable(&clk); if (ret) return ret; } clk_rate = clk_get_rate(&clk); if (!clk_rate) return -EINVAL; priv->usart_clk_rate = clk_rate; clk_free(&clk); return 0; }
static int rcar_gpio_probe(struct udevice *dev) { struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct rcar_gpio_priv *priv = dev_get_priv(dev); struct fdtdec_phandle_args args; struct clk clk; int node = dev_of_offset(dev); int ret; priv->regs = (void __iomem *)devfdt_get_addr(dev); uc_priv->bank_name = dev->name; ret = fdtdec_parse_phandle_with_args(gd->fdt_blob, node, "gpio-ranges", NULL, 3, 0, &args); uc_priv->gpio_count = ret == 0 ? args.args[2] : RCAR_MAX_GPIO_PER_BANK; ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) { dev_err(dev, "Failed to get GPIO bank clock\n"); return ret; } ret = clk_enable(&clk); clk_free(&clk); if (ret) { dev_err(dev, "Failed to enable GPIO bank clock\n"); return ret; } return 0; }
static int at91_hlcdc_enable_clk(struct udevice *dev) { struct atmel_hlcdc_priv *priv = dev_get_priv(dev); struct clk clk; ulong clk_rate; int ret; ret = clk_get_by_index(dev, 0, &clk); if (ret) return -EINVAL; ret = clk_enable(&clk); if (ret) return ret; clk_rate = clk_get_rate(&clk); if (!clk_rate) { clk_disable(&clk); return -ENODEV; } priv->clk_rate = clk_rate; clk_free(&clk); return 0; }
static int rockchip_dwmmc_probe(struct udevice *dev) { struct rockchip_mmc_plat *plat = dev_get_platdata(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; struct udevice *pwr_dev __maybe_unused; int ret; #if CONFIG_IS_ENABLED(OF_PLATDATA) struct dtd_rockchip_rk3288_dw_mshc *dtplat = &plat->dtplat; host->name = dev->name; host->ioaddr = map_sysmem(dtplat->reg[0], dtplat->reg[1]); host->buswidth = dtplat->bus_width; host->get_mmc_clk = rockchip_dwmmc_get_mmc_clk; host->priv = dev; host->dev_index = 0; priv->fifo_depth = dtplat->fifo_depth; priv->fifo_mode = 0; priv->minmax[0] = 400000; /* 400 kHz */ priv->minmax[1] = dtplat->max_frequency; ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->clk); if (ret < 0) return ret; #else ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) return ret; #endif host->fifoth_val = MSIZE(0x2) | RX_WMARK(priv->fifo_depth / 2 - 1) | TX_WMARK(priv->fifo_depth / 2); host->fifo_mode = priv->fifo_mode; #ifdef CONFIG_PWRSEQ /* Enable power if needed */ ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", &pwr_dev); if (!ret) { ret = pwrseq_set_power(pwr_dev, true); if (ret) return ret; } #endif dwmci_setup_cfg(&plat->cfg, host, priv->minmax[1], priv->minmax[0]); host->mmc = &plat->mmc; host->mmc->priv = &priv->host; host->mmc->dev = dev; upriv->mmc = host->mmc; return dwmci_probe(dev); }
static int stm32_timer_probe(struct udevice *dev) { struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct stm32_timer_priv *priv = dev_get_priv(dev); struct stm32_timer_regs *regs; struct clk clk; fdt_addr_t addr; int ret; u32 rate, psc; addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; priv->base = (struct stm32_timer_regs *)addr; ret = clk_get_by_index(dev, 0, &clk); if (ret < 0) return ret; ret = clk_enable(&clk); if (ret) { dev_err(dev, "failed to enable clock\n"); return ret; } regs = priv->base; /* Stop the timer */ clrbits_le32(®s->cr1, CR1_CEN); /* get timer clock */ rate = clk_get_rate(&clk); /* we set timer prescaler to obtain a 1MHz timer counter frequency */ psc = (rate / CONFIG_SYS_HZ_CLOCK) - 1; writel(psc, ®s->psc); /* Set timer frequency to 1MHz */ uc_priv->clock_rate = CONFIG_SYS_HZ_CLOCK; /* Configure timer for auto-reload */ setbits_le32(®s->cr1, CR1_ARPE); /* load value for auto reload */ writel(GPT_FREE_RUNNING, ®s->arr); /* start timer */ setbits_le32(®s->cr1, CR1_CEN); /* Update generation */ setbits_le32(®s->egr, EGR_UG); return 0; }
static int k3_arasan_sdhci_probe(struct udevice *dev) { struct k3_arasan_sdhci_plat *plat = dev_get_platdata(dev); struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct sdhci_host *host = dev_get_priv(dev); struct power_domain sdhci_pwrdmn; struct clk clk; unsigned long clock; int ret; ret = power_domain_get_by_index(dev, &sdhci_pwrdmn, 0); if (ret) { dev_err(dev, "failed to get power domain\n"); return ret; } ret = power_domain_on(&sdhci_pwrdmn); if (ret) { dev_err(dev, "Power domain on failed\n"); return ret; } ret = clk_get_by_index(dev, 0, &clk); if (ret) { dev_err(dev, "failed to get clock\n"); return ret; } clock = clk_get_rate(&clk); if (IS_ERR_VALUE(clock)) { dev_err(dev, "failed to get rate\n"); return clock; } host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B; host->max_clk = clock; ret = sdhci_setup_cfg(&plat->cfg, host, plat->f_max, K3_ARASAN_SDHCI_MIN_FREQ); host->mmc = &plat->mmc; if (ret) return ret; host->mmc->priv = host; host->mmc->dev = dev; upriv->mmc = host->mmc; return sdhci_probe(dev); }
static int pic32_spi_probe(struct udevice *bus) { struct pic32_spi_priv *priv = dev_get_priv(bus); struct dm_spi_bus *dm_spi = dev_get_uclass_priv(bus); struct udevice *clkdev; fdt_addr_t addr; fdt_size_t size; int ret; debug("%s: %d, bus: %i\n", __func__, __LINE__, bus->seq); addr = fdtdec_get_addr_size(gd->fdt_blob, bus->of_offset, "reg", &size); if (addr == FDT_ADDR_T_NONE) return -EINVAL; priv->regs = ioremap(addr, size); if (!priv->regs) return -EINVAL; dm_spi->max_hz = fdtdec_get_int(gd->fdt_blob, bus->of_offset, "spi-max-frequency", 250000000); /* get clock rate */ ret = clk_get_by_index(bus, 0, &clkdev); if (ret < 0) { printf("pic32-spi: error, clk not found\n"); return ret; } priv->clk_rate = clk_get_periph_rate(clkdev, ret); /* initialize HW */ pic32_spi_hw_init(priv); /* set word len */ pic32_spi_set_word_size(priv, SPI_DEFAULT_WORDLEN); /* PIC32 SPI controller can automatically drive /CS during transfer * depending on fifo fill-level. /CS will stay asserted as long as * TX fifo is non-empty, else will be deasserted confirming completion * of the ongoing transfer. To avoid this sort of error we will drive * /CS manually by toggling cs-gpio pins. */ ret = gpio_request_by_name_nodev(gd->fdt_blob, bus->of_offset, "cs-gpios", 0, &priv->cs_gpio, GPIOD_IS_OUT); if (ret) { printf("pic32-spi: error, cs-gpios not found\n"); return ret; } return 0; }
static int zynqmp_qspi_probe(struct udevice *bus) { struct zynqmp_qspi_platdata *plat = dev_get_platdata(bus); struct zynqmp_qspi_priv *priv = dev_get_priv(bus); #if !defined(CONFIG_ARCH_VERSAL) struct clk clk; unsigned long clock; int ret; #endif debug("%s: bus:%p, priv:%p\n", __func__, bus, priv); priv->regs = plat->regs; priv->dma_regs = plat->dma_regs; priv->is_dual = plat->is_dual; priv->io_mode = plat->io_mode; if (priv->is_dual == -1) { debug("%s: No QSPI device detected based on MIO settings\n", __func__); return -1; } #if !defined(CONFIG_ARCH_VERSAL) ret = clk_get_by_index(bus, 0, &clk); if (ret < 0) { dev_err(dev, "failed to get clock\n"); return ret; } clock = clk_get_rate(&clk); if (IS_ERR_VALUE(clock)) { dev_err(dev, "failed to get rate\n"); return clock; } debug("%s: CLK %ld\n", __func__, clock); ret = clk_enable(&clk); if (ret && ret != -ENOSYS) { dev_err(dev, "failed to enable clock\n"); return ret; } plat->frequency = clock; plat->speed_hz = plat->frequency; #endif /* init the zynq spi hw */ zynqmp_qspi_init_hw(priv); return 0; }
static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus) { struct rk_i2c *priv = dev_get_priv(bus); int ret; ret = clk_get_by_index(bus, 0, &priv->clk); if (ret < 0) { debug("%s: Could not get clock for %s: %d\n", __func__, bus->name, ret); return ret; } return 0; }
int clk_get_by_name(struct udevice *dev, const char *name, struct clk *clk) { int index; debug("%s(dev=%p, name=%s, clk=%p)\n", __func__, dev, name, clk); index = fdt_stringlist_search(gd->fdt_blob, dev_of_offset(dev), "clock-names", name); if (index < 0) { debug("fdt_stringlist_search() failed: %d\n", index); return index; } return clk_get_by_index(dev, index, clk); }
static int rockchip_dwmmc_probe(struct udevice *dev) { struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev); struct rockchip_dwmmc_priv *priv = dev_get_priv(dev); struct dwmci_host *host = &priv->host; struct udevice *pwr_dev __maybe_unused; u32 minmax[2]; int ret; int fifo_depth; ret = clk_get_by_index(dev, 0, &priv->clk); if (ret < 0) return ret; priv->periph = ret; if (fdtdec_get_int_array(gd->fdt_blob, dev->of_offset, "clock-freq-min-max", minmax, 2)) return -EINVAL; fifo_depth = fdtdec_get_int(gd->fdt_blob, dev->of_offset, "fifo-depth", 0); if (fifo_depth < 0) return -EINVAL; host->fifoth_val = MSIZE(0x2) | RX_WMARK(fifo_depth / 2 - 1) | TX_WMARK(fifo_depth / 2); if (fdtdec_get_bool(gd->fdt_blob, dev->of_offset, "fifo-mode")) host->fifo_mode = true; #ifdef CONFIG_PWRSEQ /* Enable power if needed */ ret = uclass_get_device_by_phandle(UCLASS_PWRSEQ, dev, "mmc-pwrseq", &pwr_dev); if (!ret) { ret = pwrseq_set_power(pwr_dev, true); if (ret) return ret; } #endif ret = add_dwmci(host, minmax[1], minmax[0]); if (ret) return ret; upriv->mmc = host->mmc; return 0; }
DEBUG_UART_FUNCS #endif #if CONFIG_IS_ENABLED(DM_SERIAL) #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) static int omap_serial_ofdata_to_platdata(struct udevice *dev) { struct ns16550_platdata *plat = dev->platdata; fdt_addr_t addr; struct clk clk; int err; /* try Processor Local Bus device first */ addr = dev_read_addr(dev); if (addr == FDT_ADDR_T_NONE) return -EINVAL; plat->base = (unsigned long)map_physmem(addr, 0, MAP_NOCACHE); plat->reg_offset = dev_read_u32_default(dev, "reg-offset", 0); plat->reg_shift = 2; err = clk_get_by_index(dev, 0, &clk); if (!err) { err = clk_get_rate(&clk); if (!IS_ERR_VALUE(err)) plat->clock = err; } else if (err != -ENOENT && err != -ENODEV && err != -ENOSYS) { debug("omap serial failed to get clock\n"); return err; } if (!plat->clock) plat->clock = dev_read_u32_default(dev, "clock-frequency", CONFIG_SYS_NS16550_CLK); if (!plat->clock) { debug("omap serial clock not defined\n"); return -EINVAL; } plat->fcr = UART_FCR_DEFVAL; return 0; }
int rockchip_saradc_probe(struct udevice *dev) { struct rockchip_saradc_priv *priv = dev_get_priv(dev); struct clk clk; int ret; ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; ret = clk_set_rate(&clk, priv->data->clk_rate); if (IS_ERR_VALUE(ret)) return ret; priv->active_channel = -1; return 0; }
static ulong periph_get_rate(struct clk *clk) { struct udevice *dev; struct clk clk_dev; ulong clk_rate; int ret; dev = dev_get_parent(clk->dev); ret = clk_get_by_index(dev, 0, &clk_dev); if (ret) return ret; clk_rate = clk_get_rate(&clk_dev); clk_free(&clk_dev); return clk_rate; }
static int denali_dt_probe(struct udevice *dev) { struct denali_nand_info *denali = dev_get_priv(dev); const struct denali_dt_data *data; struct clk clk; struct resource res; int ret; data = (void *)dev_get_driver_data(dev); if (data) { denali->revision = data->revision; denali->caps = data->caps; denali->ecc_caps = data->ecc_caps; } denali->dev = dev; ret = dev_read_resource_byname(dev, "denali_reg", &res); if (ret) return ret; denali->reg = devm_ioremap(dev, res.start, resource_size(&res)); ret = dev_read_resource_byname(dev, "nand_data", &res); if (ret) return ret; denali->host = devm_ioremap(dev, res.start, resource_size(&res)); ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; ret = clk_enable(&clk); if (ret) return ret; denali->clk_x_rate = clk_get_rate(&clk); return denali_init(denali); }
static int timer_pre_probe(struct udevice *dev) { #if !CONFIG_IS_ENABLED(OF_PLATDATA) struct timer_dev_priv *uc_priv = dev_get_uclass_priv(dev); struct clk timer_clk; int err; ulong ret; err = clk_get_by_index(dev, 0, &timer_clk); if (!err) { ret = clk_get_rate(&timer_clk); if (IS_ERR_VALUE(ret)) return ret; uc_priv->clock_rate = ret; } else uc_priv->clock_rate = fdtdec_get_int(gd->fdt_blob, dev_of_offset(dev), "clock-frequency", 0); #endif return 0; }
static int stm32_qspi_probe(struct udevice *bus) { struct stm32_qspi_platdata *plat = dev_get_platdata(bus); struct stm32_qspi_priv *priv = dev_get_priv(bus); struct dm_spi_bus *dm_spi_bus; dm_spi_bus = bus->uclass_priv; dm_spi_bus->max_hz = plat->max_hz; priv->regs = (struct stm32_qspi_regs *)(uintptr_t)plat->base; priv->max_hz = plat->max_hz; #ifdef CONFIG_CLK int ret; struct clk clk; ret = clk_get_by_index(bus, 0, &clk); if (ret < 0) return ret; ret = clk_enable(&clk); if (ret) { dev_err(bus, "failed to enable clock\n"); return ret; } priv->clock_rate = clk_get_rate(&clk); if (priv->clock_rate < 0) { clk_disable(&clk); return priv->clock_rate; } #endif setbits_le32(&priv->regs->cr, STM32_QSPI_CR_SSHIFT); return 0; }
int s5p_serial_setbrg(struct udevice *dev, int baudrate) { struct s5p_serial_platdata *plat = dev->platdata; struct s5p_uart *const uart = plat->reg; u32 uclk; #ifdef CONFIG_CLK_EXYNOS struct clk clk; u32 ret; ret = clk_get_by_index(dev, 1, &clk); if (ret < 0) return ret; uclk = clk_get_rate(&clk); #else uclk = get_uart_clk(plat->port_id); #endif s5p_serial_baud(uart, uclk, baudrate); return 0; }
static int macb_enable_clk(struct udevice *dev) { struct macb_device *macb = dev_get_priv(dev); struct clk clk; ulong clk_rate; int ret; ret = clk_get_by_index(dev, 0, &clk); if (ret) return -EINVAL; ret = clk_enable(&clk); if (ret) return ret; clk_rate = clk_get_rate(&clk); if (!clk_rate) return -EINVAL; macb->pclk_rate = clk_rate; return 0; }
static int rk3288_clk_config(struct udevice *dev) { struct display_plat *uc_plat = dev_get_uclass_platdata(dev); struct clk clk; int ret; /* * Configure the maximum clock to permit whatever resolution the * monitor wants */ ret = clk_get_by_index(uc_plat->src_dev, 0, &clk); if (ret >= 0) { ret = clk_set_rate(&clk, 384000000); clk_free(&clk); } if (ret < 0) { debug("%s: Failed to set clock in source device '%s': ret=%d\n", __func__, uc_plat->src_dev->name, ret); return ret; } return 0; }
static int cdns_i2c_ofdata_to_platdata(struct udevice *dev) { struct i2c_cdns_bus *i2c_bus = dev_get_priv(dev); struct cdns_i2c_platform_data *pdata = (struct cdns_i2c_platform_data *)dev_get_driver_data(dev); struct clk clk; int ret; i2c_bus->regs = (struct cdns_i2c_regs *)dev_read_addr(dev); if (!i2c_bus->regs) return -ENOMEM; if (pdata) i2c_bus->quirks = pdata->quirks; ret = clk_get_by_index(dev, 0, &clk); if (ret) return ret; i2c_bus->input_freq = clk_get_rate(&clk); return 0; }