/* set up the UTMI USB controller with the parameters provided */ static int init_utmi_usb_controller(struct fdt_usb *config) { u32 val; int loop_count; const unsigned *timing; struct usb_ctlr *usbctlr = config->reg; struct clk_rst_ctlr *clkrst; struct usb_ctlr *usb1ctlr; clock_enable(config->periph_id); /* Reset the usb controller */ usbf_reset_controller(config, usbctlr); /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */ clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); /* Follow the crystal clock disable by >100ns delay */ udelay(1); /* * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP * mux must be switched to actually use a_sess_vld threshold. */ if (config->dr_mode == DR_MODE_OTG && fdt_gpio_isvalid(&config->vbus_gpio)) clrsetbits_le32(&usbctlr->usb1_legacy_ctrl, VBUS_SENSE_CTL_MASK, VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT); /* * PLL Delay CONFIGURATION settings. The following parameters control * the bring up of the plls. */ timing = get_pll_timing(); if (!controller->has_hostpc) { val = readl(&usbctlr->utmip_misc_cfg1); clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, timing[PARAM_ACTIVE_DELAY_COUNT] << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); writel(val, &usbctlr->utmip_misc_cfg1); /* Set PLL enable delay count and crystal frequency count */ val = readl(&usbctlr->utmip_pll_cfg1); clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, timing[PARAM_ENABLE_DELAY_COUNT] << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, timing[PARAM_XTAL_FREQ_COUNT] << UTMIP_XTAL_FREQ_COUNT_SHIFT); writel(val, &usbctlr->utmip_pll_cfg1); } else { clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE; val = readl(&clkrst->crc_utmip_pll_cfg2); clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK, timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT); clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK, timing[PARAM_ACTIVE_DELAY_COUNT] << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT); writel(val, &clkrst->crc_utmip_pll_cfg2); /* Set PLL enable delay count and crystal frequency count */ val = readl(&clkrst->crc_utmip_pll_cfg1); clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK, timing[PARAM_ENABLE_DELAY_COUNT] << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT); clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK, timing[PARAM_XTAL_FREQ_COUNT] << UTMIP_XTAL_FREQ_COUNT_SHIFT); writel(val, &clkrst->crc_utmip_pll_cfg1); /* Disable Power Down state for PLL */ clrbits_le32(&clkrst->crc_utmip_pll_cfg1, PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN | PLL_ACTIVE_POWERDOWN); /* Recommended PHY settings for EYE diagram */ val = readl(&usbctlr->utmip_xcvr_cfg0); clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK, 0x4 << UTMIP_XCVR_SETUP_SHIFT); clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK, 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT); clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK, 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT); writel(val, &usbctlr->utmip_xcvr_cfg0); clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_XCVR_TERM_RANGE_ADJ_MASK, 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT); /* Some registers can be controlled from USB1 only. */ if (config->periph_id != PERIPH_ID_USBD) { clock_enable(PERIPH_ID_USBD); /* Disable Reset if in Reset state */ reset_set_enable(PERIPH_ID_USBD, 0); } usb1ctlr = (struct usb_ctlr *) ((u32)config->reg & USB1_ADDR_MASK); val = readl(&usb1ctlr->utmip_bias_cfg0); setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB); clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK, 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT); clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK, 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT); writel(val, &usb1ctlr->utmip_bias_cfg0); /* Miscellaneous setting mentioned in Programming Guide */ clrbits_le32(&usbctlr->utmip_misc_cfg0, UTMIP_SUSPEND_EXIT_ON_EDGE); } /* Setting the tracking length time */ clrsetbits_le32(&usbctlr->utmip_bias_cfg1, UTMIP_BIAS_PDTRK_COUNT_MASK, timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT); /* Program debounce time for VBUS to become valid */ clrsetbits_le32(&usbctlr->utmip_debounce_cfg0, UTMIP_DEBOUNCE_CFG0_MASK, timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT); setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J); /* Disable battery charge enabling bit */ setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG); clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE); setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL); /* * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT * Setting these fields, together with default values of the * other fields, results in programming the registers below as * follows: * UTMIP_HSRX_CFG0 = 0x9168c000 * UTMIP_HSRX_CFG1 = 0x13 */ /* Set PLL enable delay count and Crystal frequency count */ val = readl(&usbctlr->utmip_hsrx_cfg0); clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK, utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT); clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK, utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT); writel(val, &usbctlr->utmip_hsrx_cfg0); /* Configure the UTMIP_HS_SYNC_START_DLY */ clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1, UTMIP_HS_SYNC_START_DLY_MASK, utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT); /* Preceed the crystal clock disable by >100ns delay. */ udelay(1); /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */ setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN); if (controller->has_hostpc) { if (config->periph_id == PERIPH_ID_USBD) clrbits_le32(&clkrst->crc_utmip_pll_cfg2, UTMIP_FORCE_PD_SAMP_A_POWERDOWN); if (config->periph_id == PERIPH_ID_USB3) clrbits_le32(&clkrst->crc_utmip_pll_cfg2, UTMIP_FORCE_PD_SAMP_C_POWERDOWN); } /* Finished the per-controller init. */ /* De-assert UTMIP_RESET to bring out of reset. */ clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET); /* Wait for the phy clock to become valid in 100 ms */ for (loop_count = 100000; loop_count != 0; loop_count--) { if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) break; udelay(1); } if (!loop_count) return -1; /* Disable ICUSB FS/LS transceiver */ clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1); /* Select UTMI parallel interface */ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_UTMI << PTS_SHIFT); clrbits_le32(&usbctlr->port_sc1, STS); /* Deassert power down state */ clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN | UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN); clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN | UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN); if (controller->has_hostpc) { /* * BIAS Pad Power Down is common among all 3 USB * controllers and can be controlled from USB1 only. */ usb1ctlr = (struct usb_ctlr *) ((u32)config->reg & USB1_ADDR_MASK); clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD); udelay(25); clrbits_le32(&usb1ctlr->utmip_bias_cfg1, UTMIP_FORCE_PDTRK_POWERDOWN); } return 0; }
static void setup_non_essential_dplls(void) { u32 sys_clk_khz, abe_ref_clk; u32 sysclk_ind, sd_div, num, den; const struct dpll_params *params; sysclk_ind = get_sys_clk_index(); sys_clk_khz = get_sys_clk_freq() / 1000; /* IVA */ clrsetbits_le32(&prcm->cm_bypclk_dpll_iva, CM_BYPCLK_DPLL_IVA_CLKSEL_MASK, DPLL_IVA_CLKSEL_CORE_X2_DIV_2); do_setup_dpll(&prcm->cm_clkmode_dpll_iva, &iva_dpll_params_1862mhz[sysclk_ind], DPLL_LOCK); /* * USB: * USB dpll is J-type. Need to set DPLL_SD_DIV for jitter correction * DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)]* CLKINP / 250) * - where CLKINP is sys_clk in MHz * Use CLKINP in KHz and adjust the denominator accordingly so * that we have enough accuracy and at the same time no overflow */ params = &usb_dpll_params_1920mhz[sysclk_ind]; num = params->m * sys_clk_khz; den = (params->n + 1) * 250 * 1000; num += den - 1; sd_div = num / den; clrsetbits_le32(&prcm->cm_clksel_dpll_usb, CM_CLKSEL_DPLL_DPLL_SD_DIV_MASK, sd_div << CM_CLKSEL_DPLL_DPLL_SD_DIV_SHIFT); /* Now setup the dpll with the regular function */ do_setup_dpll(&prcm->cm_clkmode_dpll_usb, params, DPLL_LOCK); #ifdef CONFIG_SYS_OMAP4_ABE_SYSCK params = &abe_dpll_params_sysclk_196608khz[sysclk_ind]; abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_SYSCLK; #else params = &abe_dpll_params_32k_196608khz; abe_ref_clk = CM_ABE_PLL_REF_CLKSEL_CLKSEL_32KCLK; /* * We need to enable some additional options to achieve * 196.608MHz from 32768 Hz */ setbits_le32(&prcm->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_DRIFTGUARD_EN_MASK| CM_CLKMODE_DPLL_RELOCK_RAMP_EN_MASK| CM_CLKMODE_DPLL_LPMODE_EN_MASK| CM_CLKMODE_DPLL_REGM4XEN_MASK); /* Spend 4 REFCLK cycles at each stage */ clrsetbits_le32(&prcm->cm_clkmode_dpll_abe, CM_CLKMODE_DPLL_RAMP_RATE_MASK, 1 << CM_CLKMODE_DPLL_RAMP_RATE_SHIFT); #endif /* Select the right reference clk */ clrsetbits_le32(&prcm->cm_abe_pll_ref_clksel, CM_ABE_PLL_REF_CLKSEL_CLKSEL_MASK, abe_ref_clk << CM_ABE_PLL_REF_CLKSEL_CLKSEL_SHIFT); /* Lock the dpll */ do_setup_dpll(&prcm->cm_clkmode_dpll_abe, params, DPLL_LOCK); }
/* * Enable non-essential clock domains, modules and * do some additional special settings needed */ static void enable_non_essential_clocks(void) { u32 i, max = 100, wait_for_enable = 0; u32 *const clk_domains_non_essential[] = { &prcm->cm_mpu_m3_clkstctrl, &prcm->cm_ivahd_clkstctrl, &prcm->cm_dsp_clkstctrl, &prcm->cm_dss_clkstctrl, &prcm->cm_sgx_clkstctrl, &prcm->cm1_abe_clkstctrl, &prcm->cm_c2c_clkstctrl, &prcm->cm_cam_clkstctrl, &prcm->cm_dss_clkstctrl, &prcm->cm_sdma_clkstctrl, 0 }; u32 *const clk_modules_hw_auto_non_essential[] = { &prcm->cm_mpu_m3_mpu_m3_clkctrl, &prcm->cm_ivahd_ivahd_clkctrl, &prcm->cm_ivahd_sl2_clkctrl, &prcm->cm_dsp_dsp_clkctrl, &prcm->cm_l3_2_gpmc_clkctrl, &prcm->cm_l3instr_l3_3_clkctrl, &prcm->cm_l3instr_l3_instr_clkctrl, &prcm->cm_l3instr_intrconn_wp1_clkctrl, &prcm->cm_l3init_hsi_clkctrl, &prcm->cm_l3init_hsusbtll_clkctrl, 0 }; u32 *const clk_modules_explicit_en_non_essential[] = { &prcm->cm1_abe_aess_clkctrl, &prcm->cm1_abe_pdm_clkctrl, &prcm->cm1_abe_dmic_clkctrl, &prcm->cm1_abe_mcasp_clkctrl, &prcm->cm1_abe_mcbsp1_clkctrl, &prcm->cm1_abe_mcbsp2_clkctrl, &prcm->cm1_abe_mcbsp3_clkctrl, &prcm->cm1_abe_slimbus_clkctrl, &prcm->cm1_abe_timer5_clkctrl, &prcm->cm1_abe_timer6_clkctrl, &prcm->cm1_abe_timer7_clkctrl, &prcm->cm1_abe_timer8_clkctrl, &prcm->cm1_abe_wdt3_clkctrl, &prcm->cm_l4per_gptimer9_clkctrl, &prcm->cm_l4per_gptimer10_clkctrl, &prcm->cm_l4per_gptimer11_clkctrl, &prcm->cm_l4per_gptimer3_clkctrl, &prcm->cm_l4per_gptimer4_clkctrl, &prcm->cm_l4per_hdq1w_clkctrl, &prcm->cm_l4per_mcbsp4_clkctrl, &prcm->cm_l4per_mcspi2_clkctrl, &prcm->cm_l4per_mcspi3_clkctrl, &prcm->cm_l4per_mcspi4_clkctrl, &prcm->cm_l4per_mmcsd3_clkctrl, &prcm->cm_l4per_mmcsd4_clkctrl, &prcm->cm_l4per_mmcsd5_clkctrl, &prcm->cm_l4per_uart1_clkctrl, &prcm->cm_l4per_uart2_clkctrl, &prcm->cm_l4per_uart4_clkctrl, &prcm->cm_wkup_keyboard_clkctrl, &prcm->cm_wkup_wdtimer2_clkctrl, &prcm->cm_cam_iss_clkctrl, &prcm->cm_cam_fdif_clkctrl, &prcm->cm_dss_dss_clkctrl, &prcm->cm_sgx_sgx_clkctrl, &prcm->cm_l3init_hsusbhost_clkctrl, &prcm->cm_l3init_fsusb_clkctrl, 0 }; /* Enable optional functional clock for ISS */ setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); /* Enable all optional functional clocks of DSS */ setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); /* Put the clock domains in SW_WKUP mode */ for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { enable_clock_domain(clk_domains_non_essential[i], CD_CLKCTRL_CLKTRCTRL_SW_WKUP); } /* Clock modules that need to be put in HW_AUTO */ for (i = 0; (i < max) && clk_modules_hw_auto_non_essential[i]; i++) { enable_clock_module(clk_modules_hw_auto_non_essential[i], MODULE_CLKCTRL_MODULEMODE_HW_AUTO, wait_for_enable); }; /* Clock modules that need to be put in SW_EXPLICIT_EN mode */ for (i = 0; (i < max) && clk_modules_explicit_en_non_essential[i]; i++) { enable_clock_module(clk_modules_explicit_en_non_essential[i], MODULE_CLKCTRL_MODULEMODE_SW_EXPLICIT_EN, wait_for_enable); }; /* Put the clock domains in HW_AUTO mode now */ for (i = 0; (i < max) && clk_domains_non_essential[i]; i++) { enable_clock_domain(clk_domains_non_essential[i], CD_CLKCTRL_CLKTRCTRL_HW_AUTO); } /* Put camera module in no sleep mode */ clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << MODULE_CLKCTRL_MODULEMODE_SHIFT); }
static int _spi_xfer(struct kwspi_registers *reg, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { unsigned int tmpdout, tmpdin; int tm, isread = 0; debug("spi_xfer: dout %p din %p bitlen %u\n", dout, din, bitlen); if (flags & SPI_XFER_BEGIN) _spi_cs_activate(reg); /* * handle data in 8-bit chunks * TBD: 2byte xfer mode to be enabled */ clrsetbits_le32(®->cfg, KWSPI_XFERLEN_MASK, KWSPI_XFERLEN_1BYTE); while (bitlen > 4) { debug("loopstart bitlen %d\n", bitlen); tmpdout = 0; /* Shift data so it's msb-justified */ if (dout) tmpdout = *(u32 *)dout & 0xff; clrbits_le32(®->irq_cause, KWSPI_SMEMRDIRQ); writel(tmpdout, ®->dout); /* Write the data out */ debug("*** spi_xfer: ... %08x written, bitlen %d\n", tmpdout, bitlen); /* * Wait for SPI transmit to get out * or time out (1 second = 1000 ms) * The NE event must be read and cleared first */ for (tm = 0, isread = 0; tm < KWSPI_TIMEOUT; ++tm) { if (readl(®->irq_cause) & KWSPI_SMEMRDIRQ) { isread = 1; tmpdin = readl(®->din); debug("spi_xfer: din %p..%08x read\n", din, tmpdin); if (din) { *((u8 *)din) = (u8)tmpdin; din += 1; } if (dout) dout += 1; bitlen -= 8; } if (isread) break; } if (tm >= KWSPI_TIMEOUT) printf("*** spi_xfer: Time out during SPI transfer\n"); debug("loopend bitlen %d\n", bitlen); } if (flags & SPI_XFER_END) _spi_cs_deactivate(reg); return 0; }
static void mxs_power_init_4p2_regulator(void) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp, tmp2; setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_4P2); writel(POWER_CHARGE_ENABLE_LOAD, &power_regs->hw_power_charge_set); writel(POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, &power_regs->hw_power_5vctrl_clr); clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_TRG_MASK); /* Power up the 4p2 rail and logic/control */ writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, &power_regs->hw_power_5vctrl_clr); /* * Start charging up the 4p2 capacitor. We ramp of this charge * gradually to avoid large inrush current from the 5V cable which can * cause transients/problems */ mxs_enable_4p2_dcdc_input(0); if (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) { /* * If we arrived here, we were unable to recover from mx23 chip * errata 5837. 4P2 is disabled and sufficient battery power is * not present. Exiting to not enable DCDC power during 5V * connected state. */ clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_DCDC); writel(POWER_5VCTRL_PWD_CHARGE_4P2_MASK, &power_regs->hw_power_5vctrl_set); hang(); } /* * Here we set the 4p2 brownout level to something very close to 4.2V. * We then check the brownout status. If the brownout status is false, * the voltage is already close to the target voltage of 4.2V so we * can go ahead and set the 4P2 current limit to our max target limit. * If the brownout status is true, we need to ramp us the current limit * so that we don't cause large inrush current issues. We step up the * current limit until the brownout status is false or until we've * reached our maximum defined 4p2 current limit. */ clrsetbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK, 22 << POWER_DCDC4P2_BO_OFFSET); /* 4.15V */ if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) { setbits_le32(&power_regs->hw_power_5vctrl, 0x3f << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); } else { tmp = (readl(&power_regs->hw_power_5vctrl) & POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK) >> POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; while (tmp < 0x3f) { if (!(readl(&power_regs->hw_power_sts) & POWER_STS_DCDC_4P2_BO)) { tmp = readl(&power_regs->hw_power_5vctrl); tmp |= POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; early_delay(100); writel(tmp, &power_regs->hw_power_5vctrl); break; } else { tmp++; tmp2 = readl(&power_regs->hw_power_5vctrl); tmp2 &= ~POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK; tmp2 |= tmp << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET; writel(tmp2, &power_regs->hw_power_5vctrl); early_delay(100); } } } clrbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_BO_MASK); writel(POWER_CTRL_DCDC4P2_BO_IRQ, &power_regs->hw_power_ctrl_clr); }
static void fsl_xhci_set_beat_burst_length(struct dwc3 *dwc3_reg) { clrsetbits_le32(&dwc3_reg->g_sbuscfg0, USB3_ENABLE_BEAT_BURST_MASK, USB3_ENABLE_BEAT_BURST); setbits_le32(&dwc3_reg->g_sbuscfg1, USB3_SET_BEAT_BURST_LIMIT); }
static void dpll3_init_36xx(u32 sil_index, u32 clk_index) { struct prcm *prcm_base = (struct prcm *)PRCM_BASE; dpll_param *ptr = (dpll_param *) get_36x_core_dpll_param(); void (*f_lock_pll) (u32, u32, u32, u32); int xip_safe, p0, p1, p2, p3; xip_safe = is_running_in_sram(); /* Moving it to the right sysclk base */ ptr += clk_index; if (xip_safe) { /* CORE DPLL */ /* Select relock bypass: CM_CLKEN_PLL[0:2] */ clrsetbits_le32(&prcm_base->clken_pll, 0x00000007, PLL_FAST_RELOCK_BYPASS); wait_on_value(ST_CORE_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); /* CM_CLKSEL1_EMU[DIV_DPLL3] */ clrsetbits_le32(&prcm_base->clksel1_emu, 0x001F0000, CORE_M3X2 << 16); /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ clrsetbits_le32(&prcm_base->clksel1_pll, 0xF8000000, ptr->m2 << 27); /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ clrsetbits_le32(&prcm_base->clksel1_pll, 0x07FF0000, ptr->m << 16); /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ clrsetbits_le32(&prcm_base->clksel1_pll, 0x00007F00, ptr->n << 8); /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ clrbits_le32(&prcm_base->clksel1_pll, 0x00000040); /* SSI */ clrsetbits_le32(&prcm_base->clksel_core, 0x00000F00, CORE_SSI_DIV << 8); /* FSUSB */ clrsetbits_le32(&prcm_base->clksel_core, 0x00000030, CORE_FUSB_DIV << 4); /* L4 */ clrsetbits_le32(&prcm_base->clksel_core, 0x0000000C, CORE_L4_DIV << 2); /* L3 */ clrsetbits_le32(&prcm_base->clksel_core, 0x00000003, CORE_L3_DIV); /* GFX */ clrsetbits_le32(&prcm_base->clksel_gfx, 0x00000007, GFX_DIV_36X); /* RESET MGR */ clrsetbits_le32(&prcm_base->clksel_wkup, 0x00000006, WKUP_RSM << 1); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ clrsetbits_le32(&prcm_base->clken_pll, 0x000000F0, ptr->fsel << 4); /* LOCK MODE */ clrsetbits_le32(&prcm_base->clken_pll, 0x00000007, PLL_LOCK); wait_on_value(ST_CORE_CLK, 1, &prcm_base->idlest_ckgen, LDELAY); } else if (is_running_in_flash()) { /* * if running from flash, jump to small relocated code * area in SRAM. */ f_lock_pll = (void *) (SRAM_CLK_CODE); p0 = readl(&prcm_base->clken_pll); clrsetbits_le32(&p0, 0x00000007, PLL_FAST_RELOCK_BYPASS); /* FREQSEL (CORE_DPLL_FREQSEL): CM_CLKEN_PLL[4:7] */ clrsetbits_le32(&p0, 0x000000F0, ptr->fsel << 4); p1 = readl(&prcm_base->clksel1_pll); /* M2 (CORE_DPLL_CLKOUT_DIV): CM_CLKSEL1_PLL[27:31] */ clrsetbits_le32(&p1, 0xF8000000, ptr->m2 << 27); /* M (CORE_DPLL_MULT): CM_CLKSEL1_PLL[16:26] */ clrsetbits_le32(&p1, 0x07FF0000, ptr->m << 16); /* N (CORE_DPLL_DIV): CM_CLKSEL1_PLL[8:14] */ clrsetbits_le32(&p1, 0x00007F00, ptr->n << 8); /* Source is the CM_96M_FCLK: CM_CLKSEL1_PLL[6] */ clrbits_le32(&p1, 0x00000040); p2 = readl(&prcm_base->clksel_core); /* SSI */ clrsetbits_le32(&p2, 0x00000F00, CORE_SSI_DIV << 8); /* FSUSB */ clrsetbits_le32(&p2, 0x00000030, CORE_FUSB_DIV << 4); /* L4 */ clrsetbits_le32(&p2, 0x0000000C, CORE_L4_DIV << 2); /* L3 */ clrsetbits_le32(&p2, 0x00000003, CORE_L3_DIV); p3 = (u32)&prcm_base->idlest_ckgen; (*f_lock_pll) (p0, p1, p2, p3); } }
static void mctl_itm_disable(void) { struct sunxi_dram_reg *dram = (struct sunxi_dram_reg *)SUNXI_DRAMC_BASE; clrsetbits_le32(&dram->ccr, DRAM_CCR_INIT, DRAM_CCR_ITM_OFF); }
static inline void do_lock_dpll(const struct dpll_regs *dpll_regs) { clrsetbits_le32(dpll_regs->cm_clkmode_dpll, CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_LOCK << CM_CLKMODE_DPLL_EN_SHIFT); }
static int stm32_fmc_ofdata_to_platdata(struct udevice *dev) { struct stm32_sdram_params *params = dev_get_platdata(dev); struct bank_params *bank_params; struct ofnode_phandle_args args; u32 *syscfg_base; u32 mem_remap; u32 swp_fmc; ofnode bank_node; char *bank_name; u8 bank = 0; int ret; ret = dev_read_phandle_with_args(dev, "st,syscfg", NULL, 0, 0, &args); if (ret) { dev_dbg(dev, "%s: can't find syscon device (%d)\n", __func__, ret); } else { syscfg_base = (u32 *)ofnode_get_addr(args.node); mem_remap = dev_read_u32_default(dev, "st,mem_remap", NOT_FOUND); if (mem_remap != NOT_FOUND) { /* set memory mapping selection */ clrsetbits_le32(syscfg_base, MEM_MODE_MASK, mem_remap); } else { dev_dbg(dev, "%s: cannot find st,mem_remap property\n", __func__); } swp_fmc = dev_read_u32_default(dev, "st,swp_fmc", NOT_FOUND); if (swp_fmc != NOT_FOUND) { /* set fmc swapping selection */ clrsetbits_le32(syscfg_base, SWP_FMC_MASK, swp_fmc << SWP_FMC_OFFSET); } else { dev_dbg(dev, "%s: cannot find st,swp_fmc property\n", __func__); } dev_dbg(dev, "syscfg %x = %x\n", (u32)syscfg_base, *syscfg_base); } dev_for_each_subnode(bank_node, dev) { /* extract the bank index from DT */ bank_name = (char *)ofnode_get_name(bank_node); strsep(&bank_name, "@"); if (!bank_name) { pr_err("missing sdram bank index"); return -EINVAL; } bank_params = ¶ms->bank_params[bank]; strict_strtoul(bank_name, 10, (long unsigned int *)&bank_params->target_bank); if (bank_params->target_bank >= MAX_SDRAM_BANK) { pr_err("Found bank %d , but only bank 0 and 1 are supported", bank_params->target_bank); return -EINVAL; } debug("Find bank %s %u\n", bank_name, bank_params->target_bank); params->bank_params[bank].sdram_control = (struct stm32_sdram_control *) ofnode_read_u8_array_ptr(bank_node, "st,sdram-control", sizeof(struct stm32_sdram_control)); if (!params->bank_params[bank].sdram_control) { pr_err("st,sdram-control not found for %s", ofnode_get_name(bank_node)); return -EINVAL; } params->bank_params[bank].sdram_timing = (struct stm32_sdram_timing *) ofnode_read_u8_array_ptr(bank_node, "st,sdram-timing", sizeof(struct stm32_sdram_timing)); if (!params->bank_params[bank].sdram_timing) { pr_err("st,sdram-timing not found for %s", ofnode_get_name(bank_node)); return -EINVAL; } bank_params->sdram_ref_count = ofnode_read_u32_default(bank_node, "st,sdram-refcount", 8196); bank++; }
void power_enable_xclkout(void) { /* use xxti for xclk out */ clrsetbits_le32(&exynos_power->pmu_debug, PMU_DEBUG_CLKOUT_SEL_MASK, PMU_DEBUG_XXTI); }
static int tegra30_spi_xfer(struct udevice *dev, unsigned int bitlen, const void *data_out, void *data_in, unsigned long flags) { struct udevice *bus = dev->parent; struct tegra30_spi_priv *priv = dev_get_priv(bus); struct spi_regs *regs = priv->regs; u32 reg, tmpdout, tmpdin = 0; const u8 *dout = data_out; u8 *din = data_in; int num_bytes; int ret; debug("%s: slave %u:%u dout %p din %p bitlen %u\n", __func__, bus->seq, spi_chip_select(dev), dout, din, bitlen); if (bitlen % 8) return -1; num_bytes = bitlen / 8; ret = 0; reg = readl(®s->status); writel(reg, ®s->status); /* Clear all SPI events via R/W */ debug("%s entry: STATUS = %08x\n", __func__, reg); reg = readl(®s->status2); writel(reg, ®s->status2); /* Clear all STATUS2 events via R/W */ debug("%s entry: STATUS2 = %08x\n", __func__, reg); debug("%s entry: COMMAND = %08x\n", __func__, readl(®s->command)); clrsetbits_le32(®s->command2, SLINK_CMD2_SS_EN_MASK, SLINK_CMD2_TXEN | SLINK_CMD2_RXEN | (spi_chip_select(dev) << SLINK_CMD2_SS_EN_SHIFT)); debug("%s entry: COMMAND2 = %08x\n", __func__, readl(®s->command2)); if (flags & SPI_XFER_BEGIN) spi_cs_activate(dev); /* handle data in 32-bit chunks */ while (num_bytes > 0) { int bytes; int is_read = 0; int tm, i; tmpdout = 0; bytes = (num_bytes > 4) ? 4 : num_bytes; if (dout != NULL) { for (i = 0; i < bytes; ++i) tmpdout = (tmpdout << 8) | dout[i]; dout += bytes; } num_bytes -= bytes; clrsetbits_le32(®s->command, SLINK_CMD_BIT_LENGTH_MASK, bytes * 8 - 1); writel(tmpdout, ®s->tx_fifo); setbits_le32(®s->command, SLINK_CMD_GO); /* * Wait for SPI transmit FIFO to empty, or to time out. * The RX FIFO status will be read and cleared last */ for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) { u32 status; status = readl(®s->status); /* We can exit when we've had both RX and TX activity */ if (is_read && (status & SLINK_STAT_TXF_EMPTY)) break; if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) != SLINK_STAT_RDY) tm++; else if (!(status & SLINK_STAT_RXF_EMPTY)) { tmpdin = readl(®s->rx_fifo); is_read = 1; /* swap bytes read in */ if (din != NULL) { for (i = bytes - 1; i >= 0; --i) { din[i] = tmpdin & 0xff; tmpdin >>= 8; } din += bytes; } } } if (tm >= SPI_TIMEOUT) ret = tm; /* clear ACK RDY, etc. bits */ writel(readl(®s->status), ®s->status); }
void rkvop_mode_set(struct rk3288_vop *regs, const struct display_timing *edid, enum vop_modes mode) { u32 hactive = edid->hactive.typ; u32 vactive = edid->vactive.typ; u32 hsync_len = edid->hsync_len.typ; u32 hback_porch = edid->hback_porch.typ; u32 vsync_len = edid->vsync_len.typ; u32 vback_porch = edid->vback_porch.typ; u32 hfront_porch = edid->hfront_porch.typ; u32 vfront_porch = edid->vfront_porch.typ; uint flags; int mode_flags; switch (mode) { case VOP_MODE_HDMI: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_HDMI_OUT_EN(1)); break; case VOP_MODE_EDP: default: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_EDP_OUT_EN(1)); break; case VOP_MODE_LVDS: clrsetbits_le32(®s->sys_ctrl, M_ALL_OUT_EN, V_RGB_OUT_EN(1)); break; } if (mode == VOP_MODE_HDMI || mode == VOP_MODE_EDP) /* RGBaaa */ mode_flags = 15; else /* RGB888 */ mode_flags = 0; flags = V_DSP_OUT_MODE(mode_flags) | V_DSP_HSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_HSYNC_HIGH)) | V_DSP_VSYNC_POL(!!(edid->flags & DISPLAY_FLAGS_VSYNC_HIGH)); clrsetbits_le32(®s->dsp_ctrl0, M_DSP_OUT_MODE | M_DSP_VSYNC_POL | M_DSP_HSYNC_POL, flags); writel(V_HSYNC(hsync_len) | V_HORPRD(hsync_len + hback_porch + hactive + hfront_porch), ®s->dsp_htotal_hs_end); writel(V_HEAP(hsync_len + hback_porch + hactive) | V_HASP(hsync_len + hback_porch), ®s->dsp_hact_st_end); writel(V_VSYNC(vsync_len) | V_VERPRD(vsync_len + vback_porch + vactive + vfront_porch), ®s->dsp_vtotal_vs_end); writel(V_VAEP(vsync_len + vback_porch + vactive)| V_VASP(vsync_len + vback_porch), ®s->dsp_vact_st_end); writel(V_HEAP(hsync_len + hback_porch + hactive) | V_HASP(hsync_len + hback_porch), ®s->post_dsp_hact_info); writel(V_VAEP(vsync_len + vback_porch + vactive)| V_VASP(vsync_len + vback_porch), ®s->post_dsp_vact_info); writel(0x01, ®s->reg_cfg_done); /* enable reg config */ }
/* set up the ULPI USB controller with the parameters provided */ static int init_ulpi_usb_controller(struct fdt_usb *config) { u32 val; int loop_count; struct ulpi_viewport ulpi_vp; struct usb_ctlr *usbctlr = config->reg; /* set up ULPI reference clock on pllp_out4 */ clock_enable(PERIPH_ID_DEV2_OUT); clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK); /* reset ULPI phy */ if (fdt_gpio_isvalid(&config->phy_reset_gpio)) { fdtdec_setup_gpio(&config->phy_reset_gpio); gpio_direction_output(config->phy_reset_gpio.gpio, 0); mdelay(5); gpio_set_value(config->phy_reset_gpio.gpio, 1); } /* Reset the usb controller */ clock_enable(config->periph_id); usbf_reset_controller(config, usbctlr); /* enable pinmux bypass */ setbits_le32(&usbctlr->ulpi_timing_ctrl_0, ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP); /* Select ULPI parallel interface */ clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT); /* enable ULPI transceiver */ setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB); /* configure ULPI transceiver timings */ val = 0; writel(val, &usbctlr->ulpi_timing_ctrl_1); val |= ULPI_DATA_TRIMMER_SEL(4); val |= ULPI_STPDIRNXT_TRIMMER_SEL(4); val |= ULPI_DIR_TRIMMER_SEL(4); writel(val, &usbctlr->ulpi_timing_ctrl_1); udelay(10); val |= ULPI_DATA_TRIMMER_LOAD; val |= ULPI_STPDIRNXT_TRIMMER_LOAD; val |= ULPI_DIR_TRIMMER_LOAD; writel(val, &usbctlr->ulpi_timing_ctrl_1); /* set up phy for host operation with external vbus supply */ ulpi_vp.port_num = 0; ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport; if (ulpi_init(&ulpi_vp)) { printf("Tegra ULPI viewport init failed\n"); return -1; } ulpi_set_vbus(&ulpi_vp, 1, 1); ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0); /* enable wakeup events */ setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC); /* Enable and wait for the phy clock to become valid in 100 ms */ setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); for (loop_count = 100000; loop_count != 0; loop_count--) { if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID) break; udelay(1); } if (!loop_count) return -1; clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR); return 0; }
/* * Sends a command out on the bus. Takes the mmc pointer, * a command pointer, and an optional data pointer. */ static int mxsmmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, struct mmc_data *data) { struct mxsmmc_priv *priv = mmc->priv; struct mxs_ssp_regs *ssp_regs = priv->regs; uint32_t reg; int timeout; uint32_t ctrl0; int ret; debug("MMC%d: CMD%d\n", mmc->block_dev.devnum, cmd->cmdidx); /* Check bus busy */ timeout = MXSMMC_MAX_TIMEOUT; while (--timeout) { udelay(1000); reg = readl(&ssp_regs->hw_ssp_status); if (!(reg & (SSP_STATUS_BUSY | SSP_STATUS_DATA_BUSY | SSP_STATUS_CMD_BUSY))) { break; } } if (!timeout) { printf("MMC%d: Bus busy timeout!\n", mmc->block_dev.devnum); return -ETIMEDOUT; } /* See if card is present */ if (!mxsmmc_cd(priv)) { printf("MMC%d: No card detected!\n", mmc->block_dev.devnum); return -ENOMEDIUM; } /* Start building CTRL0 contents */ ctrl0 = priv->buswidth; /* Set up command */ if (!(cmd->resp_type & MMC_RSP_CRC)) ctrl0 |= SSP_CTRL0_IGNORE_CRC; if (cmd->resp_type & MMC_RSP_PRESENT) /* Need to get response */ ctrl0 |= SSP_CTRL0_GET_RESP; if (cmd->resp_type & MMC_RSP_136) /* It's a 136 bits response */ ctrl0 |= SSP_CTRL0_LONG_RESP; if (data && (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER)) writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_clr); else writel(SSP_CTRL1_DMA_ENABLE, &ssp_regs->hw_ssp_ctrl1_set); /* Command index */ reg = readl(&ssp_regs->hw_ssp_cmd0); reg &= ~(SSP_CMD0_CMD_MASK | SSP_CMD0_APPEND_8CYC); reg |= cmd->cmdidx << SSP_CMD0_CMD_OFFSET; if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION) reg |= SSP_CMD0_APPEND_8CYC; writel(reg, &ssp_regs->hw_ssp_cmd0); /* Command argument */ writel(cmd->cmdarg, &ssp_regs->hw_ssp_cmd1); /* Set up data */ if (data) { /* READ or WRITE */ if (data->flags & MMC_DATA_READ) { ctrl0 |= SSP_CTRL0_READ; } else if (priv->mmc_is_wp && priv->mmc_is_wp(mmc->block_dev.devnum)) { printf("MMC%d: Can not write a locked card!\n", mmc->block_dev.devnum); return -EOPNOTSUPP; } ctrl0 |= SSP_CTRL0_DATA_XFER; reg = data->blocksize * data->blocks; #if defined(CONFIG_MX23) ctrl0 |= reg & SSP_CTRL0_XFER_COUNT_MASK; clrsetbits_le32(&ssp_regs->hw_ssp_cmd0, SSP_CMD0_BLOCK_SIZE_MASK | SSP_CMD0_BLOCK_COUNT_MASK, ((data->blocks - 1) << SSP_CMD0_BLOCK_COUNT_OFFSET) | ((ffs(data->blocksize) - 1) << SSP_CMD0_BLOCK_SIZE_OFFSET)); #elif defined(CONFIG_MX28) writel(reg, &ssp_regs->hw_ssp_xfer_size); reg = ((data->blocks - 1) << SSP_BLOCK_SIZE_BLOCK_COUNT_OFFSET) | ((ffs(data->blocksize) - 1) << SSP_BLOCK_SIZE_BLOCK_SIZE_OFFSET); writel(reg, &ssp_regs->hw_ssp_block_size); #endif } /* Kick off the command */ ctrl0 |= SSP_CTRL0_WAIT_FOR_IRQ | SSP_CTRL0_ENABLE | SSP_CTRL0_RUN; writel(ctrl0, &ssp_regs->hw_ssp_ctrl0); /* Wait for the command to complete */ timeout = MXSMMC_MAX_TIMEOUT; while (--timeout) { udelay(1000); reg = readl(&ssp_regs->hw_ssp_status); if (!(reg & SSP_STATUS_CMD_BUSY)) break; } if (!timeout) { printf("MMC%d: Command %d busy\n", mmc->block_dev.devnum, cmd->cmdidx); return -ETIMEDOUT; } /* Check command timeout */ if (reg & SSP_STATUS_RESP_TIMEOUT) { printf("MMC%d: Command %d timeout (status 0x%08x)\n", mmc->block_dev.devnum, cmd->cmdidx, reg); return -ETIMEDOUT; } /* Check command errors */ if (reg & (SSP_STATUS_RESP_CRC_ERR | SSP_STATUS_RESP_ERR)) { printf("MMC%d: Command %d error (status 0x%08x)!\n", mmc->block_dev.devnum, cmd->cmdidx, reg); return -ECOMM; } /* Copy response to response buffer */ if (cmd->resp_type & MMC_RSP_136) { cmd->response[3] = readl(&ssp_regs->hw_ssp_sdresp0); cmd->response[2] = readl(&ssp_regs->hw_ssp_sdresp1); cmd->response[1] = readl(&ssp_regs->hw_ssp_sdresp2); cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp3); } else cmd->response[0] = readl(&ssp_regs->hw_ssp_sdresp0); /* Return if no data to process */ if (!data) return 0; if (data->blocksize * data->blocks < MXSMMC_SMALL_TRANSFER) { ret = mxsmmc_send_cmd_pio(priv, data); if (ret) { printf("MMC%d: Data timeout with command %d " "(status 0x%08x)!\n", mmc->block_dev.devnum, cmd->cmdidx, reg); return ret; } } else { ret = mxsmmc_send_cmd_dma(priv, data); if (ret) { printf("MMC%d: DMA transfer failed\n", mmc->block_dev.devnum); return ret; } } /* Check data errors */ reg = readl(&ssp_regs->hw_ssp_status); if (reg & (SSP_STATUS_TIMEOUT | SSP_STATUS_DATA_CRC_ERR | SSP_STATUS_FIFO_OVRFLW | SSP_STATUS_FIFO_UNDRFLW)) { printf("MMC%d: Data error with command %d (status 0x%08x)!\n", mmc->block_dev.devnum, cmd->cmdidx, reg); return -ECOMM; } return 0; }
static inline void do_bypass_dpll(const struct dpll_regs *dpll_regs) { clrsetbits_le32(dpll_regs->cm_clkmode_dpll, CM_CLKMODE_DPLL_DPLL_EN_MASK, DPLL_EN_MN_BYPASS << CM_CLKMODE_DPLL_EN_SHIFT); }
/* * Enable non-essential clock domains, modules and * do some additional special settings needed */ void enable_non_essential_clocks(void) { u32 const clk_domains_non_essential[] = { (*prcm)->cm_mpu_m3_clkstctrl, (*prcm)->cm_ivahd_clkstctrl, (*prcm)->cm_dsp_clkstctrl, (*prcm)->cm_dss_clkstctrl, (*prcm)->cm_sgx_clkstctrl, (*prcm)->cm1_abe_clkstctrl, (*prcm)->cm_c2c_clkstctrl, (*prcm)->cm_cam_clkstctrl, (*prcm)->cm_dss_clkstctrl, (*prcm)->cm_sdma_clkstctrl, 0 }; u32 const clk_modules_hw_auto_non_essential[] = { (*prcm)->cm_l3instr_l3_3_clkctrl, (*prcm)->cm_l3instr_l3_instr_clkctrl, (*prcm)->cm_l3instr_intrconn_wp1_clkctrl, (*prcm)->cm_l3init_hsi_clkctrl, 0 }; u32 const clk_modules_explicit_en_non_essential[] = { (*prcm)->cm1_abe_aess_clkctrl, (*prcm)->cm1_abe_pdm_clkctrl, (*prcm)->cm1_abe_dmic_clkctrl, (*prcm)->cm1_abe_mcasp_clkctrl, (*prcm)->cm1_abe_mcbsp1_clkctrl, (*prcm)->cm1_abe_mcbsp2_clkctrl, (*prcm)->cm1_abe_mcbsp3_clkctrl, (*prcm)->cm1_abe_slimbus_clkctrl, (*prcm)->cm1_abe_timer5_clkctrl, (*prcm)->cm1_abe_timer6_clkctrl, (*prcm)->cm1_abe_timer7_clkctrl, (*prcm)->cm1_abe_timer8_clkctrl, (*prcm)->cm1_abe_wdt3_clkctrl, (*prcm)->cm_l4per_gptimer9_clkctrl, (*prcm)->cm_l4per_gptimer10_clkctrl, (*prcm)->cm_l4per_gptimer11_clkctrl, (*prcm)->cm_l4per_gptimer3_clkctrl, (*prcm)->cm_l4per_gptimer4_clkctrl, (*prcm)->cm_l4per_hdq1w_clkctrl, (*prcm)->cm_l4per_mcbsp4_clkctrl, (*prcm)->cm_l4per_mcspi2_clkctrl, (*prcm)->cm_l4per_mcspi3_clkctrl, (*prcm)->cm_l4per_mcspi4_clkctrl, (*prcm)->cm_l4per_mmcsd3_clkctrl, (*prcm)->cm_l4per_mmcsd4_clkctrl, (*prcm)->cm_l4per_mmcsd5_clkctrl, (*prcm)->cm_l4per_uart1_clkctrl, (*prcm)->cm_l4per_uart2_clkctrl, (*prcm)->cm_l4per_uart4_clkctrl, (*prcm)->cm_wkup_keyboard_clkctrl, (*prcm)->cm_wkup_wdtimer2_clkctrl, (*prcm)->cm_cam_iss_clkctrl, (*prcm)->cm_cam_fdif_clkctrl, (*prcm)->cm_dss_dss_clkctrl, (*prcm)->cm_sgx_sgx_clkctrl, 0 }; /* Enable optional functional clock for ISS */ setbits_le32((*prcm)->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK); /* Enable all optional functional clocks of DSS */ setbits_le32((*prcm)->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK); do_enable_clocks(clk_domains_non_essential, clk_modules_hw_auto_non_essential, clk_modules_explicit_en_non_essential, 0); /* Put camera module in no sleep mode */ clrsetbits_le32((*prcm)->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK, CD_CLKCTRL_CLKTRCTRL_NO_SLEEP << MODULE_CLKCTRL_MODULEMODE_SHIFT); }
void init_pll(const struct pll_init_data *data) { u32 tmp, tmp_ctl, pllm, plld, pllod, bwadj; pllm = data->pll_m - 1; plld = (data->pll_d - 1) & PLL_DIV_MASK; pllod = (data->pll_od - 1) & PLL_CLKOD_MASK; if (data->pll == MAIN_PLL) { /* The requered delay before main PLL configuration */ sdelay(210000); tmp = pllctl_reg_read(data->pll, secctl); if (tmp & (PLLCTL_BYPASS)) { setbits_le32(keystone_pll_regs[data->pll].reg1, BIT(MAIN_ENSAT_OFFSET)); pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN | PLLCTL_PLLENSRC); sdelay(340); pllctl_reg_setbits(data->pll, secctl, PLLCTL_BYPASS); pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLPWRDN); sdelay(21000); pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLPWRDN); } else { pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLEN | PLLCTL_PLLENSRC); sdelay(340); } pllctl_reg_write(data->pll, mult, pllm & PLLM_MULT_LO_MASK); clrsetbits_le32(keystone_pll_regs[data->pll].reg0, PLLM_MULT_HI_SMASK, (pllm << 6)); /* Set the BWADJ (12 bit field) */ tmp_ctl = pllm >> 1; /* Divide the pllm by 2 */ clrsetbits_le32(keystone_pll_regs[data->pll].reg0, PLL_BWADJ_LO_SMASK, (tmp_ctl << PLL_BWADJ_LO_SHIFT)); clrsetbits_le32(keystone_pll_regs[data->pll].reg1, PLL_BWADJ_HI_MASK, (tmp_ctl >> 8)); /* * Set the pll divider (6 bit field) * * PLLD[5:0] is located in MAINPLLCTL0 */ clrsetbits_le32(keystone_pll_regs[data->pll].reg0, PLL_DIV_MASK, plld); /* Set the OUTPUT DIVIDE (4 bit field) in SECCTL */ pllctl_reg_rmw(data->pll, secctl, PLL_CLKOD_SMASK, (pllod << PLL_CLKOD_SHIFT)); wait_for_completion(data); pllctl_reg_write(data->pll, div1, PLLM_RATIO_DIV1); pllctl_reg_write(data->pll, div2, PLLM_RATIO_DIV2); pllctl_reg_write(data->pll, div3, PLLM_RATIO_DIV3); pllctl_reg_write(data->pll, div4, PLLM_RATIO_DIV4); pllctl_reg_write(data->pll, div5, PLLM_RATIO_DIV5); pllctl_reg_setbits(data->pll, alnctl, 0x1f); /* * Set GOSET bit in PLLCMD to initiate the GO operation * to change the divide */ pllctl_reg_setbits(data->pll, cmd, PLLSTAT_GO); sdelay(1500); /* wait for the phase adj */ wait_for_completion(data); /* Reset PLL */ pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLRST); sdelay(21000); /* Wait for a minimum of 7 us*/ pllctl_reg_clrbits(data->pll, ctl, PLLCTL_PLLRST); sdelay(105000); /* Wait for PLL Lock time (min 50 us) */ pllctl_reg_clrbits(data->pll, secctl, PLLCTL_BYPASS); tmp = pllctl_reg_setbits(data->pll, ctl, PLLCTL_PLLEN); #ifndef CONFIG_SOC_K2E } else if (data->pll == TETRIS_PLL) {
static void dpll4_init_34xx(u32 sil_index, u32 clk_index) { struct prcm *prcm_base = (struct prcm *)PRCM_BASE; dpll_param *ptr = (dpll_param *) get_per_dpll_param(); /* Moving it to the right sysclk base */ ptr = ptr + clk_index; /* EN_PERIPH_DPLL: CM_CLKEN_PLL[16:18] */ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_STOP << 16); wait_on_value(ST_PERIPH_CLK, 0, &prcm_base->idlest_ckgen, LDELAY); /* * Errata 1.50 Workaround for OMAP3 ES1.0 only * If using default divisors, write default divisor + 1 * and then the actual divisor value */ /* M6 */ clrsetbits_le32(&prcm_base->clksel1_emu, 0x1F000000, (PER_M6X2 + 1) << 24); clrsetbits_le32(&prcm_base->clksel1_emu, 0x1F000000, PER_M6X2 << 24); /* M5 */ clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, (PER_M5X2 + 1)); clrsetbits_le32(&prcm_base->clksel_cam, 0x0000001F, PER_M5X2); /* M4 */ clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, (PER_M4X2 + 1)); clrsetbits_le32(&prcm_base->clksel_dss, 0x0000001F, PER_M4X2); /* M3 */ clrsetbits_le32(&prcm_base->clksel_dss, 0x00001F00, (PER_M3X2 + 1) << 8); clrsetbits_le32(&prcm_base->clksel_dss, 0x00001F00, PER_M3X2 << 8); /* M2 (DIV_96M): CM_CLKSEL3_PLL[0:4] */ clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, (ptr->m2 + 1)); clrsetbits_le32(&prcm_base->clksel3_pll, 0x0000001F, ptr->m2); /* Workaround end */ /* M (PERIPH_DPLL_MULT): CM_CLKSEL2_PLL[8:18] */ clrsetbits_le32(&prcm_base->clksel2_pll, 0x0007FF00, ptr->m << 8); /* N (PERIPH_DPLL_DIV): CM_CLKSEL2_PLL[0:6] */ clrsetbits_le32(&prcm_base->clksel2_pll, 0x0000007F, ptr->n); /* FREQSEL (PERIPH_DPLL_FREQSEL): CM_CLKEN_PLL[20:23] */ clrsetbits_le32(&prcm_base->clken_pll, 0x00F00000, ptr->fsel << 20); /* LOCK MODE (EN_PERIPH_DPLL): CM_CLKEN_PLL[16:18] */ clrsetbits_le32(&prcm_base->clken_pll, 0x00070000, PLL_LOCK << 16); wait_on_value(ST_PERIPH_CLK, 2, &prcm_base->idlest_ckgen, LDELAY); }
void mx28_power_set_vddd(uint32_t new_target, uint32_t new_brownout) { struct mx28_power_regs *power_regs = (struct mx28_power_regs *)MXS_POWER_BASE; uint32_t cur_target, diff, bo_int = 0; uint32_t powered_by_linreg = 0; new_brownout = new_target - new_brownout; cur_target = readl(&power_regs->hw_power_vdddctrl); cur_target &= POWER_VDDDCTRL_TRG_MASK; cur_target *= 25; /* 25 mV step*/ cur_target += 800; /* 800 mV lowest */ powered_by_linreg = mx28_get_vddd_power_source_off(); if (new_target > cur_target) { if (powered_by_linreg) { bo_int = readl(&power_regs->hw_power_vdddctrl); clrbits_le32(&power_regs->hw_power_vdddctrl, POWER_CTRL_ENIRQ_VDDD_BO); } setbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_BO_OFFSET_MASK); do { if (new_target - cur_target > 100) diff = cur_target + 100; else diff = new_target; diff -= 800; diff /= 25; clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_TRG_MASK, diff); if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) early_delay(1500); else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) ; } cur_target = readl(&power_regs->hw_power_vdddctrl); cur_target &= POWER_VDDDCTRL_TRG_MASK; cur_target *= 25; /* 25 mV step*/ cur_target += 800; /* 800 mV lowest */ } while (new_target > cur_target); if (powered_by_linreg) { writel(POWER_CTRL_VDDD_BO_IRQ, &power_regs->hw_power_ctrl_clr); if (bo_int & POWER_CTRL_ENIRQ_VDDD_BO) setbits_le32(&power_regs->hw_power_vdddctrl, POWER_CTRL_ENIRQ_VDDD_BO); } } else { do { if (cur_target - new_target > 100) diff = cur_target - 100; else diff = new_target; diff -= 800; diff /= 25; clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_TRG_MASK, diff); if (powered_by_linreg || (readl(&power_regs->hw_power_sts) & POWER_STS_VDD5V_GT_VDDIO)) early_delay(1500); else { while (!(readl(&power_regs->hw_power_sts) & POWER_STS_DC_OK)) ; } cur_target = readl(&power_regs->hw_power_vdddctrl); cur_target &= POWER_VDDDCTRL_TRG_MASK; cur_target *= 25; /* 25 mV step*/ cur_target += 800; /* 800 mV lowest */ } while (new_target < cur_target); } clrsetbits_le32(&power_regs->hw_power_vdddctrl, POWER_VDDDCTRL_BO_OFFSET_MASK, new_brownout << POWER_VDDDCTRL_BO_OFFSET_OFFSET); }
/****************************************************************************** * prcm_init() - inits clocks for PRCM as defined in clocks.h * called from SRAM, or Flash (using temp SRAM stack). *****************************************************************************/ void prcm_init(void) { u32 osc_clk = 0, sys_clkin_sel; u32 clk_index, sil_index = 0; struct prm *prm_base = (struct prm *)PRM_BASE; struct prcm *prcm_base = (struct prcm *)PRCM_BASE; /* * Gauge the input clock speed and find out the sys_clkin_sel * value corresponding to the input clock. */ osc_clk = get_osc_clk_speed(); get_sys_clkin_sel(osc_clk, &sys_clkin_sel); /* set input crystal speed */ clrsetbits_le32(&prm_base->clksel, 0x00000007, sys_clkin_sel); /* If the input clock is greater than 19.2M always divide/2 */ if (sys_clkin_sel > 2) { /* input clock divider */ clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 2 << 6); clk_index = sys_clkin_sel / 2; } else { /* input clock divider */ clrsetbits_le32(&prm_base->clksrc_ctrl, 0x000000C0, 1 << 6); clk_index = sys_clkin_sel; } if (get_cpu_family() == CPU_OMAP36XX) { /* * In warm reset conditions on OMAP36xx/AM/DM37xx * the rom code incorrectly sets the DPLL4 clock * input divider to /6.5. Section 3.5.3.3.3.2.1 of * the AM/DM37x TRM explains that the /6.5 divider * is used only when the input clock is 13MHz. * * If the part is in this cpu family *and* the input * clock *is not* 13 MHz, then reset the DPLL4 clock * input divider to /1 as it should never set to /6.5 * in this case. */ if (sys_clkin_sel != 1) { /* 13 MHz */ /* Bit 8: DPLL4_CLKINP_DIV */ clrbits_le32(&prm_base->clksrc_ctrl, 0x00000100); } /* Unlock MPU DPLL (slows things down, and needed later) */ clrsetbits_le32(&prcm_base->clken_pll_mpu, 0x00000007, PLL_LOW_POWER_BYPASS); wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY); dpll3_init_36xx(0, clk_index); dpll4_init_36xx(0, clk_index); dpll5_init_36xx(0, clk_index); iva_init_36xx(0, clk_index); mpu_init_36xx(0, clk_index); /* Lock MPU DPLL to set frequency */ clrsetbits_le32(&prcm_base->clken_pll_mpu, 0x00000007, PLL_LOCK); wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY); } else { /* * The DPLL tables are defined according to sysclk value and * silicon revision. The clk_index value will be used to get * the values for that input sysclk from the DPLL param table * and sil_index will get the values for that SysClk for the * appropriate silicon rev. */ if (((get_cpu_family() == CPU_OMAP34XX) && (get_cpu_rev() >= CPU_3XX_ES20)) || (get_cpu_family() == CPU_AM35XX)) sil_index = 1; /* Unlock MPU DPLL (slows things down, and needed later) */ clrsetbits_le32(&prcm_base->clken_pll_mpu, 0x00000007, PLL_LOW_POWER_BYPASS); wait_on_value(ST_MPU_CLK, 0, &prcm_base->idlest_pll_mpu, LDELAY); dpll3_init_34xx(sil_index, clk_index); dpll4_init_34xx(sil_index, clk_index); dpll5_init_34xx(sil_index, clk_index); if (get_cpu_family() != CPU_AM35XX) iva_init_34xx(sil_index, clk_index); mpu_init_34xx(sil_index, clk_index); /* Lock MPU DPLL to set frequency */ clrsetbits_le32(&prcm_base->clken_pll_mpu, 0x00000007, PLL_LOCK); wait_on_value(ST_MPU_CLK, 1, &prcm_base->idlest_pll_mpu, LDELAY); } /* Set up GPTimers to sys_clk source only */ setbits_le32(&prcm_base->clksel_per, 0x000000FF); setbits_le32(&prcm_base->clksel_wkup, 1); sdelay(5000); }
static void board_clock_init(void) { unsigned int set, clr, clr_src_cpu, clr_pll_con0, clr_src_dmc; struct exynos4x12_clock *clk = (struct exynos4x12_clock *) samsung_get_base_clock(); /* * CMU_CPU clocks src to MPLL * Bit values: 0 ; 1 * MUX_APLL_SEL: FIN_PLL ; FOUT_APLL * MUX_CORE_SEL: MOUT_APLL ; SCLK_MPLL * MUX_HPM_SEL: MOUT_APLL ; SCLK_MPLL_USER_C * MUX_MPLL_USER_SEL_C: FIN_PLL ; SCLK_MPLL */ clr_src_cpu = MUX_APLL_SEL(1) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1); set = MUX_APLL_SEL(0) | MUX_CORE_SEL(1) | MUX_HPM_SEL(1) | MUX_MPLL_USER_SEL_C(1); clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); /* Wait for mux change */ while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) continue; /* Set APLL to 1000MHz */ clr_pll_con0 = SDIV(7) | PDIV(63) | MDIV(1023) | FSEL(1); set = SDIV(0) | PDIV(3) | MDIV(125) | FSEL(1); clrsetbits_le32(&clk->apll_con0, clr_pll_con0, set); /* Wait for PLL to be locked */ while (!(readl(&clk->apll_con0) & PLL_LOCKED_BIT)) continue; /* Set CMU_CPU clocks src to APLL */ set = MUX_APLL_SEL(1) | MUX_CORE_SEL(0) | MUX_HPM_SEL(0) | MUX_MPLL_USER_SEL_C(1); clrsetbits_le32(&clk->src_cpu, clr_src_cpu, set); /* Wait for mux change */ while (readl(&clk->mux_stat_cpu) & MUX_STAT_CPU_CHANGING) continue; set = CORE_RATIO(0) | COREM0_RATIO(2) | COREM1_RATIO(5) | PERIPH_RATIO(0) | ATB_RATIO(4) | PCLK_DBG_RATIO(1) | APLL_RATIO(0) | CORE2_RATIO(0); /* * Set dividers for MOUTcore = 1000 MHz * coreout = MOUT / (ratio + 1) = 1000 MHz (0) * corem0 = armclk / (ratio + 1) = 333 MHz (2) * corem1 = armclk / (ratio + 1) = 166 MHz (5) * periph = armclk / (ratio + 1) = 1000 MHz (0) * atbout = MOUT / (ratio + 1) = 200 MHz (4) * pclkdbgout = atbout / (ratio + 1) = 100 MHz (1) * sclkapll = MOUTapll / (ratio + 1) = 1000 MHz (0) * core2out = core_out / (ratio + 1) = 1000 MHz (0) (armclk) */ clr = CORE_RATIO(7) | COREM0_RATIO(7) | COREM1_RATIO(7) | PERIPH_RATIO(7) | ATB_RATIO(7) | PCLK_DBG_RATIO(7) | APLL_RATIO(7) | CORE2_RATIO(7); clrsetbits_le32(&clk->div_cpu0, clr, set); /* Wait for divider ready status */ while (readl(&clk->div_stat_cpu0) & DIV_STAT_CPU0_CHANGING) continue; /* * For MOUThpm = 1000 MHz (MOUTapll) * doutcopy = MOUThpm / (ratio + 1) = 200 (4) * sclkhpm = doutcopy / (ratio + 1) = 200 (4) * cores_out = armclk / (ratio + 1) = 200 (4) */ clr = COPY_RATIO(7) | HPM_RATIO(7) | CORES_RATIO(7); set = COPY_RATIO(4) | HPM_RATIO(4) | CORES_RATIO(4); clrsetbits_le32(&clk->div_cpu1, clr, set); /* Wait for divider ready status */ while (readl(&clk->div_stat_cpu1) & DIV_STAT_CPU1_CHANGING) continue; /* * Set CMU_DMC clocks src to APLL * Bit values: 0 ; 1 * MUX_C2C_SEL: SCLKMPLL ; SCLKAPLL * MUX_DMC_BUS_SEL: SCLKMPLL ; SCLKAPLL * MUX_DPHY_SEL: SCLKMPLL ; SCLKAPLL * MUX_MPLL_SEL: FINPLL ; MOUT_MPLL_FOUT * MUX_PWI_SEL: 0110 (MPLL); 0111 (EPLL); 1000 (VPLL); 0(XXTI) * MUX_G2D_ACP0_SEL: SCLKMPLL ; SCLKAPLL * MUX_G2D_ACP1_SEL: SCLKEPLL ; SCLKVPLL * MUX_G2D_ACP_SEL: OUT_ACP0 ; OUT_ACP1 */ clr_src_dmc = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) | MUX_MPLL_SEL(1) | MUX_PWI_SEL(15) | MUX_G2D_ACP0_SEL(1) | MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); set = MUX_C2C_SEL(1) | MUX_DMC_BUS_SEL(1) | MUX_DPHY_SEL(1) | MUX_MPLL_SEL(0) | MUX_PWI_SEL(0) | MUX_G2D_ACP0_SEL(1) | MUX_G2D_ACP1_SEL(1) | MUX_G2D_ACP_SEL(1); clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); /* Wait for mux change */ while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) continue; /* Set MPLL to 800MHz */ set = SDIV(0) | PDIV(3) | MDIV(100) | FSEL(0) | PLL_ENABLE(1); clrsetbits_le32(&clk->mpll_con0, clr_pll_con0, set); /* Wait for PLL to be locked */ while (!(readl(&clk->mpll_con0) & PLL_LOCKED_BIT)) continue; /* Switch back CMU_DMC mux */ set = MUX_C2C_SEL(0) | MUX_DMC_BUS_SEL(0) | MUX_DPHY_SEL(0) | MUX_MPLL_SEL(1) | MUX_PWI_SEL(8) | MUX_G2D_ACP0_SEL(0) | MUX_G2D_ACP1_SEL(0) | MUX_G2D_ACP_SEL(0); clrsetbits_le32(&clk->src_dmc, clr_src_dmc, set); /* Wait for mux change */ while (readl(&clk->mux_stat_dmc) & MUX_STAT_DMC_CHANGING) continue; /* CLK_DIV_DMC0 */ clr = ACP_RATIO(7) | ACP_PCLK_RATIO(7) | DPHY_RATIO(7) | DMC_RATIO(7) | DMCD_RATIO(7) | DMCP_RATIO(7); /* * For: * MOUTdmc = 800 MHz * MOUTdphy = 800 MHz * * aclk_acp = MOUTdmc / (ratio + 1) = 200 (3) * pclk_acp = aclk_acp / (ratio + 1) = 100 (1) * sclk_dphy = MOUTdphy / (ratio + 1) = 400 (1) * sclk_dmc = MOUTdmc / (ratio + 1) = 400 (1) * aclk_dmcd = sclk_dmc / (ratio + 1) = 200 (1) * aclk_dmcp = aclk_dmcd / (ratio + 1) = 100 (1) */ set = ACP_RATIO(3) | ACP_PCLK_RATIO(1) | DPHY_RATIO(1) | DMC_RATIO(1) | DMCD_RATIO(1) | DMCP_RATIO(1); clrsetbits_le32(&clk->div_dmc0, clr, set); /* Wait for divider ready status */ while (readl(&clk->div_stat_dmc0) & DIV_STAT_DMC0_CHANGING) continue; /* CLK_DIV_DMC1 */ clr = G2D_ACP_RATIO(15) | C2C_RATIO(7) | PWI_RATIO(15) | C2C_ACLK_RATIO(7) | DVSEM_RATIO(127) | DPM_RATIO(127); /* * For: * MOUTg2d = 800 MHz * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); clrsetbits_le32(&clk->div_dmc1, clr, set); /* Wait for divider ready status */ while (readl(&clk->div_stat_dmc1) & DIV_STAT_DMC1_CHANGING) continue; /* CLK_SRC_PERIL0 */ clr = UART0_SEL(15) | UART1_SEL(15) | UART2_SEL(15) | UART3_SEL(15) | UART4_SEL(15); /* * Set CLK_SRC_PERIL0 clocks src to MPLL * src values: 0(XXTI); 1(XusbXTI); 2(SCLK_HDMI24M); 3(SCLK_USBPHY0); * 5(SCLK_HDMIPHY); 6(SCLK_MPLL_USER_T); 7(SCLK_EPLL); * 8(SCLK_VPLL) * * Set all to SCLK_MPLL_USER_T */ set = UART0_SEL(6) | UART1_SEL(6) | UART2_SEL(6) | UART3_SEL(6) | UART4_SEL(6); clrsetbits_le32(&clk->src_peril0, clr, set); /* CLK_DIV_PERIL0 */ clr = UART0_RATIO(15) | UART1_RATIO(15) | UART2_RATIO(15) | UART3_RATIO(15) | UART4_RATIO(15); /* * For MOUTuart0-4: 800MHz * * SCLK_UARTx = MOUTuartX / (ratio + 1) = 100 (7) */ set = UART0_RATIO(7) | UART1_RATIO(7) | UART2_RATIO(7) | UART3_RATIO(7) | UART4_RATIO(7); clrsetbits_le32(&clk->div_peril0, clr, set); while (readl(&clk->div_stat_peril0) & DIV_STAT_PERIL0_CHANGING) continue; /* CLK_DIV_FSYS1 */ clr = MMC0_RATIO(15) | MMC0_PRE_RATIO(255) | MMC1_RATIO(15) | MMC1_PRE_RATIO(255); /* * For MOUTmmc0-3 = 800 MHz (MPLL) * * DOUTmmc1 = MOUTmmc1 / (ratio + 1) = 100 (7) * sclk_mmc1 = DOUTmmc1 / (ratio + 1) = 50 (1) * DOUTmmc0 = MOUTmmc0 / (ratio + 1) = 100 (7) * sclk_mmc0 = DOUTmmc0 / (ratio + 1) = 50 (1) */ set = MMC0_RATIO(7) | MMC0_PRE_RATIO(1) | MMC1_RATIO(7) | MMC1_PRE_RATIO(1); clrsetbits_le32(&clk->div_fsys1, clr, set); /* Wait for divider ready status */ while (readl(&clk->div_stat_fsys1) & DIV_STAT_FSYS1_CHANGING) continue; /* CLK_DIV_FSYS2 */ clr = MMC2_RATIO(15) | MMC2_PRE_RATIO(255) | MMC3_RATIO(15) | MMC3_PRE_RATIO(255); /* * For MOUTmmc0-3 = 800 MHz (MPLL) * * DOUTmmc3 = MOUTmmc3 / (ratio + 1) = 100 (7) * sclk_mmc3 = DOUTmmc3 / (ratio + 1) = 50 (1) * DOUTmmc2 = MOUTmmc2 / (ratio + 1) = 100 (7) * sclk_mmc2 = DOUTmmc2 / (ratio + 1) = 50 (1) */ set = MMC2_RATIO(7) | MMC2_PRE_RATIO(1) | MMC3_RATIO(7) | MMC3_PRE_RATIO(1); clrsetbits_le32(&clk->div_fsys2, clr, set); /* Wait for divider ready status */ while (readl(&clk->div_stat_fsys2) & DIV_STAT_FSYS2_CHANGING) continue; /* CLK_DIV_FSYS3 */ clr = MMC4_RATIO(15) | MMC4_PRE_RATIO(255); /* * For MOUTmmc4 = 800 MHz (MPLL) * * DOUTmmc4 = MOUTmmc4 / (ratio + 1) = 100 (7) * sclk_mmc4 = DOUTmmc4 / (ratio + 1) = 100 (0) */ set = MMC4_RATIO(7) | MMC4_PRE_RATIO(0); clrsetbits_le32(&clk->div_fsys3, clr, set); /* Wait for divider ready status */ while (readl(&clk->div_stat_fsys3) & DIV_STAT_FSYS3_CHANGING) continue; return; }
static void mxs_enable_4p2_dcdc_input(int xfer) { struct mxs_power_regs *power_regs = (struct mxs_power_regs *)MXS_POWER_BASE; uint32_t tmp, vbus_thresh, vbus_5vdetect, pwd_bo; uint32_t prev_5v_brnout, prev_5v_droop; prev_5v_brnout = readl(&power_regs->hw_power_5vctrl) & POWER_5VCTRL_PWDN_5VBRNOUT; prev_5v_droop = readl(&power_regs->hw_power_ctrl) & POWER_CTRL_ENIRQ_VDD5V_DROOP; clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_PWDN_5VBRNOUT); writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, &power_regs->hw_power_reset); clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); if (xfer && (readl(&power_regs->hw_power_5vctrl) & POWER_5VCTRL_ENABLE_DCDC)) { return; } /* * Recording orignal values that will be modified temporarlily * to handle a chip bug. See chip errata for CQ ENGR00115837 */ tmp = readl(&power_regs->hw_power_5vctrl); vbus_thresh = tmp & POWER_5VCTRL_VBUSVALID_TRSH_MASK; vbus_5vdetect = tmp & POWER_5VCTRL_VBUSVALID_5VDETECT; pwd_bo = readl(&power_regs->hw_power_minpwr) & POWER_MINPWR_PWD_BO; /* * Disable mechanisms that get erroneously tripped by when setting * the DCDC4P2 EN_DCDC */ clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_VBUSVALID_5VDETECT | POWER_5VCTRL_VBUSVALID_TRSH_MASK); writel(POWER_MINPWR_PWD_BO, &power_regs->hw_power_minpwr_set); if (xfer) { setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); early_delay(20); clrbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_DCDC_XFER); setbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_ENABLE_DCDC); } else { setbits_le32(&power_regs->hw_power_dcdc4p2, POWER_DCDC4P2_ENABLE_DCDC); } early_delay(25); clrsetbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_VBUSVALID_TRSH_MASK, vbus_thresh); if (vbus_5vdetect) writel(vbus_5vdetect, &power_regs->hw_power_5vctrl_set); if (!pwd_bo) clrbits_le32(&power_regs->hw_power_minpwr, POWER_MINPWR_PWD_BO); while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VBUS_VALID_IRQ) writel(POWER_CTRL_VBUS_VALID_IRQ, &power_regs->hw_power_ctrl_clr); if (prev_5v_brnout) { writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_set); writel(POWER_RESET_UNLOCK_KEY, &power_regs->hw_power_reset); } else { writel(POWER_5VCTRL_PWDN_5VBRNOUT, &power_regs->hw_power_5vctrl_clr); writel(POWER_RESET_UNLOCK_KEY | POWER_RESET_PWD_OFF, &power_regs->hw_power_reset); } while (readl(&power_regs->hw_power_ctrl) & POWER_CTRL_VDD5V_DROOP_IRQ) writel(POWER_CTRL_VDD5V_DROOP_IRQ, &power_regs->hw_power_ctrl_clr); if (prev_5v_droop) clrbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); else setbits_le32(&power_regs->hw_power_ctrl, POWER_CTRL_ENIRQ_VDD5V_DROOP); }
void lowlevel_init(void* cur,void * target) { int i; #if 0 if(cur != target) //r0!=r1 { //running from spi // take me as a spi rom boot mode romboot_info->por_cfg = POR_INTL_SPI | (READ_CBUS_REG(ASSIST_POR_CONFIG)&(~POR_INTL_CFG_MASK)); romboot_info->boot_id = 0;//boot from spi /// Release pull up registers . } #endif //gpiob_8 clrbits_le32(P_PREG_GGPIO_O, 1<<16); clrbits_le32(P_PREG_GGPIO_EN_N, 1<<16); //gpiob_5 clrbits_le32(P_PREG_GGPIO_O, 1<<13); clrbits_le32(P_PREG_GGPIO_EN_N, 1<<13); //writel((1<<22)|100000,P_WATCHDOG_TC);//enable Watchdog 1 seconds //Adjust 1us timer base //clrbits_le32(P_PREG_FGPIO_O, 1<<21); //mute // setbits_le32(P_PREG_GGPIO_O, 1<<5); // clrbits_le32(P_PREG_GGPIO_EN_N, 1<<5); // //vcc_12v/24v power down GPIOX_70 // setbits_le32(P_PREG_GGPIO_O, 1<<6); // clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6); // bl // setbits_le32(P_PREG_FGPIO_O, 1<<21); // clrbits_le32(P_PREG_FGPIO_EN_N, 1<<21); //Wr(REG_LVDS_PHY_CNTL4, 0);//LVDS_MDR_PU //clrbits_le32(P_PREG_GGPIO_O, 1<<6); //clrbits_le32(P_PREG_GGPIO_EN_N, 1<<6); WRITE_CBUS_REG_BITS(PREG_CTLREG0_ADDR,CONFIG_CRYSTAL_MHZ,4,5); /* Select TimerE 1 us base */ clrsetbits_le32(P_ISA_TIMER_MUX,0x7<<8,0x1<<8); if(1) { writel(0,P_WATCHDOG_TC);//disable Watchdog //while(1) { __udelay(50000); } } memory_pll_init(0,NULL); //serial_put_dword(get_timer(0)); //serial_put_dword(readl(0xc1100000+0x200b*4)); #if CONFIG_ENABLE_SPL_DEBUG_ROM __udelay(100000);//wait for a uart input if(serial_tstc()){ writel(0,P_WATCHDOG_TC);//disable Watchdog debug_rom(__FILE__,__LINE__); } #else __udelay(1000);//delay 1 ms , wait pll ready #endif #if 1 #if CONFIG_ENABLE_SPL_DEBUG_ROM if(ddr_init_test()){ writel(0,P_WATCHDOG_TC);//disable Watchdog debug_rom(__FILE__,__LINE__); } #else do{ }while(ddr_init_test(0x6)); #endif #endif writel(0,P_WATCHDOG_TC);//disable Watchdog //serial_puts("\nM2C (Haier TV) Systemp Started\n"); }
static void enable_hpet(void) { /* Move HPET to default address 0xfed00000 and enable it */ clrsetbits_le32(RCB_REG(HPTC), 3 << 0, 1 << 7); }
int dram_init(void) { static const struct ddr3_jedec_timings pcm052_ddr_timings = { .tinit = 5, .trst_pwron = 80000, .cke_inactive = 200000, .wrlat = 5, .caslat_lin = 12, .trc = 6, .trrd = 4, .tccd = 4, .tbst_int_interval = 4, .tfaw = 18, .trp = 6, .twtr = 4, .tras_min = 15, .tmrd = 4, .trtp = 4, .tras_max = 14040, .tmod = 12, .tckesr = 4, .tcke = 3, .trcd_int = 6, .tras_lockout = 1, .tdal = 10, .bstlen = 3, .tdll = 512, .trp_ab = 6, .tref = 1542, .trfc = 64, .tref_int = 5, .tpdex = 3, .txpdll = 10, .txsnr = 68, .txsr = 506, .cksrx = 5, .cksre = 5, .freq_chg_en = 1, .zqcl = 256, .zqinit = 512, .zqcs = 64, .ref_per_zq = 64, .zqcs_rotate = 1, .aprebit = 10, .cmd_age_cnt = 255, .age_cnt = 255, .q_fullness = 0, .odt_rd_mapcs0 = 1, .odt_wr_mapcs0 = 1, .wlmrd = 40, .wldqsen = 25, }; static const iomux_v3_cfg_t pcm052_pads[] = { PCM052_VF610_PAD_DDR_A15__DDR_A_15, PCM052_VF610_PAD_DDR_A14__DDR_A_14, PCM052_VF610_PAD_DDR_A13__DDR_A_13, PCM052_VF610_PAD_DDR_A12__DDR_A_12, PCM052_VF610_PAD_DDR_A11__DDR_A_11, PCM052_VF610_PAD_DDR_A10__DDR_A_10, PCM052_VF610_PAD_DDR_A9__DDR_A_9, PCM052_VF610_PAD_DDR_A8__DDR_A_8, PCM052_VF610_PAD_DDR_A7__DDR_A_7, PCM052_VF610_PAD_DDR_A6__DDR_A_6, PCM052_VF610_PAD_DDR_A5__DDR_A_5, PCM052_VF610_PAD_DDR_A4__DDR_A_4, PCM052_VF610_PAD_DDR_A3__DDR_A_3, PCM052_VF610_PAD_DDR_A2__DDR_A_2, PCM052_VF610_PAD_DDR_A1__DDR_A_1, PCM052_VF610_PAD_DDR_A0__DDR_A_0, PCM052_VF610_PAD_DDR_BA2__DDR_BA_2, PCM052_VF610_PAD_DDR_BA1__DDR_BA_1, PCM052_VF610_PAD_DDR_BA0__DDR_BA_0, PCM052_VF610_PAD_DDR_CAS__DDR_CAS_B, PCM052_VF610_PAD_DDR_CKE__DDR_CKE_0, PCM052_VF610_PAD_DDR_CLK__DDR_CLK_0, PCM052_VF610_PAD_DDR_CS__DDR_CS_B_0, PCM052_VF610_PAD_DDR_D15__DDR_D_15, PCM052_VF610_PAD_DDR_D14__DDR_D_14, PCM052_VF610_PAD_DDR_D13__DDR_D_13, PCM052_VF610_PAD_DDR_D12__DDR_D_12, PCM052_VF610_PAD_DDR_D11__DDR_D_11, PCM052_VF610_PAD_DDR_D10__DDR_D_10, PCM052_VF610_PAD_DDR_D9__DDR_D_9, PCM052_VF610_PAD_DDR_D8__DDR_D_8, PCM052_VF610_PAD_DDR_D7__DDR_D_7, PCM052_VF610_PAD_DDR_D6__DDR_D_6, PCM052_VF610_PAD_DDR_D5__DDR_D_5, PCM052_VF610_PAD_DDR_D4__DDR_D_4, PCM052_VF610_PAD_DDR_D3__DDR_D_3, PCM052_VF610_PAD_DDR_D2__DDR_D_2, PCM052_VF610_PAD_DDR_D1__DDR_D_1, PCM052_VF610_PAD_DDR_D0__DDR_D_0, PCM052_VF610_PAD_DDR_DQM1__DDR_DQM_1, PCM052_VF610_PAD_DDR_DQM0__DDR_DQM_0, PCM052_VF610_PAD_DDR_DQS1__DDR_DQS_1, PCM052_VF610_PAD_DDR_DQS0__DDR_DQS_0, PCM052_VF610_PAD_DDR_RAS__DDR_RAS_B, PCM052_VF610_PAD_DDR_WE__DDR_WE_B, PCM052_VF610_PAD_DDR_ODT1__DDR_ODT_0, PCM052_VF610_PAD_DDR_ODT0__DDR_ODT_1, PCM052_VF610_PAD_DDR_DDRBYTE1__DDR_DDRBYTE1, PCM052_VF610_PAD_DDR_DDRBYTE0__DDR_DDRBYTE0, PCM052_VF610_PAD_DDR_RESETB, }; imx_iomux_v3_setup_multiple_pads(pcm052_pads, ARRAY_SIZE(pcm052_pads)); ddrmc_ctrl_init_ddr3(&pcm052_ddr_timings, pcm052_cr_settings, pcm052_phy_settings, 1, 2); gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); return 0; } static void setup_iomux_uart(void) { static const iomux_v3_cfg_t uart1_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTB4__UART1_TX, VF610_UART_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTB5__UART1_RX, VF610_UART_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads)); } #define ENET_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_50ohm | PAD_CTL_OBE_IBE_ENABLE) static void setup_iomux_enet(void) { static const iomux_v3_cfg_t enet0_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTA6__RMII0_CLKIN, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC1__RMII0_MDIO, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC0__RMII0_MDC, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC2__RMII0_CRS_DV, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC3__RMII0_RD1, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC4__RMII0_RD0, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC5__RMII0_RXER, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC6__RMII0_TD1, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC7__RMII0_TD0, ENET_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTC8__RMII0_TXEN, ENET_PAD_CTRL), }; imx_iomux_v3_setup_multiple_pads(enet0_pads, ARRAY_SIZE(enet0_pads)); } /* * I2C2 is the only I2C used, on pads PTA22/PTA23. */ static void setup_iomux_i2c(void) { static const iomux_v3_cfg_t i2c_pads[] = { VF610_PAD_PTA22__I2C2_SCL, VF610_PAD_PTA23__I2C2_SDA, }; imx_iomux_v3_setup_multiple_pads(i2c_pads, ARRAY_SIZE(i2c_pads)); } #ifdef CONFIG_NAND_VF610_NFC static void setup_iomux_nfc(void) { static const iomux_v3_cfg_t nfc_pads[] = { VF610_PAD_PTD31__NF_IO15, VF610_PAD_PTD30__NF_IO14, VF610_PAD_PTD29__NF_IO13, VF610_PAD_PTD28__NF_IO12, VF610_PAD_PTD27__NF_IO11, VF610_PAD_PTD26__NF_IO10, VF610_PAD_PTD25__NF_IO9, VF610_PAD_PTD24__NF_IO8, VF610_PAD_PTD23__NF_IO7, VF610_PAD_PTD22__NF_IO6, VF610_PAD_PTD21__NF_IO5, VF610_PAD_PTD20__NF_IO4, VF610_PAD_PTD19__NF_IO3, VF610_PAD_PTD18__NF_IO2, VF610_PAD_PTD17__NF_IO1, VF610_PAD_PTD16__NF_IO0, VF610_PAD_PTB24__NF_WE_B, VF610_PAD_PTB25__NF_CE0_B, VF610_PAD_PTB27__NF_RE_B, VF610_PAD_PTC26__NF_RB_B, VF610_PAD_PTC27__NF_ALE, VF610_PAD_PTC28__NF_CLE }; imx_iomux_v3_setup_multiple_pads(nfc_pads, ARRAY_SIZE(nfc_pads)); } #endif static void setup_iomux_qspi(void) { static const iomux_v3_cfg_t qspi0_pads[] = { VF610_PAD_PTD0__QSPI0_A_QSCK, VF610_PAD_PTD1__QSPI0_A_CS0, VF610_PAD_PTD2__QSPI0_A_DATA3, VF610_PAD_PTD3__QSPI0_A_DATA2, VF610_PAD_PTD4__QSPI0_A_DATA1, VF610_PAD_PTD5__QSPI0_A_DATA0, VF610_PAD_PTD7__QSPI0_B_QSCK, VF610_PAD_PTD8__QSPI0_B_CS0, VF610_PAD_PTD9__QSPI0_B_DATA3, VF610_PAD_PTD10__QSPI0_B_DATA2, VF610_PAD_PTD11__QSPI0_B_DATA1, VF610_PAD_PTD12__QSPI0_B_DATA0, }; imx_iomux_v3_setup_multiple_pads(qspi0_pads, ARRAY_SIZE(qspi0_pads)); } #define ESDHC_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_HIGH | \ PAD_CTL_DSE_20ohm | PAD_CTL_OBE_IBE_ENABLE) struct fsl_esdhc_cfg esdhc_cfg[1] = { {ESDHC1_BASE_ADDR}, }; int board_mmc_getcd(struct mmc *mmc) { /* eSDHC1 is always present */ return 1; } int board_mmc_init(bd_t *bis) { static const iomux_v3_cfg_t esdhc1_pads[] = { NEW_PAD_CTRL(VF610_PAD_PTA24__ESDHC1_CLK, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA25__ESDHC1_CMD, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA26__ESDHC1_DAT0, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA27__ESDHC1_DAT1, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA28__ESDHC1_DAT2, ESDHC_PAD_CTRL), NEW_PAD_CTRL(VF610_PAD_PTA29__ESDHC1_DAT3, ESDHC_PAD_CTRL), }; esdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); imx_iomux_v3_setup_multiple_pads( esdhc1_pads, ARRAY_SIZE(esdhc1_pads)); return fsl_esdhc_initialize(bis, &esdhc_cfg[0]); } static void clock_init(void) { struct ccm_reg *ccm = (struct ccm_reg *)CCM_BASE_ADDR; struct anadig_reg *anadig = (struct anadig_reg *)ANADIG_BASE_ADDR; clrsetbits_le32(&ccm->ccgr0, CCM_REG_CTRL_MASK, CCM_CCGR0_UART1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr1, CCM_REG_CTRL_MASK, CCM_CCGR1_PIT_CTRL_MASK | CCM_CCGR1_WDOGA5_CTRL_MASK); clrsetbits_le32(&ccm->ccgr2, CCM_REG_CTRL_MASK, CCM_CCGR2_IOMUXC_CTRL_MASK | CCM_CCGR2_PORTA_CTRL_MASK | CCM_CCGR2_PORTB_CTRL_MASK | CCM_CCGR2_PORTC_CTRL_MASK | CCM_CCGR2_PORTD_CTRL_MASK | CCM_CCGR2_PORTE_CTRL_MASK | CCM_CCGR2_QSPI0_CTRL_MASK); clrsetbits_le32(&ccm->ccgr3, CCM_REG_CTRL_MASK, CCM_CCGR3_ANADIG_CTRL_MASK | CCM_CCGR3_SCSC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr4, CCM_REG_CTRL_MASK, CCM_CCGR4_WKUP_CTRL_MASK | CCM_CCGR4_CCM_CTRL_MASK | CCM_CCGR4_GPC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr6, CCM_REG_CTRL_MASK, CCM_CCGR6_OCOTP_CTRL_MASK | CCM_CCGR6_DDRMC_CTRL_MASK); clrsetbits_le32(&ccm->ccgr7, CCM_REG_CTRL_MASK, CCM_CCGR7_SDHC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr9, CCM_REG_CTRL_MASK, CCM_CCGR9_FEC0_CTRL_MASK | CCM_CCGR9_FEC1_CTRL_MASK); clrsetbits_le32(&ccm->ccgr10, CCM_REG_CTRL_MASK, CCM_CCGR10_NFC_CTRL_MASK | CCM_CCGR10_I2C2_CTRL_MASK); clrsetbits_le32(&anadig->pll2_ctrl, ANADIG_PLL2_CTRL_POWERDOWN, ANADIG_PLL2_CTRL_ENABLE | ANADIG_PLL2_CTRL_DIV_SELECT); clrsetbits_le32(&anadig->pll1_ctrl, ANADIG_PLL1_CTRL_POWERDOWN, ANADIG_PLL1_CTRL_ENABLE | ANADIG_PLL1_CTRL_DIV_SELECT); clrsetbits_le32(&ccm->ccr, CCM_CCR_OSCNT_MASK, CCM_CCR_FIRC_EN | CCM_CCR_OSCNT(5)); clrsetbits_le32(&ccm->ccsr, CCM_REG_CTRL_MASK, CCM_CCSR_PLL1_PFD_CLK_SEL(3) | CCM_CCSR_PLL2_PFD4_EN | CCM_CCSR_PLL2_PFD3_EN | CCM_CCSR_PLL2_PFD2_EN | CCM_CCSR_PLL2_PFD1_EN | CCM_CCSR_PLL1_PFD4_EN | CCM_CCSR_PLL1_PFD3_EN | CCM_CCSR_PLL1_PFD2_EN | CCM_CCSR_PLL1_PFD1_EN | CCM_CCSR_DDRC_CLK_SEL(1) | CCM_CCSR_FAST_CLK_SEL(1) | CCM_CCSR_SYS_CLK_SEL(4)); clrsetbits_le32(&ccm->cacrr, CCM_REG_CTRL_MASK, CCM_CACRR_IPG_CLK_DIV(1) | CCM_CACRR_BUS_CLK_DIV(2) | CCM_CACRR_ARM_CLK_DIV(0)); clrsetbits_le32(&ccm->cscmr1, CCM_REG_CTRL_MASK, CCM_CSCMR1_ESDHC1_CLK_SEL(3) | CCM_CSCMR1_QSPI0_CLK_SEL(3) | CCM_CSCMR1_NFC_CLK_SEL(0)); clrsetbits_le32(&ccm->cscdr1, CCM_REG_CTRL_MASK, CCM_CSCDR1_RMII_CLK_EN); clrsetbits_le32(&ccm->cscdr2, CCM_REG_CTRL_MASK, CCM_CSCDR2_ESDHC1_EN | CCM_CSCDR2_ESDHC1_CLK_DIV(0) | CCM_CSCDR2_NFC_EN); clrsetbits_le32(&ccm->cscdr3, CCM_REG_CTRL_MASK, CCM_CSCDR3_QSPI0_EN | CCM_CSCDR3_QSPI0_DIV(1) | CCM_CSCDR3_QSPI0_X2_DIV(1) | CCM_CSCDR3_QSPI0_X4_DIV(3) | CCM_CSCDR3_NFC_PRE_DIV(5)); clrsetbits_le32(&ccm->cscmr2, CCM_REG_CTRL_MASK, CCM_CSCMR2_RMII_CLK_SEL(0)); } static void mscm_init(void) { struct mscm_ir *mscmir = (struct mscm_ir *)MSCM_IR_BASE_ADDR; int i; for (i = 0; i < MSCM_IRSPRC_NUM; i++) writew(MSCM_IRSPRC_CP0_EN, &mscmir->irsprc[i]); } int board_phy_config(struct phy_device *phydev) { if (phydev->drv->config) phydev->drv->config(phydev); return 0; } int board_early_init_f(void) { clock_init(); mscm_init(); setup_iomux_uart(); setup_iomux_enet(); setup_iomux_i2c(); setup_iomux_qspi(); setup_iomux_nfc(); return 0; }
static inline void enable_clock_domain(u32 *const clkctrl_reg, u32 enable_mode) { clrsetbits_le32(clkctrl_reg, CD_CLKCTRL_CLKTRCTRL_MASK, enable_mode << CD_CLKCTRL_CLKTRCTRL_SHIFT); debug("Enable clock domain - 0x%08x\n", clkctrl_reg); }
static void writebits(uint32_t value, uint32_t *addr, uint32_t mask) { clrsetbits_le32(addr, mask, (value & mask)); }
static void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode) { clrsetbits_le32(&dwc3_reg->g_ctl, DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG), DWC3_GCTL_PRTCAPDIR(mode)); }
static void sunxi_lcdc_tcon1_mode_set(const struct ctfb_res_modes *mode, int *clk_div, int *clk_double, bool use_portd_hvsync) { struct sunxi_lcdc_reg * const lcdc = (struct sunxi_lcdc_reg *)SUNXI_LCD0_BASE; int bp, clk_delay, total, val, yres; /* Use tcon1 */ clrsetbits_le32(&lcdc->ctrl, SUNXI_LCDC_CTRL_IO_MAP_MASK, SUNXI_LCDC_CTRL_IO_MAP_TCON1); clk_delay = sunxi_lcdc_get_clk_delay(mode, 1); writel(SUNXI_LCDC_TCON1_CTRL_ENABLE | ((mode->vmode == FB_VMODE_INTERLACED) ? SUNXI_LCDC_TCON1_CTRL_INTERLACE_ENABLE : 0) | SUNXI_LCDC_TCON1_CTRL_CLK_DELAY(clk_delay), &lcdc->tcon1_ctrl); yres = mode->yres; if (mode->vmode == FB_VMODE_INTERLACED) yres /= 2; writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres), &lcdc->tcon1_timing_source); writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres), &lcdc->tcon1_timing_scale); writel(SUNXI_LCDC_X(mode->xres) | SUNXI_LCDC_Y(yres), &lcdc->tcon1_timing_out); bp = mode->hsync_len + mode->left_margin; total = mode->xres + mode->right_margin + bp; writel(SUNXI_LCDC_TCON1_TIMING_H_TOTAL(total) | SUNXI_LCDC_TCON1_TIMING_H_BP(bp), &lcdc->tcon1_timing_h); bp = mode->vsync_len + mode->upper_margin; total = mode->yres + mode->lower_margin + bp; if (mode->vmode == FB_VMODE_NONINTERLACED) total *= 2; writel(SUNXI_LCDC_TCON1_TIMING_V_TOTAL(total) | SUNXI_LCDC_TCON1_TIMING_V_BP(bp), &lcdc->tcon1_timing_v); writel(SUNXI_LCDC_X(mode->hsync_len) | SUNXI_LCDC_Y(mode->vsync_len), &lcdc->tcon1_timing_sync); if (use_portd_hvsync) { sunxi_gpio_set_cfgpin(SUNXI_GPD(26), SUNXI_GPD_LCD0); sunxi_gpio_set_cfgpin(SUNXI_GPD(27), SUNXI_GPD_LCD0); val = 0; if (mode->sync & FB_SYNC_HOR_HIGH_ACT) val |= SUNXI_LCDC_TCON_HSYNC_MASK; if (mode->sync & FB_SYNC_VERT_HIGH_ACT) val |= SUNXI_LCDC_TCON_VSYNC_MASK; writel(val, &lcdc->tcon1_io_polarity); clrbits_le32(&lcdc->tcon1_io_tristate, SUNXI_LCDC_TCON_VSYNC_MASK | SUNXI_LCDC_TCON_HSYNC_MASK); } #ifdef CONFIG_MACH_SUN5I if (sunxi_is_composite()) clrsetbits_le32(&lcdc->mux_ctrl, SUNXI_LCDC_MUX_CTRL_SRC0_MASK, SUNXI_LCDC_MUX_CTRL_SRC0(1)); #endif sunxi_lcdc_pll_set(1, mode->pixclock_khz, clk_div, clk_double); }