Example #1
0
File: board.c Project: A-Paul/RIOT
void board_init(void)
{
    /* initialize the boards LEDs */
    gpio_init(LED0_PIN, GPIO_OUT);
    gpio_init(LED1_PIN, GPIO_OUT);
    gpio_init(LED2_PIN, GPIO_OUT);
    gpio_init(LED3_PIN, GPIO_OUT);

    /* initialize the CPU */
    cpu_init();
}
Example #2
0
File: board.c Project: OTAkeys/RIOT
void board_init(void)
{
    /* setup on-board LEDs */
    NRF_P0->DIRSET = (LED_MASK_P0);
    NRF_P0->OUTSET = (LED_MASK_P0);
    NRF_P1->DIRSET = (LED_MASK_P1);
    NRF_P1->OUTSET = (LED_MASK_P1);

    /* initialize the CPU */
    cpu_init();
}
Example #3
0
File: board.c Project: adjih/RIOT
void board_init(void)
{
    /* initialize the CPU */
    cpu_init();

#ifdef AUTO_INIT_LED0
    /* The LED pin is also used for SPI, so we enable it
       only if explicitly wanted by the user */
    gpio_init(LED0_PIN, GPIO_OUT);
#endif
}
Example #4
0
void boot_64(uint32_t magic, uint32_t multiboot) {
  // checking multiboot magic variable.
  VGA_AT(0,0) = VGA_ENTRY('H', WHITE_ON_BLACK);
  if (magic != MULTIBOOT_BOOTLOADER_MAGIC) {
    VGA_AT(0,1) = VGA_ENTRY('!', WHITE_ON_BLACK);
    kernel_panic();
  }

  // copying multiboot data.
  VGA_AT(0,1) = VGA_ENTRY('E', WHITE_ON_BLACK);
  multiboot_info_t *info = (multiboot_info_t *)kernel_p2v((uintptr_t)multiboot);
  switch (multiboot_copy(info)) {
  case MULTIBOOT_TOO_MANY_MEMORY_MAPS:
    VGA_AT(0,2) = VGA_ENTRY('?', WHITE_ON_BLACK);
    kernel_panic();
  case MULTIBOOT_TOO_MANY_MODULES:
    VGA_AT(0,2) = VGA_ENTRY('?', WHITE_ON_BLACK);
    kernel_panic();
  case MULTIBOOT_TOO_MANY_ELF_HEADERS:
    VGA_AT(0,2) = VGA_ENTRY('.', WHITE_ON_BLACK);
    kernel_panic();
  }

  // we no longer need the original memory map at zero address.
  VGA_AT(0,2) = VGA_ENTRY('L', WHITE_ON_BLACK);
  page_set_pdpt(0, 0, 0);
  page_invalidate_all();
  
  // initialize page allocators.
  VGA_AT(0,3) = VGA_ENTRY('L', WHITE_ON_BLACK);
  lomem_init();
  himem_init();

  // initialize CPUs.
  VGA_AT(0,4) = VGA_ENTRY('B', WHITE_ON_BLACK);
  cpu_enable_features();
  cpu_init();
  service_init();
  gdt_init(); // adds per-cpu TSS into GDT.
  tss_update();

  // initialize interrupt handling.
  VGA_AT(0,5) = VGA_ENTRY('E', WHITE_ON_BLACK);
  pic_init();
  idt_init();

  // kick-start the core service.
  VGA_AT(0,6) = VGA_ENTRY('N', WHITE_ON_BLACK);
  kernel_start_core();

  // start scheduler and do stuff.
  VGA_AT(0,7) = VGA_ENTRY('D', WHITE_ON_BLACK);
  kernel_main();
}
Example #5
0
void
os_perf_cpuarr_init(perf_cpu_t *cpu_arr, int num, boolean_t hotadd)
{
	int i;
	
	for (i = 0; i < num; i++) {
		cpu_arr[i].cpuid = INVALID_CPUID;
		cpu_arr[i].hotadd = hotadd;
		cpu_init(&cpu_arr[i]);		
	}
}
static void
petalogix_s3adsp1800_init(ram_addr_t ram_size,
                          const char *boot_device,
                          const char *kernel_filename,
                          const char *kernel_cmdline,
                          const char *initrd_filename, const char *cpu_model)
{
    DeviceState *dev;
    CPUMBState *env;
    DriveInfo *dinfo;
    int i;
    target_phys_addr_t ddr_base = MEMORY_BASEADDR;
    MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1);
    MemoryRegion *phys_ram = g_new(MemoryRegion, 1);
    qemu_irq irq[32], *cpu_irq;
    MemoryRegion *sysmem = get_system_memory();

    /* init CPUs */
    if (cpu_model == NULL) {
        cpu_model = "microblaze";
    }
    env = cpu_init(cpu_model);

    /* Attach emulated BRAM through the LMB.  */
    memory_region_init_ram(phys_lmb_bram,
                           "petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE);
    vmstate_register_ram_global(phys_lmb_bram);
    memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram);

    memory_region_init_ram(phys_ram, "petalogix_s3adsp1800.ram", ram_size);
    vmstate_register_ram_global(phys_ram);
    memory_region_add_subregion(sysmem, ddr_base, phys_ram);

    dinfo = drive_get(IF_PFLASH, 0, 0);
    pflash_cfi01_register(FLASH_BASEADDR,
                          NULL, "petalogix_s3adsp1800.flash", FLASH_SIZE,
                          dinfo ? dinfo->bdrv : NULL, (64 * 1024),
                          FLASH_SIZE >> 16,
                          1, 0x89, 0x18, 0x0000, 0x0, 1);

    cpu_irq = microblaze_pic_init_cpu(env);
    dev = xilinx_intc_create(INTC_BASEADDR, cpu_irq[0], 2);
    for (i = 0; i < 32; i++) {
        irq[i] = qdev_get_gpio_in(dev, i);
    }

    sysbus_create_simple("xilinx,uartlite", UARTLITE_BASEADDR, irq[3]);
    /* 2 timers at irq 2 @ 62 Mhz.  */
    xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000);
    xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0);

    microblaze_load_kernel(env, ddr_base, ram_size,
                    BINARY_DEVICE_TREE_FILE, machine_cpu_reset);
}
void s5l8930_iop_init(void *opaque)
{
    int io;
    s5l8930_iop_s *s = (s5l8930_iop_s *) qemu_mallocz(sizeof(s5l8930_iop_s));
    s5l8930_state *s5l8930 = opaque;
	CPUState *env;
    qemu_irq *cpu_irq;
    DeviceState *dev, *dev_prev;
    int i,j;

    env = cpu_init("cortex-a8");
    if(!env) {
        fprintf(stderr, "Unable to find CPU for IOP proccess definition\n");
        exit(1);
    }

  	cpu_irq = arm_pic_init_cpu(env);

    // Allocate 4 vic controllers
    s->irq = qemu_mallocz(S5L8930_ARM7_VIC_N * sizeof(qemu_irq *));
    dev = pl192_init(S5L8930_ARM7_VIC_BASE, 4,
                     cpu_irq[ARM_PIC_CPU_IRQ],
                     cpu_irq[ARM_PIC_CPU_FIQ], NULL);
    // Each with 32 irq's
    s->irq[0] = qemu_mallocz(S5L8930_ARM7_VIC_SIZE * sizeof(qemu_irq));
    for (i = 0; i < S5L8930_ARM7_VIC_SIZE; i++)
        s->irq[0][i] = qdev_get_gpio_in(dev, i);
    for (j = 1; j < S5L8930_ARM7_VIC_N; j++) {
        dev_prev = dev;
        dev = pl192_init(S5L8930_ARM7_VIC_BASE + S5L8930_ARM7_VIC_SHIFT * j, 4+j, NULL);

        s->irq[j] = qemu_mallocz(S5L8930_ARM7_VIC_SIZE * sizeof(qemu_irq));
        for (i = 0; i < S5L8930_ARM7_VIC_SIZE; i++)
            s->irq[j][i] = qdev_get_gpio_in(dev, i);
        pl192_chain(sysbus_from_qdev(dev_prev), sysbus_from_qdev(dev));
    }


    uint32_t base = 0x86300000;
    s->name = name0;
	s->s5l8930env = s5l8930->env;
	s->iopenv = env;
	s->cdma = s5l8930->cdma;
	s->timer = s5l8930->timer;
	s->iopirq = s5l8930_get_irq(s5l8930, S5L8930_IOP_IRQ);
    io = cpu_register_io_memory(s5l8930_iop_readfn, s5l8930_iop_writefn, s, DEVICE_LITTLE_ENDIAN);
    cpu_register_physical_memory(base, 0x1000, io);

	setTimerIRQ2(s->timer, s5l8930_iop_get_irq(s, S5L8930_TIMER0_IRQ));
	IOPCpuState = s->iopenv;
	MainCpuState = s5l8930->env;
	IOPState = s;
	cpu_interrupt(env, CPU_INTERRUPT_HALT);
}
Example #8
0
void board_init(void)
{
    /* initialize core clocks via CMSIS function provided by Atmel */
    SystemInit();

    /* initialize the CPU */
    cpu_init();

    /* initialize the boards LEDs */
    led_init();
}
static void dummy_ppc_init(ram_addr_t ram_size, int vga_ram_size,
                     const char *boot_device, DisplayState *ds,
                     const char *kernel_filename, const char *kernel_cmdline,
                     const char *initrd_filename, const char *cpu_model)
{
    CPUState *env;
    int kernel_size;
    uint64_t elf_entry;
    target_ulong entry;

    if (!cpu_model)
        cpu_model = "default";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find ppc CPU definition\n");
        exit(1);
    }

    cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
    /* RAM at address zero */
    cpu_register_physical_memory(0x10000000, ram_size,
        qemu_ram_alloc(ram_size) | IO_MEM_RAM);

    /* Load kernel.  */
    if (kernel_filename) {
        kernel_size = load_elf(kernel_filename, 0, &elf_entry, NULL, NULL);
        entry = elf_entry;
        if (kernel_size < 0) {
            kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
        }
        if (kernel_size < 0) {
            kernel_size = load_image(kernel_filename, phys_ram_base);
            entry = 0;
        }
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    } else {
        entry = 0;
    }
    env->nip = entry;
    if (semihosting_enabled) {
        /* Setup initial stack.  */
        target_ulong *p;
        p = (target_ulong *)(phys_ram_base + ram_size);
        *(--p) = 0;
        *(--p) = 0;
        env->gpr[1] = 0x10000000 + ram_size - 2 * sizeof(target_ulong);
        /* Enable FPU.  */
        env->msr |= (1 << MSR_FP);
    }
}
Example #10
0
static int
cpu_ll_setup(perf_cpu_t *cpu, void *arg)
{
	cpu_init(cpu);
	if (pf_ll_setup(cpu, &s_ll_conf) != 0) {
		pf_resource_free(cpu);
		return (-1);
	}

	return (0);
}
Example #11
0
int main(void) {
	cpu_init();
	P1IFG = 0x00;
	uart_init();

	delayMs(1000);

	__enable_interrupt();

	/* Initialize RFM-module */
	rf12_initialize(2, RF12_433MHZ, 33);

	uint8_t c = 0;
	uart_puts("Hello\n");
	uint8_t payload[1];

	bool sendAck = false;
	while (true) {
		if (rf12_recvDone() && rf12_crc == 0) {
			switch(rf12_data[0]) {
			case PACKET_BAT_LEVEL:
				uart_puts("BATTERY LEVEL: ");
				uart_puts(rf12_data+1);
				break;
			case PACKET_SIGNAL:
				uart_puts("SIGNAL: ");
				uart_puts(rf12_data+1);
				break;
			default:
				uart_puts("UNKNOWN");
				break;
			}
			uart_putc('\n');
		}


		if (uart_getc(&c)) {
			if( c == 'I' ) {
				uart_putc('O');
				uart_putc('\n');
			}
		}

		/* Power down */
		// Only power down, if there is nothing to do

		if( !isReceiving && rxstate == TXRECV) {
			__bis_SR_register(LPM3_bits | GIE);
		}
	}

	return 0;
}
Example #12
0
/*
 * Activate a secondary processor.
 */
notrace static void __cpuinit start_secondary(void *unused)
{
	/*
	 * Don't put *anything* before cpu_init(), SMP booting is too
	 * fragile that we want to limit the things done here to the
	 * most necessary things.
	 */
	cpu_init();
	x86_cpuinit.early_percpu_clock_init();
	preempt_disable();
	smp_callin();

	enable_start_cpu0 = 0;

	/* otherwise gcc will move up smp_processor_id before the cpu_init */
	barrier();

	/* switch away from the initial page table */
#ifdef CONFIG_PAX_PER_CPU_PGD
	load_cr3(get_cpu_pgd(smp_processor_id(), kernel));
	__flush_tlb_all();
#elif defined(CONFIG_X86_32)
	load_cr3(swapper_pg_dir);
	__flush_tlb_all();
#endif

	/*
	 * Check TSC synchronization with the BP:
	 */
	check_tsc_sync_target();

	/*
	 * We need to hold vector_lock so there the set of online cpus
	 * does not change while we are assigning vectors to cpus.  Holding
	 * this lock ensures we don't half assign or remove an irq from a cpu.
	 */
	lock_vector_lock();
	set_cpu_online(smp_processor_id(), true);
	unlock_vector_lock();
	per_cpu(cpu_state, smp_processor_id()) = CPU_ONLINE;
	x86_platform.nmi_init();

	/* enable local interrupts */
	local_irq_enable();

	/* to prevent fake stack check failure in clock setup */
	boot_init_stack_canary();

	x86_cpuinit.setup_percpu_clockev();

	wmb();
	cpu_startup_entry(CPUHP_ONLINE);
}
Example #13
0
void board_init(void)
{
    /* enable access to the evaluation board controller chip. Without this, the
     * board controller does not forward the UART output to the USB port */
    gpio_init(BC_PIN, GPIO_OUT);
    gpio_set(BC_PIN);
    /* initialize the boards LEDs */
    gpio_init(LED0_PIN, GPIO_OUT);
    gpio_init(LED1_PIN, GPIO_OUT);
    /* initialize the CPU */
    cpu_init();
}
Example #14
0
/*
 * Power collapse the Apps processor without involving Modem.
 *
 * Return value:
 *      0: success
 */
static int __ref msm_pm_power_collapse_standalone(bool from_idle)
{
	int collapsed = 0;
	int ret;
	void *entry;

	MSM_PM_DPRINTK(MSM_PM_DEBUG_SUSPEND|MSM_PM_DEBUG_POWER_COLLAPSE,
		KERN_INFO, "%s()\n", __func__);

	ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_POWER_COLLAPSE, false);
	WARN_ON(ret);

	entry = (!smp_processor_id() || from_idle) ?
			msm_pm_collapse_exit : msm_secondary_startup;

	msm_pm_boot_config_before_pc(smp_processor_id(),
						virt_to_phys(entry));

#ifdef CONFIG_VFP
	vfp_pm_suspend();
#endif

#ifdef CONFIG_CACHE_L2X0
	if (!cpu_is_msm8625())
		l2cc_suspend();
#endif

	collapsed = msm_pm_collapse();

#ifdef CONFIG_CACHE_L2X0
	if (!cpu_is_msm8625())
		l2cc_resume();
#endif

	msm_pm_boot_config_after_pc(smp_processor_id());

	if (collapsed) {
#ifdef CONFIG_VFP
		vfp_pm_resume();
#endif
		cpu_init();
		local_fiq_enable();
	}

	MSM_PM_DPRINTK(MSM_PM_DEBUG_SUSPEND | MSM_PM_DEBUG_POWER_COLLAPSE,
		KERN_INFO,
		"%s(): msm_pm_collapse returned %d\n", __func__, collapsed);

	ret = msm_spm_set_low_power_mode(MSM_SPM_MODE_CLOCK_GATING, false);
	WARN_ON(ret);

	return !collapsed;
}
Example #15
0
void emu_init(char* args){
	hal_init();
//	mem_init();
// init the ppu before rom otherwise set_mirroring will not work
	ppu_init();
	rom_init();
	readrom(args);
	cpu_init(&cpu);
	
	cpu_reset(&cpu);
	emu_running = true;
}
Example #16
0
static void dummy_m68k_init(QEMUMachineInitArgs *args)
{
    ram_addr_t ram_size = args->ram_size;
    const char *cpu_model = args->cpu_model;
    const char *kernel_filename = args->kernel_filename;
    CPUM68KState *env;
    MemoryRegion *address_space_mem =  get_system_memory();
    MemoryRegion *ram = g_new(MemoryRegion, 1);
    int kernel_size;
    uint64_t elf_entry;
    hwaddr entry;

    if (!cpu_model)
        cpu_model = "cfv4e";
    env = cpu_init(cpu_model);
    if (!env) {
        fprintf(stderr, "Unable to find m68k CPU definition\n");
        exit(1);
    }

    /* Initialize CPU registers.  */
    env->vbr = 0;

    /* RAM at address zero */
    memory_region_init_ram(ram, "dummy_m68k.ram", ram_size);
    vmstate_register_ram_global(ram);
    memory_region_add_subregion(address_space_mem, 0, ram);

    /* Load kernel.  */
    if (kernel_filename) {
        kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
                               NULL, NULL, 1, ELF_MACHINE, 0);
        entry = elf_entry;
        if (kernel_size < 0) {
            kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL);
        }
        if (kernel_size < 0) {
            kernel_size = load_image_targphys(kernel_filename,
                                              KERNEL_LOAD_ADDR,
                                              ram_size - KERNEL_LOAD_ADDR);
            entry = KERNEL_LOAD_ADDR;
        }
        if (kernel_size < 0) {
            fprintf(stderr, "qemu: could not load kernel '%s'\n",
                    kernel_filename);
            exit(1);
        }
    } else {
        entry = 0;
    }
    env->pc = entry;
}
Example #17
0
int main(int argc, char **argv) {

	int i;

	u_int32_t actual_program_counter = 0;// actual_pcb->program_counter;

    if (cpu_init(argc, argv[1])<0) return 0;

    cpu_state_machine();

    log_info(cpu_log, "=== Exiting CPU ===");
    return 0;
}
Example #18
0
void board_init(void)
{
    /* initialize the CPU */
    cpu_init();
    /* initialize the boards LEDs */
    leds_init();
    /* disable systick interrupt, set by the spark bootloader */
    SysTick->CTRL = 0;
    /* signal to spark bootloader: do not enable IWDG! set Stop Mode Flag! */
    BKP->DR9 = 0xAFFF;
    /* configure the RIOT vector table location to internal flash + spark bootloader offset */
    SCB->VTOR = LOCATION_VTABLE;
}
Example #19
0
/*
 * Activate a secondary processor.  head.S calls this.
 */
int __devinit
start_secondary (void *unused)
{
	/* Early console may use I/O ports */
	ia64_set_kr(IA64_KR_IO_BASE, __pa(ia64_iobase));
	Dprintk("start_secondary: starting CPU 0x%x\n", hard_smp_processor_id());
	efi_map_pal_code();
	cpu_init();
	smp_callin();

	cpu_idle();
	return 0;
}
Example #20
0
File: board.c Project: attdona/RIOT
/**
 * @brief Initialize the board
 */
void board_init(void) {

    MAP_PRCMPeripheralClkEnable(PRCM_GPIOA0, PRCM_RUN_MODE_CLK);
    MAP_PRCMPeripheralClkEnable(PRCM_GPIOA1, PRCM_RUN_MODE_CLK);
    MAP_PRCMPeripheralClkEnable(PRCM_GPIOA2, PRCM_RUN_MODE_CLK);
    MAP_PRCMPeripheralClkEnable(PRCM_GPIOA3, PRCM_RUN_MODE_CLK);

    /* initialize the CPU */
    cpu_init();

    /* initialize the boards LEDs */
    led_init();
}
Example #21
0
void board_init(void)
{
    /* initialize the on-board LEDs */
    gpio_init(LED0_PIN, GPIO_OUT);
    gpio_set(LED0_PIN);
    gpio_init(LED1_PIN, GPIO_OUT);
    gpio_set(LED1_PIN);
    gpio_init(LED2_PIN, GPIO_OUT);
    gpio_set(LED2_PIN);

    /* initialize the CPU core */
    cpu_init();
}
Example #22
0
File: tests.c Project: lmb/Spielbub
/* -------------------------------------------------------------------------- */
void cpu_setup_test(context_t *ctx, uint8_t opcode)
{
    // This resets all registers.
    cpu_init(&ctx->cpu);
    
    ctx->mem.map[ctx->cpu.PC] = opcode;
    
    // Point HL into "safe" ram:
    // < 0x8000 goes to memory controller;
    // >= 0xFF00 writes to various ioregs,
    // which will cause problems.
    ctx->cpu.HL = 0x8001;
}
Example #23
0
/*
 * Activate a secondary processor.
 */
static void notrace start_secondary(void *unused)
{
	/*
	 * Don't put *anything* before cpu_init(), SMP booting is too
	 * fragile that we want to limit the things done here to the
	 * most necessary things.
	 */
	cpu_init();
	x86_cpuinit.early_percpu_clock_init();
	preempt_disable();
	smp_callin();

	enable_start_cpu0 = 0;

#ifdef CONFIG_X86_32
	/* switch away from the initial page table */
	load_cr3(swapper_pg_dir);
	__flush_tlb_all();
#endif

	/* otherwise gcc will move up smp_processor_id before the cpu_init */
	barrier();
	/*
	 * Check TSC synchronization with the BP:
	 */
	check_tsc_sync_target();

	/*
	 * Lock vector_lock and initialize the vectors on this cpu
	 * before setting the cpu online. We must set it online with
	 * vector_lock held to prevent a concurrent setup/teardown
	 * from seeing a half valid vector space.
	 */
	lock_vector_lock();
	setup_vector_irq(smp_processor_id());
	set_cpu_online(smp_processor_id(), true);
	unlock_vector_lock();
	cpu_set_state_online(smp_processor_id());
	x86_platform.nmi_init();

	/* enable local interrupts */
	local_irq_enable();

	/* to prevent fake stack check failure in clock setup */
	boot_init_stack_canary();

	x86_cpuinit.setup_percpu_clockev();

	wmb();
	cpu_startup_entry(CPUHP_ONLINE);
}
Example #24
0
/* ------------------------------------------------------------------------*//**
 * @FUNCTION		cpu_force
 * @BRIEF		Force cpu detection.
 * @RETURNS		0 on success
 *			OMAPCONF_ERR_ARG
 * @param[in]		forced_cpu: name of the force cpu
 * @DESCRIPTION		Force cpu detection.
 *//*------------------------------------------------------------------------ */
int cpu_force(char *forced_cpu)
{
	if (forced_cpu == NULL) {
		fprintf(stderr,
			"%s(): forced_cpu == NULL!\n", __func__);
		return OMAPCONF_ERR_ARG;
	}

	cpu_init();
	if (strcmp(forced_cpu, "omap5430") == 0) {
		cpu_forced_set(1);
		cpu_set(OMAP_5430);
		cpu_device_type_set(DEV_GP);
		cpu_revision_set(REV_ES1_0);
		cpu_silicon_type_set(STANDARD_PERF_SI);
		cpu_full_name_set();
	} else if (strcmp(forced_cpu, "omap5432") == 0) {
		cpu_forced_set(1);
		cpu_set(OMAP_5432);
		cpu_device_type_set(DEV_GP);
		cpu_revision_set(REV_ES1_0);
		cpu_silicon_type_set(STANDARD_PERF_SI);
		cpu_full_name_set();
	} else if (strcmp(forced_cpu, "omap4430") == 0) {
		cpu_forced_set(1);
		cpu_set(OMAP_4430);
		cpu_device_type_set(DEV_GP);
		cpu_revision_set(REV_ES2_2);
		cpu_silicon_type_set(STANDARD_PERF_SI);
		cpu_full_name_set();
	} else if (strcmp(forced_cpu, "omap4460") == 0) {
		cpu_forced_set(1);
		cpu_set(OMAP_4460);
		cpu_device_type_set(DEV_GP);
		cpu_revision_set(REV_ES1_1);
		cpu_silicon_type_set(STANDARD_PERF_SI);
		cpu_full_name_set();
	} else if (strcmp(forced_cpu, "omap4470") == 0) {
		cpu_forced_set(1);
		cpu_set(OMAP_4470);
		cpu_device_type_set(DEV_GP);
		cpu_revision_set(REV_ES1_0);
		cpu_silicon_type_set(STANDARD_PERF_SI);
		cpu_full_name_set();
	} else {
		return OMAPCONF_ERR_ARG;
	}

	cpu_forced_set(1);
	return 0;
}
Example #25
0
void emulator_load(const char *rom)
{
	ines_unloadrom();
	ines_loadrom(rom);

	mapper_make_current(c_rom->mapper);
	mapper_reset();
	
	cpu_init();
	ppu_init();
	papu_init(EMULATOR_DEF_SOUND_SAMLE_RATE, EMULATOR_DEF_SOUND_DURATION);

	emulator_last_tick = 0;
}
Example #26
0
int entry(unsigned int cpu_id, struct per_cpu *cpu_data)
{
	static volatile bool activate;
	bool master = false;

	cpu_data->cpu_id = cpu_id;

	spin_lock(&init_lock);

	if (master_cpu_id == -1) {
		master = true;
		init_early(cpu_id);
	}

	if (!error)
		cpu_init(cpu_data);

	spin_unlock(&init_lock);

	while (!error && initialized_cpus < hypervisor_header.online_cpus)
		cpu_relax();

	if (!error && master) {
		init_late(cpu_data);
		if (!error) {
			/*
			 * Make sure everything was committed before we signal
			 * the other CPUs that they can continue.
			 */
			memory_barrier();
			activate = true;
		}
	} else {
		while (!error && !activate)
			cpu_relax();
	}

	if (error) {
		if (master)
			arch_shutdown();
		arch_cpu_restore(cpu_data);
		return error;
	}

	if (master)
		printk("Activating hypervisor\n");

	/* point of no return */
	arch_cpu_activate_vmm(cpu_data);
}
Example #27
0
static inline void play_dead(void)
{
	extern void idle_task_exit(void); /* XXXAP find proper place */

	idle_task_exit();
	local_irq_disable();
	cpu_clear(smp_processor_id(), cpu_initialized);
	preempt_enable_no_resched();
	HYPERVISOR_vcpu_op(VCPUOP_down, smp_processor_id(), NULL);
	/* Same as arch/xen/kernel/smpboot.c:cpu_bringup(). */
	cpu_init();
	preempt_disable();
	local_irq_enable();
}
Example #28
0
int main(int argc, char * argv[]) {
    if (argc != 2) {
        usage(argv[0]);
        exit(1);
    }
    
    if (SDL_Init(SDL_INIT_VIDEO) != 0) {
        printf("Echec init : %s\n", SDL_GetError());
        exit(1);
    }

    GBContext   *cpu = cpu_init(argv[1]);
    GPUContext  *gpu = gpu_init(cpu);
    JOYPContext *joyp = joyp_init(cpu);
    
    uint8_t op;
    unsigned int start_time, last_time, elapsed_time;
    while (!cpu->exit) {
        start_time = SDL_GetTicks();

        while (cpu->t_clock < VSYNC_CYCLES) {
            op = read8(cpu, cpu->PC++);
            execute(cpu, op);
            
            //"realtime" operations must be here..
            cpu_ctx_update(cpu);
            gpu_ctx_update(cpu, gpu);
            joyp_ctx_update(cpu, joyp);
            handle_interrupt(cpu);
        }
        cpu->t_clock = 0;

        last_time = SDL_GetTicks();
        elapsed_time = last_time - start_time;
        if(elapsed_time < VSYNC_TIME_MS) {// just a basic frame rate wait loop
            SDL_Delay(VSYNC_TIME_MS - elapsed_time);
        }
        
        gpu_render(cpu, gpu);
//        printf("elapsed: %d\n", elapsed_time);
    }

    
    joyp_destroy(joyp);
    gpu_destroy(gpu);
    cpu_destroy(cpu);
    SDL_Quit();

    return 0;
}
Example #29
0
File: shix.c Project: slotfi64/qemu
static void shix_init(QEMUMachineInitArgs *args)
{
    const char *cpu_model = args->cpu_model;
    int ret;
    CPUSH4State *env;
    struct SH7750State *s;
    MemoryRegion *sysmem = get_system_memory();
    MemoryRegion *rom = g_new(MemoryRegion, 1);
    MemoryRegion *sdram = g_new(MemoryRegion, 2);
    
    if (!cpu_model)
        cpu_model = "any";

    printf("Initializing CPU\n");
    env = cpu_init(cpu_model);

    /* Allocate memory space */
    printf("Allocating ROM\n");
    memory_region_init_ram(rom, "shix.rom", 0x4000);
    vmstate_register_ram_global(rom);
    memory_region_set_readonly(rom, true);
    memory_region_add_subregion(sysmem, 0x00000000, rom);
    printf("Allocating SDRAM 1\n");
    memory_region_init_ram(&sdram[0], "shix.sdram1", 0x01000000);
    vmstate_register_ram_global(&sdram[0]);
    memory_region_add_subregion(sysmem, 0x08000000, &sdram[0]);
    printf("Allocating SDRAM 2\n");
    memory_region_init_ram(&sdram[1], "shix.sdram2", 0x01000000);
    vmstate_register_ram_global(&sdram[1]);
    memory_region_add_subregion(sysmem, 0x0c000000, &sdram[1]);

    /* Load BIOS in 0 (and access it through P2, 0xA0000000) */
    if (bios_name == NULL)
        bios_name = BIOS_FILENAME;
    printf("%s: load BIOS '%s'\n", __func__, bios_name);
    ret = load_image_targphys(bios_name, 0, 0x4000);
    if (ret < 0) {		/* Check bios size */
	fprintf(stderr, "ret=%d\n", ret);
	fprintf(stderr, "qemu: could not load SHIX bios '%s'\n",
		bios_name);
	exit(1);
    }

    /* Register peripherals */
    s = sh7750_init(env, sysmem);
    /* XXXXX Check success */
    tc58128_init(s, "shix_linux_nand.bin", NULL);
    fprintf(stderr, "initialization terminated\n");
}
Example #30
0
int main(void)
{
  int status;
  char buf[256];
  uint8_t commandbyte;
  uint8_t responsebyte;

  cpu_init(DEFAULT_CPU_FREQ);

#ifdef CONSOLE_SERIAL
  serial_stdio(CONSOLE_PORT);
#endif

#ifdef CONSOLE_SEMIHOSTING
  semihosting_stdio(CONSOLE_PORT)
#endif

#ifdef CONSOLE_USB
  usb_serial_stdio(NULL);
  getch();
#endif

  printf("\033[H\033[2J%s SPI Master Test (" __DATE__ " " __TIME__ ")\n\n", MCUFAMILYNAME);
  puts(revision);
  printf("\nCPU Freq:%u Hz  Compiler:%s %s %s\n\n", (unsigned int) SystemCoreClock,
    __COMPILER__, __VERSION__, __ABI__);

  if ((status = spi_master_init(SPI_PORT, 8, 0, 281250, SPI_MSBFIRST)))
  {
    printf("ERROR: spi_master_init() failed at line %d, %s\n", status, strerror(errno));
    exit(1);
  }

  for (;;)
  {
    printf("Enter a value to send: ");

    gets(buf);
    commandbyte = atoi(buf);

    if ((status = spi_master_transfer(SPI_PORT, &commandbyte, 1, &responsebyte, 1)))
    {
      printf("ERROR: spi_master_transfer() failed at line %d, %s\n", status, strerror(errno));
      exit(1);
    }

    printf("Response was %02X\n\n", responsebyte);
  }
}