static void omap_init_audio(void) { platform_device_register(&omap_mcbsp1); platform_device_register(&omap_mcbsp2); if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { platform_device_register(&omap_mcbsp3); platform_device_register(&omap_mcbsp4); } if (cpu_is_omap243x() || cpu_is_omap34xx()) platform_device_register(&omap_mcbsp5); platform_device_register(&omap_pcm); }
void __init usb_musb_init(void) { if (cpu_is_omap243x()) { musb_resources[0].start = OMAP243X_HS_BASE; musb_plat.clock = "usbhs_ick"; } else { musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; musb_plat.clock = "hsotgusb_ick"; } musb_resources[0].end = musb_resources[0].start + SZ_8K - 1; #ifdef CONFIG_NOP_USB_XCEIV if (platform_device_register(&nop_xceiv_device) < 0) { printk(KERN_ERR "Unable to register NOP-XCEIV device\n"); return; } #endif if (platform_device_register(&musb_device) < 0) { printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); return; } usb_musb_pm_init(); }
/* * The amount of SRAM depends on the core type. * Note that we cannot try to test for SRAM here because writes * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. */ static void __init omap_detect_sram(void) { omap_sram_skip = SRAM_BOOTLOADER_SZ; if (is_sram_locked()) { if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PUB_PA; if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { omap_sram_size = 0x7000; /* 28K */ omap_sram_skip += SZ_16K; } else { omap_sram_size = 0x8000; /* 32K */ } } else { omap_sram_start = OMAP2_SRAM_PUB_PA; omap_sram_size = 0x800; /* 2K */ } } else { if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ } else { omap_sram_start = OMAP2_SRAM_PA; if (cpu_is_omap242x()) omap_sram_size = 0xa0000; /* 640K */ else if (cpu_is_omap243x()) omap_sram_size = 0x10000; /* 64K */ } } }
void __init usb_musb_init(struct omap_musb_board_data *board_data) { if (cpu_is_omap243x()) { musb_resources[0].start = OMAP243X_HS_BASE; } else if (cpu_is_omap34xx()) { musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; } else if (cpu_is_omap44xx()) { musb_resources[0].start = OMAP44XX_HSUSB_OTG_BASE; musb_resources[1].start = OMAP44XX_IRQ_HS_USB_MC_N; musb_resources[2].start = OMAP44XX_IRQ_HS_USB_DMA_N; } musb_resources[0].end = musb_resources[0].start + SZ_4K - 1; /* * REVISIT: This line can be removed once all the platforms using * musb_core.c have been converted to use use clkdev. */ musb_plat.clock = "ick"; musb_plat.board_data = board_data; musb_plat.power = board_data->power >> 1; musb_plat.mode = board_data->mode; if (platform_device_register(&musb_device) < 0) printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); }
void __init usb_musb_init(void) { if (cpu_is_omap243x()) musb_resources[0].start = OMAP243X_HS_BASE; else musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; musb_resources[0].end = musb_resources[0].start + SZ_8K - 1; /* * REVISIT: This line can be removed once all the platforms using * musb_core.c have been converted to use use clkdev. */ musb_plat.clock = "ick"; #ifdef CONFIG_NOP_USB_XCEIV if (platform_device_register(&nop_xceiv_device) < 0) { printk(KERN_ERR "Unable to register NOP-XCEIV device\n"); return; } #endif if (platform_device_register(&musb_device) < 0) { printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); return; } }
void __init omap243x_clockdomains_init(void) { if (!cpu_is_omap243x()) return; clkdm_register_platform_funcs(&omap2_clkdm_operations); clkdm_register_clkdms(clockdomains_omap243x); clkdm_complete_init(); }
/* * The amount of SRAM depends on the core type. * Note that we cannot try to test for SRAM here because writes * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. */ static void __init omap_detect_sram(void) { omap_sram_skip = SRAM_BOOTLOADER_SZ; if (cpu_class_is_omap2()) { if (is_sram_locked()) { if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PUB_PA; if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { omap_sram_size = 0x7000; /* 28K */ omap_sram_skip += SZ_16K; } else { omap_sram_size = 0x8000; /* 32K */ } } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_PUB_PA; omap_sram_size = 0xa000; /* 40K */ } else { omap_sram_start = OMAP2_SRAM_PUB_PA; omap_sram_size = 0x800; /* 2K */ } } else { if (cpu_is_am33xx()) { omap_sram_start = AM33XX_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ } else if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_PA; omap_sram_size = 0xe000; /* 56K */ } else { omap_sram_start = OMAP2_SRAM_PA; if (cpu_is_omap242x()) omap_sram_size = 0xa0000; /* 640K */ else if (cpu_is_omap243x()) omap_sram_size = 0x10000; /* 64K */ } } } else { omap_sram_start = OMAP1_SRAM_PA; if (cpu_is_omap7xx()) omap_sram_size = 0x32000; /* 200K */ else if (cpu_is_omap15xx()) omap_sram_size = 0x30000; /* 192K */ else if (cpu_is_omap1610() || cpu_is_omap1611() || cpu_is_omap1621() || cpu_is_omap1710()) omap_sram_size = 0x4000; /* 16K */ else { pr_err("Could not detect SRAM size\n"); omap_sram_size = 0x4000; } } }
static void omap_init_audio(void) { #ifndef CONFIG_MACH_OMAP4_JET struct omap_hwmod *oh_hdmi; struct omap_device *od_hdmi, *od_hdmi_codec; char *oh_hdmi_name = "dss_hdmi"; char *dev_hdmi_name = "hdmi-audio-dai"; char *dev_hdmi_codec_name = "omap-hdmi-codec"; if (cpu_is_omap44xx()) { oh_hdmi = omap_hwmod_lookup(oh_hdmi_name); WARN(!oh_hdmi, "%s: could not find omap_hwmod for %s\n", __func__, oh_hdmi_name); od_hdmi = omap_device_build(dev_hdmi_name, -1, oh_hdmi, NULL, 0, NULL, 0, false); WARN(IS_ERR(od_hdmi), "%s: could not build omap_device for %s\n", __func__, dev_hdmi_name); od_hdmi_codec = omap_device_build(dev_hdmi_codec_name, -1, oh_hdmi, NULL, 0, NULL, 0, false); WARN(IS_ERR(od_hdmi_codec), "%s: could not build omap_device for %s\n", __func__, dev_hdmi_codec_name); platform_device_register(&omap4_hdmi_audio); } #endif platform_device_register(&omap_mcbsp1); platform_device_register(&omap_mcbsp2); if (cpu_is_omap243x() || cpu_is_omap34xx() || cpu_is_omap44xx()) { platform_device_register(&omap_mcbsp3); platform_device_register(&omap_mcbsp4); } if (cpu_is_omap243x() || cpu_is_omap34xx()) platform_device_register(&omap_mcbsp5); platform_device_register(&omap_pcm); }
/** * omap_ctrl_write_dsp_boot_mode - set boot mode for a remote processor * @bootmode: 8-bit value to pass to some boot code * * Sets boot mode for the boot loader of a supported processor * when a power ON sequence occurs. */ void omap_ctrl_write_dsp_boot_mode(u8 bootmode) { u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTMOD : cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTMOD : 0; if (!offset) { pr_err("%s: unsupported omap type\n", __func__); return; } omap_ctrl_writel(bootmode, offset); }
void omap_start_dma(int lch) { u32 l; if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) { int next_lch, cur_lch; char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT]; dma_chan_link_map[lch] = 1; /* Set the link register of the first channel */ enable_lnk(lch); memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map)); cur_lch = dma_chan[lch].next_lch; do { next_lch = dma_chan[cur_lch].next_lch; /* The loop case: we've been here already */ if (dma_chan_link_map[cur_lch]) break; /* Mark the current channel */ dma_chan_link_map[cur_lch] = 1; enable_lnk(cur_lch); omap_enable_channel_irq(cur_lch); cur_lch = next_lch; } while (next_lch != -1); } else if (cpu_is_omap242x() || (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) { /* Errata: Need to write lch even if not using chaining */ dma_write(lch, CLNK_CTRL(lch)); } omap_enable_channel_irq(lch); l = dma_read(CCR(lch)); /* * Errata: On ES2.0 BUFFERING disable must be set. * This will always fail on ES1.0 */ if (cpu_is_omap24xx()) l |= OMAP_DMA_CCR_EN; l |= OMAP_DMA_CCR_EN; dma_write(l, CCR(lch)); dma_chan[lch].flags |= OMAP_DMA_ACTIVE; }
/** * omap_ctrl_write_dsp_boot_addr - set boot address for a remote processor * @bootaddr: physical address of the boot loader * * Set boot address for the boot loader of a supported processor * when a power ON sequence occurs. */ void omap_ctrl_write_dsp_boot_addr(u32 bootaddr) { u32 offset = cpu_is_omap243x() ? OMAP243X_CONTROL_IVA2_BOOTADDR : cpu_is_omap34xx() ? OMAP343X_CONTROL_IVA2_BOOTADDR : cpu_is_omap44xx() ? OMAP4_CTRL_MODULE_CORE_DSP_BOOTADDR : 0; if (!offset) { pr_err("%s: unsupported omap type\n", __func__); return; } omap_ctrl_writel(bootaddr, offset); }
void __init usb_musb_init(void) { if (cpu_is_omap243x()) musb_resources[0].start = OMAP243X_HS_BASE; else musb_resources[0].start = OMAP34XX_HSUSB_OTG_BASE; musb_resources[0].end = musb_resources[0].start + SZ_8K - 1; musb_plat.clock = "ick"; if (platform_device_register(&musb_device) < 0) { printk(KERN_ERR "Unable to register HS-USB (MUSB) device\n"); return; } }
static void __init omap_generic_map_io(void) { if (cpu_is_omap242x()) { omap2_set_globals_242x(); omap242x_map_common_io(); } else if (cpu_is_omap243x()) { omap2_set_globals_243x(); omap243x_map_common_io(); } else if (cpu_is_omap34xx()) { omap2_set_globals_3xxx(); omap34xx_map_common_io(); } else if (cpu_is_omap44xx()) { omap2_set_globals_443x(); omap44xx_map_common_io(); } }
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { u8 skip_setup_idle = 0; if (cpu_is_omap24xx() || cpu_is_omap34xx()) pwrdm_init(powerdomains_omap, &omap2_pwrdm_functions); else if (cpu_is_omap44xx()) pwrdm_init(powerdomains_omap, &omap4_pwrdm_functions); clkdm_init(clockdomains_omap, clkdm_autodeps); if (cpu_is_omap242x()) omap2420_hwmod_init(); else if (cpu_is_omap243x()) omap2430_hwmod_init(); else if (cpu_is_omap34xx()) omap3xxx_hwmod_init(); else if (cpu_is_omap44xx()) omap44xx_hwmod_init(); omap_pm_if_early_init(); if (cpu_is_omap2420()) omap2420_clk_init(); else if (cpu_is_omap2430()) omap2430_clk_init(); else if (cpu_is_omap34xx()) omap3xxx_clk_init(); else if (cpu_is_omap44xx()) omap4xxx_clk_init(); else pr_err("Could not init clock framework - unknown CPU\n"); omap_serial_early_init(); #ifndef CONFIG_PM_RUNTIME skip_setup_idle = 1; #endif omap_hwmod_late_init(skip_setup_idle); if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); #ifndef CONFIG_FB_OMAP_BOOTLOADER_INIT _omap2_init_reprogram_sdrc(); #endif } gpmc_init(); omap2_dm_timer_early_init(); }
void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, struct omap_sdrc_params *sdrc_cs1) { u8 skip_setup_idle = 0; pwrdm_init(powerdomains_omap); clkdm_init(clockdomains_omap, clkdm_autodeps); if (cpu_is_omap242x()) omap2420_hwmod_init(); else if (cpu_is_omap243x()) omap2430_hwmod_init(); else if (cpu_is_omap34xx()) omap3xxx_hwmod_init(); /* The OPP tables have to be registered before a clk init */ omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); if (cpu_is_omap2420()) omap2420_clk_init(); else if (cpu_is_omap2430()) omap2430_clk_init(); else if (cpu_is_omap34xx()) omap3xxx_clk_init(); else if (cpu_is_omap44xx()) omap4xxx_clk_init(); else pr_err("Could not init clock framework - unknown CPU\n"); omap_serial_early_init(); #ifndef CONFIG_PM_RUNTIME skip_setup_idle = 1; #endif if (cpu_is_omap24xx() || cpu_is_omap34xx()) /* FIXME: OMAP4 */ omap_hwmod_late_init(skip_setup_idle); if (cpu_is_omap24xx() || cpu_is_omap34xx()) { omap2_sdrc_init(sdrc_cs0, sdrc_cs1); _omap2_init_reprogram_sdrc(); } gpmc_init(); }
/* * The amount of SRAM depends on the core type. * Note that we cannot try to test for SRAM here because writes * to secure SRAM will hang the system. Also the SRAM is not * yet mapped at this point. */ static void __init omap_detect_sram(void) { if (cpu_class_is_omap2()) { if (is_sram_locked()) { if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PUB_PA; if ((omap_type() == OMAP2_DEVICE_TYPE_EMU) || (omap_type() == OMAP2_DEVICE_TYPE_SEC)) { omap_sram_size = 0x7000; /* 28K */ } else { omap_sram_size = 0x8000; /* 32K */ } } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_START_PA; omap_sram_size = OMAP4_SRAM_SIZE; /* 56KB */ omap_sram_size -= OMAP4_SRAM_HS_RESERVE; omap_sram_start += OMAP4_SRAM_HS_RESERVE; } else if (cpu_is_omap54xx()) { omap_sram_start = OMAP4_SRAM_START_PA; omap_sram_size = OMAP5_SRAM_SIZE; /* 128KB */ omap_sram_size -= OMAP5_SRAM_HS_RESERVE; omap_sram_start += OMAP5_SRAM_HS_RESERVE; } else { omap_sram_start = OMAP2_SRAM_PUB_PA; omap_sram_size = 0x800; /* 2K */ } } else { if (cpu_is_am33xx()) { omap_sram_start = AM33XX_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ } else if (cpu_is_omap34xx()) { omap_sram_start = OMAP3_SRAM_PA; omap_sram_size = 0x10000; /* 64K */ } else if (cpu_is_omap44xx()) { omap_sram_start = OMAP4_SRAM_START_PA; omap_sram_size = OMAP4_SRAM_SIZE; /* 56K */ omap_sram_size -= OMAP4_SRAM_GP_RESERVE; omap_sram_start += OMAP4_SRAM_GP_RESERVE; } else if (cpu_is_omap54xx()) { omap_sram_start = OMAP4_SRAM_START_PA; omap_sram_size = OMAP5_SRAM_SIZE; /* 128KB */ omap_sram_size -= OMAP5_SRAM_GP_RESERVE; omap_sram_start += OMAP5_SRAM_GP_RESERVE; } else { omap_sram_start = OMAP2_SRAM_PA; if (cpu_is_omap242x()) omap_sram_size = 0xa0000; /* 640K */ else if (cpu_is_omap243x()) omap_sram_size = 0x10000; /* 64K */ } } } else { omap_sram_start = OMAP1_SRAM_PA; if (cpu_is_omap7xx()) omap_sram_size = 0x32000; /* 200K */ else if (cpu_is_omap15xx()) omap_sram_size = 0x30000; /* 192K */ else if (cpu_is_omap1610() || cpu_is_omap1611() || cpu_is_omap1621() || cpu_is_omap1710()) omap_sram_size = 0x4000; /* 16K */ else { pr_err("Could not detect SRAM size\n"); omap_sram_size = 0x4000; } } }
void __init omap2_init_common_infrastructure(void) { u8 postsetup_state; if (cpu_is_omap242x()) { omap2xxx_powerdomains_init(); omap2_clockdomains_init(); omap2420_hwmod_init(); } else if (cpu_is_omap243x()) { omap2xxx_powerdomains_init(); omap2_clockdomains_init(); omap2430_hwmod_init(); } else if (cpu_is_omap34xx()) { omap3xxx_powerdomains_init(); omap2_clockdomains_init(); omap3xxx_hwmod_init(); } else if (cpu_is_ti81xx()) { ti81xx_powerdomains_init(); omap2_clockdomains_init(); ti81xx_hwmod_init(); } else if (cpu_is_omap44xx()) { omap44xx_powerdomains_init(); omap44xx_clockdomains_init(); omap44xx_hwmod_init(); } else { pr_err("Could not init hwmod data - unknown SoC\n"); } /* Set the default postsetup state for all hwmods */ #ifdef CONFIG_PM_RUNTIME postsetup_state = _HWMOD_STATE_IDLE; #else postsetup_state = _HWMOD_STATE_ENABLED; #endif omap_hwmod_for_each(_set_hwmod_postsetup_state, &postsetup_state); /* * Set the default postsetup state for unusual modules (like * MPU WDT). * * The postsetup_state is not actually used until * omap_hwmod_late_init(), so boards that desire full watchdog * coverage of kernel initialization can reprogram the * postsetup_state between the calls to * omap2_init_common_infra() and omap2_init_common_devices(). * * XXX ideally we could detect whether the MPU WDT was currently * enabled here and make this conditional */ postsetup_state = _HWMOD_STATE_DISABLED; omap_hwmod_for_each_by_class("wd_timer", _set_hwmod_postsetup_state, &postsetup_state); omap_pm_if_early_init(); if (cpu_is_omap2420()) omap2420_clk_init(); else if (cpu_is_omap2430()) omap2430_clk_init(); else if (cpu_is_omap34xx()) omap3xxx_clk_init(); else if (cpu_is_ti816x()) ti816x_clk_init(); else if (cpu_is_ti814x()) ti814x_clk_init(); else if (cpu_is_omap44xx()) omap4xxx_clk_init(); else pr_err("Could not init clock framework - unknown SoC\n"); }