/* For SH7707, SH7709, SH7709A, SH7729, SH7300*/ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { unsigned int fcr_val = 0; #if !defined(CONFIG_CPU_SUBTYPE_SH7300) /* SH7300 doesn't use RTS/CTS */ { unsigned short data; /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ ctrl_outw(data&0x0fcf, SCPCR); } if (cflag & CRTSCTS) fcr_val |= SCFCR_MCE; else { unsigned short data; /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP4MD1,0, Set SCP6MD1,0 = {01} (output) */ ctrl_outw((data&0x0fcf)|0x1000, SCPCR); data = ctrl_inb(SCPDR); /* Set /RTS2 (bit6) = 0 */ ctrl_outb(data&0xbf, SCPDR); } #endif sci_out(port, SCFCR, fcr_val); }
/* * Initialize the board */ static void __init highlander_setup(char **cmdline_p) { u16 ver = ctrl_inw(PA_VERREG); int i; printk(KERN_INFO "Renesas Solutions Highlander %s support.\n", mach_is_r7780rp() ? "R7780RP-1" : mach_is_r7780mp() ? "R7780MP" : "R7785RP"); printk(KERN_INFO "Board version: %d (revision %d), " "FPGA version: %d (revision %d)\n", (ver >> 12) & 0xf, (ver >> 8) & 0xf, (ver >> 4) & 0xf, ver & 0xf); /* * Enable the important clocks right away.. */ for (i = 0; i < ARRAY_SIZE(r7780rp_clocks); i++) { struct clk *clk = r7780rp_clocks[i]; clk_register(clk); clk_enable(clk); } ctrl_outw(0x0000, PA_OBLED); /* Clear LED. */ if (mach_is_r7780rp()) ctrl_outw(0x0001, PA_SDPOW); /* SD Power ON */ ctrl_outw(ctrl_inw(PA_IVDRCTL) | 0x01, PA_IVDRCTL); /* Si13112 */ pm_power_off = r7780rp_power_off; }
static void sh7750_perf_counter_stop(void) { ctrl_outw(ctrl_inw(PMCR1) & ~PMCR_PMEN, PMCR1); ctrl_outw(ctrl_inw(PMCR2) & ~PMCR_PMEN, PMCR2); unregister_profile_notifier(&sh7750_timer_notifier); }
static int sh7750_perf_counter_start(void) { u16 pmcr; /* Enable counter 1 */ if (ctr[0].enabled) { pmcr = ctrl_inw(PMCR1); WARN_ON(pmcr & PMCR_PMEN); pmcr &= ~PMCR_PMM_MASK; pmcr |= ctr[0].event; ctrl_outw(pmcr | PMCR_ENABLE, PMCR1); } /* Enable counter 2 */ if (ctr[1].enabled) { pmcr = ctrl_inw(PMCR2); WARN_ON(pmcr & PMCR_PMEN); pmcr &= ~PMCR_PMM_MASK; pmcr |= ctr[1].event; ctrl_outw(pmcr | PMCR_ENABLE, PMCR2); } return register_profile_notifier(&sh7750_timer_notifier); }
static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { unsigned int fcr_val = 0; unsigned short data; if (cflag & CRTSCTS) { /* enable RTS/CTS */ if (port->mapbase == 0xa4430000) { /* SCIF0 */ /* Clear PTCR bit 9-2; enable all scif pins but sck */ data = ctrl_inw(PORT_PTCR); ctrl_outw((data & 0xfc03), PORT_PTCR); } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ /* Clear PVCR bit 9-2 */ data = ctrl_inw(PORT_PVCR); ctrl_outw((data & 0xfc03), PORT_PVCR); } fcr_val |= SCFCR_MCE; } else { if (port->mapbase == 0xa4430000) { /* SCIF0 */ /* Clear PTCR bit 5-2; enable only tx and rx */ data = ctrl_inw(PORT_PTCR); ctrl_outw((data & 0xffc3), PORT_PTCR); } else if (port->mapbase == 0xa4438000) { /* SCIF1 */ /* Clear PVCR bit 5-2 */ data = ctrl_inw(PORT_PVCR); ctrl_outw((data & 0xffc3), PORT_PVCR); } } sci_out(port, SCFCR, fcr_val); }
static void __init migor_setup(char **cmdline_p) { /* SMC91C111 - Enable IRQ0 */ ctrl_outw(ctrl_inw(PORT_PJCR) & ~0x0003, PORT_PJCR); /* KEYSC */ ctrl_outw(ctrl_inw(PORT_PYCR) & ~0x0fff, PORT_PYCR); ctrl_outw(ctrl_inw(PORT_PZCR) & ~0x0ff0, PORT_PZCR); ctrl_outw(ctrl_inw(PORT_PSELA) & ~0x4100, PORT_PSELA); ctrl_outw(ctrl_inw(PORT_HIZCRA) & ~0x4000, PORT_HIZCRA); ctrl_outw(ctrl_inw(PORT_HIZCRC) & ~0xc000, PORT_HIZCRC); ctrl_outl(ctrl_inl(MSTPCR2) & ~0x00004000, MSTPCR2); /* NAND Flash */ ctrl_outw(ctrl_inw(PORT_PXCR) & 0x0fff, PORT_PXCR); ctrl_outl((ctrl_inl(BSC_CS6ABCR) & ~0x00000600) | 0x00000200, BSC_CS6ABCR); /* I2C */ ctrl_outl(ctrl_inl(MSTPCR1) & ~0x00000200, MSTPCR1); /* Touch Panel - Enable IRQ6 */ ctrl_outw(ctrl_inw(PORT_PZCR) & ~0xc, PORT_PZCR); ctrl_outw((ctrl_inw(PORT_PSELA) | 0x8000), PORT_PSELA); ctrl_outw((ctrl_inw(PORT_HIZCRC) & ~0x4000), PORT_HIZCRC); }
/* * Initialize IRQ setting */ void __init init_se7722_IRQ(void) { int i, irq; ctrl_outw(0, IRQ01_MASK); /* disable all irqs */ ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */ for (i = 0; i < SE7722_FPGA_IRQ_NR; i++) { irq = create_irq(); if (irq < 0) return; se7722_fpga_irq[i] = irq; set_irq_chip_and_handler_name(se7722_fpga_irq[i], &se7722_irq_chip, handle_level_irq, "level"); set_irq_chip_data(se7722_fpga_irq[i], (void *)i); } set_irq_chained_handler(IRQ0_IRQ, se7722_irq_demux); set_irq_type(IRQ0_IRQ, IRQ_TYPE_LEVEL_LOW); set_irq_chained_handler(IRQ1_IRQ, se7722_irq_demux); set_irq_type(IRQ1_IRQ, IRQ_TYPE_LEVEL_LOW); }
/* For SH7707, SH7709, SH7709A, SH7729 */ static void sci_init_pins_scif(struct sci_port* port, unsigned int cflag) { unsigned int fcr_val = 0; { unsigned short data; /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP6MD1,0, SCP4MD1,0*/ ctrl_outw(data&0x0fcf, SCPCR); } if (cflag & CRTSCTS) fcr_val |= SCFCR_MCE; else { unsigned short data; /* We need to set SCPCR to enable RTS/CTS */ data = ctrl_inw(SCPCR); /* Clear out SCP7MD1,0, SCP4MD1,0, Set SCP6MD1,0 = {01} (output) */ ctrl_outw((data&0x0fcf)|0x1000, SCPCR); data = ctrl_inb(SCPDR); /* Set /RTS2 (bit6) = 0 */ ctrl_outb(data&0xbf, SCPDR); } sci_out(port, SCFCR, fcr_val); }
/* * Initialize IRQ setting */ void __init init_hs7751rvoip_IRQ(void) { int i; /* IRL0=ON HOOK1 * IRL1=OFF HOOK1 * IRL2=ON HOOK2 * IRL3=OFF HOOK2 * IRL4=Ringing Detection * IRL5=CODEC * IRL6=Ethernet * IRL7=Ethernet Hub * IRL8=USB Communication * IRL9=USB Connection * IRL10=USB DMA * IRL11=CF Card * IRL12=PCMCIA * IRL13=PCI Slot */ ctrl_outw(0x9876, IRLCNTR1); ctrl_outw(0xdcba, IRLCNTR2); ctrl_outw(0x0050, IRLCNTR4); ctrl_outw(0x4321, IRLCNTR5); for (i=0; i<14; i++) make_hs7751rvoip_irq(i); }
static void __init se7721_setup(char **cmdline_p) { /* for USB */ ctrl_outw(0x0000, 0xA405010C); /* PGCR */ ctrl_outw(0x0000, 0xA405010E); /* PHCR */ ctrl_outw(0x00AA, 0xA4050118); /* PPCR */ ctrl_outw(0x0000, 0xA4050124); /* PSELA */ }
void landisk_outw(u16 value, unsigned long port) { if (PXSEG(port)) ctrl_outw(value, port); else if (is_pci_ioaddr(port)) ctrl_outw(value, pci_ioaddr(port)); else maybebadio(port); }
void __init init_shmse_IRQ(void) { ctrl_outw(0x0028, 0xb0a00000); // mode set [active low]. ctrl_outw(0x000a, INTC_ICR1); // IRQ mode; IRQ0,1 enable. /* PC_IRQ[0-3] -> IRQ0 (32) */ make_ipr_irq( IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f-IRQ0_IRQ); /* A_IRQ[0-3] -> IRQ1 (33) */ make_ipr_irq( IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f-IRQ1_IRQ); }
void hs7751rvoip_outw(unsigned short value, unsigned long port) { if (PXSEG(port)) ctrl_outw(value, port); else if (is_pci_ioaddr(port) || shifted_port(port)) ctrl_outw(value, pci_ioaddr(port)); else maybebadio(port); }
void titan_outw(u16 value, unsigned long port) { if (PXSEG(port)) ctrl_outw(value, port); else if (port >= 0x2000) ctrl_outw(value, port2adr(port)); else maybebadio(port); }
static void ap320_wvga_power_off(void *board_data) { /* backlight */ ctrl_outw(0, FPGA_BKLREG); gpio_set_value(GPIO_PTS3, 1); /* ASD AP-320/325 LCD OFF */ ctrl_outw(0, FPGA_LCDREG); }
static void ap320_wvga_power_on(void *board_data) { msleep(100); /* ASD AP-320/325 LCD ON */ ctrl_outw(FPGA_LCDREG_VAL, FPGA_LCDREG); /* backlight */ gpio_set_value(GPIO_PTS3, 0); ctrl_outw(0x100, FPGA_BKLREG); }
void titan_outb(u8 value, unsigned long port) { if (PXSEG(port)) ctrl_outb(value, port); else ctrl_outw(value, port2adr(port)); }
static void disable_ipr_irq(unsigned int irq) { struct ipr_data *p = get_irq_chip_data(irq); unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; /* Set the priority in IPR to 0 */ ctrl_outw(ctrl_inw(addr) & (0xffff ^ (0xf << p->shift)), addr); }
static void enable_ipr_irq(unsigned int irq) { struct ipr_data *p = get_irq_chip_data(irq); unsigned long addr = get_ipr_desc(irq)->ipr_offsets[p->ipr_idx]; /* Set priority in IPR back to original value */ ctrl_outw(ctrl_inw(addr) | (p->priority << p->shift), addr); }
static int camera_power(struct device *dev, int mode) { int ret; if (mode) { long rate; camera_clk = clk_get(NULL, "video_clk"); if (IS_ERR(camera_clk)) return PTR_ERR(camera_clk); rate = clk_round_rate(camera_clk, CEU_MCLK_FREQ); ret = clk_set_rate(camera_clk, rate); if (ret < 0) goto eclkrate; /* set DRVCRB * * use 1.8 V for VccQ_VIO * use 2.85V for VccQ_SR */ ctrl_outw((ctrl_inw(DRVCRB) & ~0x0003) | 0x0001, DRVCRB); /* reset clear */ ret = gpio_request(GPIO_PTB4, NULL); if (ret < 0) goto eptb4; ret = gpio_request(GPIO_PTB7, NULL); if (ret < 0) goto eptb7; ret = gpio_direction_output(GPIO_PTB4, 1); if (!ret) ret = gpio_direction_output(GPIO_PTB7, 1); if (ret < 0) goto egpioout; msleep(1); ret = clk_enable(camera_clk); /* start VIO_CKO */ if (ret < 0) goto eclkon; return 0; } ret = 0; clk_disable(camera_clk); eclkon: gpio_set_value(GPIO_PTB7, 0); egpioout: gpio_set_value(GPIO_PTB4, 0); gpio_free(GPIO_PTB7); eptb7: gpio_free(GPIO_PTB4); eptb4: eclkrate: clk_put(camera_clk); return ret; }
static int exm7760_i2s_init(void) { int ret; unsigned short ipsel; printk(KERN_INFO "EXM32 Motherboard I2S Audio support\n"); /* switch PFC to I2S on both audio paths */ ipsel = ctrl_inw(IPSEL); ipsel &= ~(3<<10); ctrl_outw(ipsel, IPSEL); ret = -ENOMEM; exm7760_i2s_snd_device = platform_device_alloc("soc-audio", -1); if (!exm7760_i2s_snd_device) goto out; platform_set_drvdata(exm7760_i2s_snd_device, &exm7760_i2s_snd_devdata); exm7760_i2s_snd_devdata.dev = &exm7760_i2s_snd_device->dev; ret = platform_device_add(exm7760_i2s_snd_device); if (ret) platform_device_put(exm7760_i2s_snd_device); out: MSG("module_init() exit (ret %d)\n", ret); return ret; }
static int __init sh7760_ac97_init(void) { int ret; unsigned short ipsel; /* enable both AC97 controllers in pinmux reg */ ipsel = ctrl_inw(IPSEL); ctrl_outw(ipsel | (3 << 10), IPSEL); ret = -ENOMEM; sh7760_ac97_snd_device = platform_device_alloc("soc-audio", -1); if (!sh7760_ac97_snd_device) goto out; platform_set_drvdata(sh7760_ac97_snd_device, &sh7760_ac97_snd_devdata); sh7760_ac97_snd_devdata.dev = &sh7760_ac97_snd_device->dev; ret = platform_device_add(sh7760_ac97_snd_device); if (ret) platform_device_put(sh7760_ac97_snd_device); out: return ret; }
static irqreturn_t psw_irq_handler(int irq, void *arg) { struct platform_device *pdev = arg; struct push_switch *psw = platform_get_drvdata(pdev); struct push_switch_platform_info *psw_info = pdev->dev.platform_data; unsigned int l, mask; int ret = 0; l = ctrl_inw(PA_DBSW); /* Nothing to do if there's no state change */ if (psw->state) { ret = 1; goto out; } mask = l & 0x70; /* Figure out who raised it */ if (mask & (1 << psw_info->bit)) { psw->state = !!(mask & (1 << psw_info->bit)); if (psw->state) /* debounce */ mod_timer(&psw->debounce, jiffies + 50); ret = 1; } out: /* Clear the switch IRQs */ l |= (0x7 << 12); ctrl_outw(l, PA_DBSW); return IRQ_RETVAL(ret); }
static void setup_fast_timer() { unsigned long interval; #ifdef FAST_POLL_INTR interval = (current_cpu_data.module_clock/4 + FAST_POLL/2) / FAST_POLL; make_ipr_irq(FASTTIMER_IRQ, FASTTIMER_IPR_ADDR, FASTTIMER_IPR_POS, FASTTIMER_PRIORITY); printk("SnapGear: %dHz fast timer on IRQ %d\n",FAST_POLL,FASTTIMER_IRQ); if (request_irq(FASTTIMER_IRQ, fast_timer_irq, 0, "SnapGear fast timer", NULL) != 0) printk("%s(%d): request_irq() failed?\n", __FILE__, __LINE__); #else printk("SnapGear: fast timer running\n",FAST_POLL,FASTTIMER_IRQ); interval = 0xffffffff; #endif ctrl_outb(ctrl_inb(TMU_TSTR) & ~0x2, TMU_TSTR); /* disable timer 1 */ ctrl_outw(TMU1_TCR_INIT, TMU1_TCR); ctrl_outl(interval, TMU1_TCOR); ctrl_outl(interval, TMU1_TCNT); ctrl_outb(ctrl_inb(TMU_TSTR) | 0x2, TMU_TSTR); /* enable timer 1 */ printk("Timer count 1 = 0x%x\n", fast_timer_count()); udelay(1000); printk("Timer count 2 = 0x%x\n", fast_timer_count()); }
/* * Initialize the board */ static void __init rts7751r2d_setup(char **cmdline_p) { void __iomem *sm501_reg; u16 ver = ctrl_inw(PA_VERREG); printk(KERN_INFO "Renesas Technology Sales RTS7751R2D support.\n"); printk(KERN_INFO "FPGA version:%d (revision:%d)\n", (ver >> 4) & 0xf, ver & 0xf); ctrl_outw(0x0000, PA_OUTPORT); pm_power_off = rts7751r2d_power_off; /* sm501 dram configuration: * ColSizeX = 11 - External Memory Column Size: 256 words. * APX = 1 - External Memory Active to Pre-Charge Delay: 7 clocks. * RstX = 1 - External Memory Reset: Normal. * Rfsh = 1 - Local Memory Refresh to Command Delay: 12 clocks. * BwC = 1 - Local Memory Block Write Cycle Time: 2 clocks. * BwP = 1 - Local Memory Block Write to Pre-Charge Delay: 1 clock. * AP = 1 - Internal Memory Active to Pre-Charge Delay: 7 clocks. * Rst = 1 - Internal Memory Reset: Normal. * RA = 1 - Internal Memory Remain in Active State: Do not remain. */ sm501_reg = (void __iomem *)0xb3e00000 + SM501_DRAM_CONTROL; writel(readl(sm501_reg) | 0x00f107c0, sm501_reg); }
static void fast_timer_irq(int irq, void *dev_instance, struct pt_regs *regs) { unsigned long timer_status; timer_status = ctrl_inw(TMU1_TCR); timer_status &= ~0x100; ctrl_outw(timer_status, TMU1_TCR); }
/* * Initialize IRQ setting */ void __init init_se7721_IRQ(void) { /* PPCR */ ctrl_outw(ctrl_inw(0xa4050118) & ~0x00ff, 0xa4050118); register_intc_controller(&intc_desc); intc_set_priority(MRSHPC_IRQ0, 0xf - MRSHPC_IRQ0); }
int __init oprofile_arch_init(struct oprofile_operations **ops) { if (!(current_cpu_data.flags & CPU_HAS_PERF_COUNTER)) return -ENODEV; sh7750_perf_counter_ops.cpu_type = (char *)get_cpu_subtype(); *ops = &sh7750_perf_counter_ops; printk(KERN_INFO "oprofile: using SH-4 (%s) performance monitoring.\n", sh7750_perf_counter_ops.cpu_type); /* Clear the counters */ ctrl_outw(ctrl_inw(PMCR1) | PMCR_PMCLR, PMCR1); ctrl_outw(ctrl_inw(PMCR2) | PMCR_PMCLR, PMCR2); return 0; }
/* For SH7750 */ static void sci_init_pins_scif(struct uart_port *port, unsigned int cflag) { unsigned int fcr_val = 0; if (cflag & CRTSCTS) { fcr_val |= SCFCR_MCE; } else { #ifdef CONFIG_CPU_SUBTYPE_SH7343 /* Nothing */ #elif defined(CONFIG_CPU_SUBTYPE_SH7780) ctrl_outw(0x0080, SCSPTR0); /* Set RTS = 1 */ #else ctrl_outw(0x0080, SCSPTR2); /* Set RTS = 1 */ #endif } sci_out(port, SCFCR, fcr_val); }
static void cmt_clk_init(struct clk *clk) { u8 divisor = CMT_CMCSR_INIT & 0x3; ctrl_inw(CMT_CMCSR_0); ctrl_outw(CMT_CMCSR_INIT, CMT_CMCSR_0); clk->parent = clk_get(NULL, "module_clk"); clk->rate = clk->parent->rate / (8 << (divisor << 1)); }