void hang (void)
{
disable_interrupts ();
puts("### ERROR ### Please reset board ###\n");
for (;;);
}
int flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile ulong addr = info->start[0];
int flag, prot, sect, l_sect;
ulong start, now, last;
flash_to_xd();
if (s_first < 0 || s_first > s_last) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
flash_to_mem();
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
flash_to_mem();
return 1;
}
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
out8(addr + 0x555, 0x80);
iobarrier_rw();
out8(addr + 0x555, 0xAA);
iobarrier_rw();
out8(addr + 0x2AA, 0x55);
iobarrier_rw();
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = info->start[sect];
out8(addr, 0x30);
iobarrier_rw();
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = info->start[l_sect];
DEBUGF ("Start erase timeout: %d\n", CONFIG_SYS_FLASH_ERASE_TOUT);
while ((in8(addr) & 0x80) != 0x80) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
flash_reset (info->start[0]);
flash_to_mem();
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
iobarrier_rw();
}
DONE:
/* reset to read mode */
flash_reset (info->start[0]);
flash_to_mem();
printf (" done\n");
return 0;
}
int cpu_post_test_twox (void)
{
int ret = 0;
unsigned int i, reg;
int flag = disable_interrupts();
for (i = 0; i < cpu_post_twox_size && ret == 0; i++)
{
struct cpu_post_twox_s *test = cpu_post_twox_table + i;
for (reg = 0; reg < 32 && ret == 0; reg++)
{
unsigned int reg0 = (reg + 0) % 32;
unsigned int reg1 = (reg + 1) % 32;
unsigned int stk = reg < 16 ? 31 : 15;
unsigned long code[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
ASM_STW(3, stk, 8),
ASM_STW(reg0, stk, 4),
ASM_STW(reg1, stk, 0),
ASM_LWZ(reg0, stk, 8),
ASM_11X(test->cmd, reg1, reg0),
ASM_STW(reg1, stk, 8),
ASM_LWZ(reg1, stk, 0),
ASM_LWZ(reg0, stk, 4),
ASM_LWZ(3, stk, 8),
ASM_ADDI(1, stk, 16),
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
unsigned long codecr[] =
{
ASM_STW(stk, 1, -4),
ASM_ADDI(stk, 1, -16),
ASM_STW(3, stk, 8),
ASM_STW(reg0, stk, 4),
ASM_STW(reg1, stk, 0),
ASM_LWZ(reg0, stk, 8),
ASM_11X(test->cmd, reg1, reg0) | BIT_C,
ASM_STW(reg1, stk, 8),
ASM_LWZ(reg1, stk, 0),
ASM_LWZ(reg0, stk, 4),
ASM_LWZ(3, stk, 8),
ASM_ADDI(1, stk, 16),
ASM_LWZ(stk, 1, -4),
ASM_BLR,
};
ulong res;
ulong cr;
if (ret == 0)
{
cr = 0;
cpu_post_exec_21 (code, & cr, & res, test->op);
ret = res == test->res && cr == 0 ? 0 : -1;
if (ret != 0)
{
post_log ("Error at twox test %d !\n", i);
}
}
if (ret == 0)
{
cpu_post_exec_21 (codecr, & cr, & res, test->op);
ret = res == test->res &&
(cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1;
if (ret != 0)
{
post_log ("Error at twox test %d !\n", i);
}
}
}
}
if (flag)
enable_interrupts();
return ret;
}
/*
* void cpu_reboot(int howto, char *bootstr)
*
* Reboots the system
*
* Deal with any syncing, unmounting, dumping and shutdown hooks,
* then reset the CPU.
*/
void
cpu_reboot(int howto, char *bootstr)
{
u_int32_t reg;
#ifdef DIAGNOSTIC
/* info */
printf("boot: howto=%08x curproc=%p\n", howto, curproc);
#endif
/*
* If we are still cold then hit the air brakes
* and crash to earth fast
*/
if (cold) {
doshutdownhooks();
printf("The operating system has halted.\n");
printf("Please press any key to reboot.\n\n");
cngetc();
printf("rebooting...\n");
goto reset;
}
/* Disable console buffering */
/*
* If RB_NOSYNC was not specified sync the discs.
* Note: Unless cold is set to 1 here, syslogd will die during the
* unmount. It looks like syslogd is getting woken up only to find
* that it cannot page part of the binary in as the filesystem has
* been unmounted.
*/
if (!(howto & RB_NOSYNC))
bootsync();
/* Say NO to interrupts */
splhigh();
/* Do a dump if requested. */
if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
dumpsys();
/* Run any shutdown hooks */
doshutdownhooks();
/* Make sure IRQ's are disabled */
IRQdisable;
if (howto & RB_HALT) {
printf("The operating system has halted.\n");
printf("Please press any key to reboot.\n\n");
cngetc();
}
printf("rebooting...\n\r");
reset:
/*
* Make really really sure that all interrupts are disabled,
*/
(void) disable_interrupts(I32_bit|F32_bit);
IXPREG(IXP425_INT_ENABLE) = 0;
/*
* Map the boot Flash device down at physical address 0.
* This is safe since NetBSD runs out of an alias of
* SDRAM at 0x10000000.
*/
reg = EXP_CSR_READ_4(ixpsip_softc, EXP_CNFG0_OFFSET);
reg |= EXP_CNFG0_MEM_MAP;
EXP_CSR_WRITE_4(ixpsip_softc, EXP_CNFG0_OFFSET, reg);
/*
* Jump into the bootcode's reset vector
*
* XXX:
* Redboot doesn't like the state in which we leave the PCI
* ethernet card, and so fails to detect it on reboot. This
* pretty much necessitates a hard reset/power cycle to be
* able to download a new kernel image over ethernet.
*
* I suspect this is due to a bug in Redboot's i82557 driver.
*/
cpu_reset();
/* ...and if that didn't work, just croak. */
printf("RESET FAILED!\n");
for (;;);
}
int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
ulong iflag;
ulong load_end = 0;
int ret;
boot_os_fn *boot_fn;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
static int relocated = 0;
/* relocate boot function table */
if (!relocated) {
int i;
for (i = 0; i < ARRAY_SIZE(boot_os); i++)
if (boot_os[i] != NULL)
boot_os[i] += gd->reloc_off;
relocated = 1;
}
#endif
/* determine if we have a sub command */
if (argc > 1) {
char *endp;
simple_strtoul(argv[1], &endp, 16);
/* endp pointing to NULL means that argv[1] was just a
* valid number, pass it along to the normal bootm processing
*
* If endp is ':' or '#' assume a FIT identifier so pass
* along for normal processing.
*
* Right now we assume the first arg should never be '-'
*/
if ((*endp != 0) && (*endp != ':') && (*endp != '#'))
return do_bootm_subcommand(cmdtp, flag, argc, argv);
}
if (bootm_start(cmdtp, flag, argc, argv))
return 1;
/*
* We have reached the point of no return: we are going to
* overwrite all exception vector code, so we cannot easily
* recover from any failures any more...
*/
iflag = disable_interrupts();
#if defined(CONFIG_CMD_USB)
/*
* turn off USB to prevent the host controller from writing to the
* SDRAM while Linux is booting. This could happen (at least for OHCI
* controller), because the HCCA (Host Controller Communication Area)
* lies within the SDRAM and the host controller writes continously to
* this area (as busmaster!). The HccaFrameNumber is for example
* updated every 1 ms within the HCCA structure in SDRAM! For more
* details see the OpenHCI specification.
*/
usb_stop();
#endif
ret = bootm_load_os(images.os, &load_end, 1);
if (ret < 0) {
if (ret == BOOTM_ERR_RESET)
do_reset(cmdtp, flag, argc, argv);
if (ret == BOOTM_ERR_OVERLAP) {
if (images.legacy_hdr_valid) {
image_header_t *hdr;
hdr = &images.legacy_hdr_os_copy;
if (image_get_type(hdr) == IH_TYPE_MULTI)
puts("WARNING: legacy format multi "
"component image "
"overwritten\n");
} else {
puts("ERROR: new format image overwritten - "
"must RESET the board to recover\n");
bootstage_error(BOOTSTAGE_ID_OVERWRITTEN);
do_reset(cmdtp, flag, argc, argv);
}
}
if (ret == BOOTM_ERR_UNIMPLEMENTED) {
if (iflag)
enable_interrupts();
bootstage_error(BOOTSTAGE_ID_DECOMP_UNIMPL);
return 1;
}
}
lmb_reserve(&images.lmb, images.os.load, (load_end - images.os.load));
if (images.os.type == IH_TYPE_STANDALONE) {
if (iflag)
enable_interrupts();
/* This may return when 'autostart' is 'no' */
bootm_start_standalone(iflag, argc, argv);
return 0;
}
bootstage_mark(BOOTSTAGE_ID_CHECK_BOOT_OS);
#ifdef CONFIG_SILENT_CONSOLE
if (images.os.os == IH_OS_LINUX)
fixup_silent_linux();
#endif
boot_fn = boot_os[images.os.os];
if (boot_fn == NULL) {
if (iflag)
enable_interrupts();
printf("ERROR: booting os '%s' (%d) is not supported\n",
genimg_get_os_name(images.os.os), images.os.os);
bootstage_error(BOOTSTAGE_ID_CHECK_BOOT_OS);
return 1;
}
arch_preboot_os();
boot_fn(0, argc, argv, &images);
bootstage_error(BOOTSTAGE_ID_BOOT_OS_RETURNED);
#ifdef DEBUG
puts("\n## Control returned to monitor - resetting...\n");
#endif
do_reset(cmdtp, flag, argc, argv);
return 1;
}
void disable_interrupts_int_serial(void) {
disable_interrupts();
}
int cpu_post_test_b (void)
{
int ret = 0;
unsigned int i;
int flag = disable_interrupts();
if (ret == 0)
{
ulong code[] =
{
ASM_MFLR(4),
ASM_MTLR(3),
ASM_B(4),
ASM_MFLR(3),
ASM_MTLR(4),
ASM_BLR,
};
ulong res;
cpu_post_exec_11 (code, &res, 0);
ret = res == 0 ? 0 : -1;
if (ret != 0)
{
post_log ("Error at b1 test !\n");
}
}
if (ret == 0)
{
ulong code[] =
{
ASM_MFLR(4),
ASM_MTLR(3),
ASM_BL(4),
ASM_MFLR(3),
ASM_MTLR(4),
ASM_BLR,
};
ulong res;
cpu_post_exec_11 (code, &res, 0);
ret = res == (ulong)code + 12 ? 0 : -1;
if (ret != 0)
{
post_log ("Error at b2 test !\n");
}
}
if (ret == 0)
{
ulong cc, cd;
int cond;
ulong ctr;
int link;
i = 0;
for (cc = 0; cc < 4 && ret == 0; cc++)
{
for (cd = 0; cd < 4 && ret == 0; cd++)
{
for (link = 0; link <= 1 && ret == 0; link++)
{
for (cond = 0; cond <= 1 && ret == 0; cond++)
{
for (ctr = 1; ctr <= 2 && ret == 0; ctr++)
{
int decr = cd < 2;
int cr = cond ? 0x80000000 : 0x00000000;
int jumpc = cc >= 2 ||
(cc == 0 && !cond) ||
(cc == 1 && cond);
int jumpd = cd >= 2 ||
(cd == 0 && ctr != 1) ||
(cd == 1 && ctr == 1);
int jump = jumpc && jumpd;
ret = cpu_post_test_bc (link ? OP_BCL : OP_BC,
(cc << 3) + (cd << 1), 0, jump, decr, link,
ctr, cr);
if (ret != 0)
{
post_log ("Error at b3 test %d !\n", i);
}
i++;
}
}
}
}
}
}
if (flag)
enable_interrupts();
return ret;
}
void main(void)
{
UINT8 i = 0;
UINT8 a = 0;
INT8 s6 = 0;
INT8 c6 = 0;
INT8 dd = 0;
disable_interrupts();
cpu_fast();// GBC
enable_interrupts();
mode(M_DRAWING);
color(3, 0, SOLID);
set_bkg_palette(0, 1, palette);
plot_heart(12, 30);
plot_heart(22, 26);
for (i = 0; i != 8; i++)
{
pixels[i].x = HX;
pixels[i].y = HY;
}
while (1)
{
INT8 xmin = pixels[0].x;
INT8 xmax = pixels[0].x;
INT8 ymin = pixels[0].y;
INT8 ymax = pixels[0].y;
// calc min-max of last drawn cube
for (i = 1; i != 8; i++)
{
pixel_t * p = pixels + i;
if (xmin > p->x)
xmin = p->x;
else if (xmax < p->x)
xmax = p->x;
if (ymin < p->y)
ymin = p->y;
else if (ymax > p->y)
ymax = p->y;
}
// step
s6 = sin6[a];
c6 = cos6[a];
dd = s6 + s6;
a += 3;
// transform and project
for (i = 0; i != 8; i++)
{
vertex_t * v = vertices + i;
pixel_t * p = pixels + i;
INT8 x = (v->x * c6) + (v->z * s6) + dd;
INT8 y = (v->y * 31) + dd;
INT8 z = (v->z * c6) - (v->x * s6);
/* rotates in z
INT8 x = (v->x * c6) - (v->y * s6);
INT8 y = (v->y * c6) + (v->x * s6);
INT8 z = (v->z * 31);
*/
UINT16 dx = x < 0 ? -x : x;
UINT16 dy = y < 0 ? -y : y;
UINT16 dz = 128 - z;
dx = (dx << 5) / dz;
dy = (dy << 5) / dz;
p->x = HX + (x < 0 ? -dx : dx);
p->y = HY + (y < 0 ? -dy : dy);
}
// sync
//wait_vbl_done();
// draw wireframe
color(WHITE, WHITE, SOLID);
box(xmin - 1, ymin + 1, xmax + 1, ymax - 1, M_FILL);
color(1, 0, SOLID);
for (i = 0; i != 12; i++)
{
edge_t * edge = edges + i;
pixel_t * p0 = pixels + edge->i;
pixel_t * p1 = pixels + edge->j;
if (p0->x > p1->x)
line(p1->x, p1->y, p0->x, p0->y);
else
line(p0->x, p0->y, p1->x, p1->y);
}
}
}
/**
* Hauptfunktion. Wird als erstes aufgerufen.
* Struktogramm:
* <img src="../../Spielablauf_Struktogramm.png">
* @return gibt 0 zurück
*/
int main()
{
init_graphics(); //Function um Grafik Lib zu initialisieren, gibt evtl später mal Errorcode zurück...
init_counter();
/**
* \todo UART Interrupts funktionieren noch nicht.
* Als Workaround wird nun alle 1ms im Timer-Interrupt-Handler die UART1 Schnittstelle gepollt. <br>
*/
init_uart();
init_genrand(GUI_GetTime());
while(1)
{
init_game();
init_level();
// warten bis eine taste gedrückt wird, welche den initialen Zustand von snake_direction ändert
snake_direction = '?';
while(snake_direction == '?');
// jetzt food zeichnen
food = randomize_food();
draw_food(food);
enable_interrupts();
do
{
switch(step_forward(check_initial_state()))
{
case COLLISION:
game_over = 1;
disable_interrupts();
//write_byte(score);
FFLCR &= ~(1<<7); // DLAB löschen für zugriff
while (!(FFLSR & (1<<5))); // Solange UART Busy
FFTHR = score;
enable_interrupts();
break;
case FOOD:
score++;
if(size >= 15)
{
// wenn Länge = 15: Level-Up
score += 10;
level++;
init_level();
}
food = randomize_food();
disable_interrupts();
draw_food(food);
enable_interrupts();
break;
case NOTHING:
break;
}
delay(delay_time);
}
while(game_over != 1);
}
return 0;
}
/*
* void cpu_reboot(int howto, char *bootstr)
*
* Reboots the system
*
* Deal with any syncing, unmounting, dumping and shutdown hooks,
* then reset the CPU.
*/
void
cpu_reboot(int howto, char *bootstr)
{
/*
* If we are still cold then hit the air brakes
* and crash to earth fast
*/
if (cold) {
*(volatile uint8_t *)HDLG_LEDCTRL |= LEDCTRL_STAT_RED;
howto |= RB_HALT;
goto haltsys;
}
/* Disable console buffering */
/*
* If RB_NOSYNC was not specified sync the discs.
* Note: Unless cold is set to 1 here, syslogd will die during the
* unmount. It looks like syslogd is getting woken up only to find
* that it cannot page part of the binary in as the filesystem has
* been unmounted.
*/
if ((howto & RB_NOSYNC) == 0) {
bootsync();
/*resettodr();*/
}
/* wait 1s */
delay(1 * 1000 * 1000);
/* Say NO to interrupts */
splhigh();
/* Do a dump if requested. */
if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP) {
dumpsys();
}
haltsys:
/* Run any shutdown hooks */
doshutdownhooks();
/* Make sure IRQ's are disabled */
IRQdisable;
if (howto & RB_HALT) {
*(volatile uint8_t *)HDLG_PWRMNG = PWRMNG_POWOFF;
delay(3 * 1000 * 1000); /* wait 3s */
printf("SHUTDOWN FAILED!\n");
printf("The operating system has halted.\n");
printf("Please press any key to reboot.\n\n");
cngetc();
}
printf("rebooting...\n\r");
(void)disable_interrupts(I32_bit|F32_bit);
cpu_idcache_wbinv_all();
cpu_drain_writebuf();
*(volatile uint8_t *)HDLG_PWRMNG = PWRMNG_RESET;
delay(1 * 1000 * 1000); /* wait 1s */
/* ...and if that didn't work, just croak. */
printf("RESET FAILED!\n");
for (;;) {
continue;
}
}
void main()
{
mydevices.numberOfInputs=0;
mydevices.numberOfOutputs=0;
clock = 0;
ledErrorCounter=0;
hw_setup();
//TODO: User Code
//struct switches array[NUMBER_OF_SWITCHES];
/*
button_test();
dimmer_test();
*/
///////////////SALA//////////////////////////////
/* eeprom_on_off_init(20,21,6);//2 int Grande a comecar da esquerda
eeprom_on_off_init(22,23,0);//2
//eeprom_dimmer_init(40,41,42,7);//2
eeprom_on_off_init(41,42,7);//2
eeprom_on_off_init(26,27,3);//2
///Sanca parede grande
unsigned int on_adr[8]={20,255,255,255,255,255,255,255};
unsigned int off_adr[8]={21,255,255,255,255,255,255,255};
eeprom_onOff_out_init(on_adr,off_adr,3);//Sanca parede grande
eeprom_onOff_out_init(on_adr,off_adr,5);//Sanca parede grande
///Sanca parede rosa
unsigned int on_adrr[8]={22,255,255,255,255,255,255,255};
unsigned int off_adrr[8]={23,255,255,255,255,255,255,255};
eeprom_onOff_out_init(on_adrr,off_adrr,7);//Sanca parede grande
on_adrr[1]=26;
off_adrr[1]=27;
eeprom_onOff_out_init(on_adrr,off_adrr,4);//Sanca parede grande
///VARANDA
unsigned int dimmer_dim_adr[8]={40,255,255,255,255,255,255,255};
unsigned int dimmer_on_adr[8]={41,255,255,255,255,255,255,255};
unsigned int dimmer_off_adr[8]={42,255,255,255,255,255,255,255};
//eeprom_dimmer_out_init(dimmer_dim_adr,dimmer_on_adr,dimmer_off_adr,6);//varanda
eeprom_onOff_out_init(dimmer_on_adr,dimmer_off_adr,6);//varanda
eeprom_button_init(28,29,4,true);//estores down
eeprom_button_init(30,31,5,true);//estores up
unsigned int up_adr[8]={30,255,255,255,255,255,255,255};
unsigned int down_adr[8]={28,255,255,255,255,255,255,255};
unsigned int x_adr[8]={255,255,255,255,255,255,255,255};
eeprom_shutter_out_init(up_adr,down_adr,x_adr,x_adr,8,9,0,10);
eeprom_shutter_out_init(up_adr,down_adr,x_adr,x_adr,10,11,0,10);
eeprom_shutter_out_init(up_adr,down_adr,x_adr,x_adr,12,13,0,10);
eeprom_shutter_out_init(up_adr,down_adr,x_adr,x_adr,14,15,0,10);
*/
/////////////////////////////////////////////////7
/*
///////////////QUARTO GRANDE//////////////////////////////
eeprom_on_off_init(1,2,2);//2 on_adr off_adr real_button inicia botao
unsigned int on_adr[8]={1,255,255,255,255,255,255,255};
unsigned int off_adr[8]={2,10,255,255,255,255,255,255};
unsigned int nill_adr[8]={255,255,255,255,255,255,255,255};
unsigned int ventax_off_adr[8]={16,255,255,255,255,255,255,255};
unsigned int x_adr[8]={1,255,255,255,255,255,255,255};
eeprom_onOff_out_init(on_adr,off_adr,4);//SANCA?
//outputs 4=sanca 3=casabanho 2=casa de banho 9=ventax 1=corredor
///casa de banho
eeprom_on_off_init(3,4,4);//interruptor casa de banho??
off_adr[0]=4;
on_adr[0]=3;
eeprom_timer_init(off_adr,on_adr,15,16,time_off,60);
eeprom_onOff_out_init(on_adr,off_adr,3); //luz casa de banho
eeprom_onOff_out_init(on_adr,off_adr,2); //luz2 casa de banho
eeprom_onOff_out_init(on_adr,ventax_off_adr,9);//VENTAX
///fim casa de banho
//corredor
eeprom_on_off_init(17,18,5);//interruptor luz corredor
unsigned int corredor_on_adr[8]={17,255,255,255,255,255,255,255};
unsigned int corredor_off_adr[8]={18,255,255,255,255,255,255,255};
eeprom_onOff_out_init(corredor_on_adr,corredor_off_adr,1); //luz corredor
//fim corredor
eeprom_button_init(5,6,0,true);//2 //estores
eeprom_button_init(7,8,1,true);//2
off_adr[0]=255;
off_adr[1]=255;
on_adr[0]=5;
x_adr[0]=7;
eeprom_shutter_out_init(on_adr,x_adr,off_adr,off_adr,11,10,0,10);//up down fullup full down
eeprom_on_off_init(9,10,6);
eeprom_on_off_init(20,21,7);
unsigned int cama_on_adr[8]={9,255,255,255,255,255,255,255};
unsigned int cama_off_adr[8]={10,255,255,255,255,255,255,255};
eeprom_onOff_out_init(cama_on_adr,cama_off_adr,7);
cama_on_adr[0]=20;
cama_off_adr[0]=21;
eeprom_onOff_out_init(cama_on_adr,cama_off_adr,6);
/////////////////////////////////////////////////7
*/
/////////////////////QUARTO RENATA///////////////
//
// INPUTS
// 0,1 cozinha
// 2,3 quarto
//
// OUTPUTS
// 5 quarto renata economica
// 6 janela hologeneo
// 7 entrada
// 2 cozinha fluorescente
// 3 cima balcao halogeneo
// 4 divisoria halogeneo
// 10 balcao baixo verde
// 11 balcao cima verde
// 12 balcao cima vermelho
// 13 balcao cima azul
// 14 balcao baixo azul
// 15 balcao baixo vermelho
//INPUT INIT
eeprom_on_off_init(60,61,0);//on_adr off_adr real_btn interruptor cozinha 1
eeprom_on_off_init(62,63,1);//on_adr off_adr real_btn interruptor cozinha 2
// eeprom_dimmer_init(68,62,63,1);//dim_adr on_adr off_adr
eeprom_on_off_init(64,65,2);//on_adr off_adr real_btn interruptor quarto renata 1
// eeprom_on_off_init(66,67,3);//on_adr off_adr real_btn interruptor quarto renata 2
eeprom_dimmer_init(68,66,67,3);//dim_adr on_adr off_adr
//OUTPUT INIT
unsigned int on_adr[8]={60,255,255,255,255,255,255,255};
unsigned int off_adr[8]={61,10,255,255,255,255,255,255};
unsigned int dim_adr[8]={68,255,255,255,255,255,255,255};
eeprom_onOff_out_init(on_adr,off_adr,2); //luz cozinha fluorescente
on_adr[0]=62;
off_adr[0]=63;
eeprom_onOff_out_init(on_adr,off_adr,3); //luz cozinha cima balcao halogeneo
eeprom_onOff_out_init(on_adr,off_adr,4); //luz cozinha divisoria
eeprom_onOff_out_init(on_adr,off_adr,15); //luz balcao baixo vermelho
eeprom_onOff_out_init(on_adr,off_adr,12); //luz balcao cima vermelho
//eeprom_dimmer_out_init(dim_adr,on_adr,off_adr,3); //luz cozinha cima balcao halogeneo
//eeprom_dimmer_out_init(dim_adr,on_adr,off_adr,4); //luz cozinha divisoria
//eeprom_dimmer_out_init(dim_adr,on_adr,off_adr,15); //luz cozinha divisoria
on_adr[0]=64;
off_adr[0]=65;
eeprom_onOff_out_init(on_adr,off_adr,5); //luz quarto renata economica
on_adr[0]=66;
off_adr[0]=67;
// eeprom_onOff_out_init(on_adr,off_adr,7); //luz quarto renata entrada
// eeprom_onOff_out_init(on_adr,off_adr,6); //luz quarto renata janela
eeprom_dimmer_out_init(dim_adr,on_adr,off_adr,7); //luz quarto renata entrada
eeprom_dimmer_out_init(dim_adr,on_adr,off_adr,6); //luz quarto renata janela
readDevices();
#ifdef DEBUG
printf("inputs:%d outputs:%d %d %d\n\r",mydevices.numberOfInputs,mydevices.numberOfOutputs,((struct outputs)mydevices.myoutputs[0]).type,((struct outputs)mydevices.myoutputs[1]).type);
#endif
dimmer_outputs_init();
// printf("start %Lu %Lu %Lu\n\r",fpointer(N_LUZES,0),delays1[N_LUZES][0],delays2[N_LUZES][0]);
/*((struct light)mydevices.myoutputs[0].device).dim_value.value=50;
((struct light)mydevices.myoutputs[0].device).dim_value.needs_update=true;
((struct light)mydevices.myoutputs[0].device).off.value=1;
((struct light)mydevices.myoutputs[0].device).off.needs_update=true;
*/
write_outputs();
// printf("start %Lu\n\r",fpointer(N_LUZES,0));
interrupts_enable();
while(true){
restart_wdt();
if(syncError || oscError)
{
++ledErrorCounter;
if(ledErrorCounter>1000)
{
output_toggle(LED);
ledErrorCounter=0;
}
}
#ifdef DEBUG
if(kbhit())
{
setup_wdt(WDT_OFF);
disable_interrupts (GLOBAL) ;
goDebug();
}
#endif
process_outpoints();
write_outputs();
if(secondFlag)
{
secondFlag=false;
processTimedEvents();
if(!syncError && !oscError) output_toggle(LED);
}
// print_inputs(false);
}
}
/* TODO: 2x16 unsupported */
int
flash_erase (flash_info_t *info, int s_first, int s_last)
{
volatile unsigned char *addr = (uchar *)(info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
/* TODO: 2x16 unsupported */
if(info->portwidth==4) return 1;
if((info->flash_id & FLASH_TYPEMASK) == FLASH_ROM) return 1;
if((info->flash_id & FLASH_TYPEMASK) == FLASH_RAM) {
for (sect = s_first; sect<=s_last; sect++) {
int sector_size=info->size/info->sector_count;
addr = (uchar *)(info->start[sect]);
memset((void *)addr, 0, sector_size);
}
return 0;
}
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf ("- missing\n");
} else {
printf ("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id&FLASH_VENDMASK) == FLASH_MAN_INTEL) {
return flash_erase_intel(info,
(unsigned short)s_first,
(unsigned short)s_last);
}
#if 0
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf ("Can't erase unknown flash type %08lx - aborted\n",
info->flash_id);
return 1;
}
#endif
prot = 0;
for (sect=s_first; sect<=s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf ("- Warning: %d protected sectors will not be erased!\n",
prot);
} else {
printf ("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
flash_cmd(info->portwidth,addr,0x555,0xAA);
flash_cmd(info->portwidth,addr,0x2AA,0x55);
flash_cmd(info->portwidth,addr,0x555,0x80);
flash_cmd(info->portwidth,addr,0x555,0xAA);
flash_cmd(info->portwidth,addr,0x2AA,0x55);
/* Start erase on unprotected sectors */
for (sect = s_first; sect<=s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (uchar *)(info->start[sect]);
flash_cmd(info->portwidth,addr,0,0x30);
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay (1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer (0);
last = start;
addr = (volatile unsigned char *)(info->start[l_sect]);
/* broken for 2x16: TODO */
while ((addr[0] & 0x80) != 0x80) {
if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) {
printf ("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc ('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (volatile unsigned char *)info->start[0];
flash_cmd(info->portwidth,addr,0,0xf0);
flash_cmd(info->portwidth,addr,0,0xf0);
printf (" done\n");
return 0;
}
static int32
timer_thread(void *cookie)
{
status_t status = 0;
do {
bigtime_t timeout;
bigtime_t now;
cpu_status cpu;
timer_function func;
void * cookie;
int i;
int index;
cpu = disable_interrupts();
acquire_spinlock(&sTimerSpinlock);
now = system_time();
cookie = 0;
func = 0;
// find timer with smallest event time
index = -1;
timeout = B_INFINITE_TIMEOUT;
for (i = 0; i < sTimerCount; i++) {
if (sTimerData[i].next_event < timeout) {
timeout = sTimerData[i].next_event;
index = i;
}
}
if (timeout < now) {
// timer is ready for execution, load func and cookie
ASSERT(index >= 0 && index < sTimerCount);
func = sTimerData[index].func;
cookie = sTimerData[index].cookie;
if (sTimerData[index].periodic) {
// periodic timer is ready, update the entry
sTimerData[index].next_event += sTimerData[index].interval;
} else {
// single shot timer is ready, delete the entry
if (index != (sTimerCount - 1) && sTimerCount != 1) {
memcpy(&sTimerData[index], &sTimerData[sTimerCount - 1], sizeof(struct timer_info));
}
sTimerCount--;
}
}
release_spinlock(&sTimerSpinlock);
restore_interrupts(cpu);
// execute timer hook
if (timeout < now) {
ASSERT(func);
func(cookie);
continue;
}
status = acquire_sem_etc(sTimerSem, 1, B_ABSOLUTE_TIMEOUT, timeout);
} while (status != B_BAD_SEM_ID);
return 0;
}
int cpu_post_test_load (void)
{
int ret = 0;
unsigned int i;
int flag = disable_interrupts();
for (i = 0; i < cpu_post_load_size && ret == 0; i++)
{
struct cpu_post_load_s *test = cpu_post_load_table + i;
uchar data[16] =
{ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 };
ulong base0 = (ulong) (data + 8);
ulong base = base0;
ulong value;
if (test->index)
{
ulong code[] =
{
ASM_12(test->cmd, 5, 3, 4),
ASM_BLR,
};
cpu_post_exec_22w (code, &base, test->offset, &value);
}
else
{
ulong code[] =
{
ASM_11I(test->cmd, 4, 3, test->offset),
ASM_BLR,
};
cpu_post_exec_21w (code, &base, &value);
}
if (ret == 0)
{
if (test->update)
ret = base == base0 + test->offset ? 0 : -1;
else
ret = base == base0 ? 0 : -1;
}
if (ret == 0)
{
switch (test->width)
{
case 1:
ret = *(uchar *)(base0 + test->offset) == value ?
0 : -1;
break;
case 2:
ret = *(ushort *)(base0 + test->offset) == value ?
0 : -1;
break;
case 3:
ret = *(short *)(base0 + test->offset) == value ?
0 : -1;
break;
case 4:
ret = *(ulong *)(base0 + test->offset) == value ?
0 : -1;
break;
}
}
if (ret != 0)
{
post_log ("Error at load test %d !\n", i);
}
}
if (flag)
enable_interrupts();
return ret;
}
extern "C" int
_start(kernel_args *bootKernelArgs, int currentCPU)
{
if (bootKernelArgs->kernel_args_size != sizeof(kernel_args)
|| bootKernelArgs->version != CURRENT_KERNEL_ARGS_VERSION) {
// This is something we cannot handle right now - release kernels
// should always be able to handle the kernel_args of earlier
// released kernels.
debug_early_boot_message("Version mismatch between boot loader and "
"kernel!\n");
return -1;
}
smp_set_num_cpus(bootKernelArgs->num_cpus);
// wait for all the cpus to get here
smp_cpu_rendezvous(&sCpuRendezvous);
// the passed in kernel args are in a non-allocated range of memory
if (currentCPU == 0)
memcpy(&sKernelArgs, bootKernelArgs, sizeof(kernel_args));
smp_cpu_rendezvous(&sCpuRendezvous2);
// do any pre-booting cpu config
cpu_preboot_init_percpu(&sKernelArgs, currentCPU);
thread_preboot_init_percpu(&sKernelArgs, currentCPU);
// if we're not a boot cpu, spin here until someone wakes us up
if (smp_trap_non_boot_cpus(currentCPU, &sCpuRendezvous3)) {
// init platform
arch_platform_init(&sKernelArgs);
// setup debug output
debug_init(&sKernelArgs);
set_dprintf_enabled(true);
dprintf("Welcome to kernel debugger output!\n");
dprintf("Haiku revision: %s\n", get_haiku_revision());
// init modules
TRACE("init CPU\n");
cpu_init(&sKernelArgs);
cpu_init_percpu(&sKernelArgs, currentCPU);
TRACE("init interrupts\n");
int_init(&sKernelArgs);
TRACE("init VM\n");
vm_init(&sKernelArgs);
// Before vm_init_post_sem() is called, we have to make sure that
// the boot loader allocated region is not used anymore
boot_item_init();
debug_init_post_vm(&sKernelArgs);
low_resource_manager_init();
// now we can use the heap and create areas
arch_platform_init_post_vm(&sKernelArgs);
lock_debug_init();
TRACE("init driver_settings\n");
driver_settings_init(&sKernelArgs);
debug_init_post_settings(&sKernelArgs);
TRACE("init notification services\n");
notifications_init();
TRACE("init teams\n");
team_init(&sKernelArgs);
TRACE("init ELF loader\n");
elf_init(&sKernelArgs);
TRACE("init modules\n");
module_init(&sKernelArgs);
TRACE("init semaphores\n");
haiku_sem_init(&sKernelArgs);
TRACE("init interrupts post vm\n");
int_init_post_vm(&sKernelArgs);
cpu_init_post_vm(&sKernelArgs);
commpage_init();
call_all_cpus_sync(non_boot_cpu_init, &sKernelArgs);
TRACE("init system info\n");
system_info_init(&sKernelArgs);
TRACE("init SMP\n");
smp_init(&sKernelArgs);
cpu_build_topology_tree();
TRACE("init timer\n");
timer_init(&sKernelArgs);
TRACE("init real time clock\n");
rtc_init(&sKernelArgs);
timer_init_post_rtc();
TRACE("init condition variables\n");
condition_variable_init();
// now we can create and use semaphores
TRACE("init VM semaphores\n");
vm_init_post_sem(&sKernelArgs);
TRACE("init generic syscall\n");
generic_syscall_init();
smp_init_post_generic_syscalls();
TRACE("init scheduler\n");
scheduler_init();
TRACE("init threads\n");
thread_init(&sKernelArgs);
TRACE("init kernel daemons\n");
kernel_daemon_init();
arch_platform_init_post_thread(&sKernelArgs);
TRACE("init I/O interrupts\n");
int_init_io(&sKernelArgs);
TRACE("init VM threads\n");
vm_init_post_thread(&sKernelArgs);
low_resource_manager_init_post_thread();
TRACE("init DPC\n");
dpc_init();
TRACE("init VFS\n");
vfs_init(&sKernelArgs);
#if ENABLE_SWAP_SUPPORT
TRACE("init swap support\n");
swap_init();
#endif
TRACE("init POSIX semaphores\n");
realtime_sem_init();
xsi_sem_init();
xsi_msg_init();
// Start a thread to finish initializing the rest of the system. Note,
// it won't be scheduled before calling scheduler_start() (on any CPU).
TRACE("spawning main2 thread\n");
thread_id thread = spawn_kernel_thread(&main2, "main2",
B_NORMAL_PRIORITY, NULL);
resume_thread(thread);
// We're ready to start the scheduler and enable interrupts on all CPUs.
scheduler_enable_scheduling();
// bring up the AP cpus in a lock step fashion
TRACE("waking up AP cpus\n");
sCpuRendezvous = sCpuRendezvous2 = 0;
smp_wake_up_non_boot_cpus();
smp_cpu_rendezvous(&sCpuRendezvous); // wait until they're booted
// exit the kernel startup phase (mutexes, etc work from now on out)
TRACE("exiting kernel startup\n");
gKernelStartup = false;
smp_cpu_rendezvous(&sCpuRendezvous2);
// release the AP cpus to go enter the scheduler
TRACE("starting scheduler on cpu 0 and enabling interrupts\n");
scheduler_start();
enable_interrupts();
} else {
// lets make sure we're in sync with the main cpu
// the boot processor has probably been sending us
// tlb sync messages all along the way, but we've
// been ignoring them
arch_cpu_global_TLB_invalidate();
// this is run for each non boot processor after they've been set loose
smp_per_cpu_init(&sKernelArgs, currentCPU);
// wait for all other AP cpus to get to this point
smp_cpu_rendezvous(&sCpuRendezvous);
smp_cpu_rendezvous(&sCpuRendezvous2);
// welcome to the machine
scheduler_start();
enable_interrupts();
}
#ifdef TRACE_BOOT
// We disable interrupts for this dprintf(), since otherwise dprintf()
// would acquires a mutex, which is something we must not do in an idle
// thread, or otherwise the scheduler would be seriously unhappy.
disable_interrupts();
TRACE("main: done... begin idle loop on cpu %d\n", currentCPU);
enable_interrupts();
#endif
for (;;)
cpu_idle();
return 0;
}
status_t
ice1712_buffer_exchange(ice1712 *card, multi_buffer_info *data)
{
int cpu_status = 0, status;
/* unsigned char peak[MAX_ADC];
int i;
*/
// TRACE("Avant Exchange p : %d, r : %d\n", data->playback_buffer_cycle, data->record_buffer_cycle);
status = acquire_sem_etc(card->buffer_ready_sem, 1, B_RELATIVE_TIMEOUT | B_CAN_INTERRUPT, 50000);
switch (status) {
case B_NO_ERROR:
// TRACE("B_NO_ERROR\n");
cpu_status = disable_interrupts();
// Playback buffers info
data->played_real_time = card->played_time;
data->played_frames_count = card->frames_count;
data->playback_buffer_cycle = (card->buffer - 1) % SWAPPING_BUFFERS; //Buffer played
// Record buffers info
data->recorded_real_time = card->played_time;
data->recorded_frames_count = card->frames_count;
data->record_buffer_cycle = (card->buffer - 1) % SWAPPING_BUFFERS; //Buffer filled
data->flags = B_MULTI_BUFFER_PLAYBACK | B_MULTI_BUFFER_RECORD;
restore_interrupts(cpu_status);
break;
case B_BAD_SEM_ID:
TRACE("B_BAD_SEM_ID\n");
break;
case B_INTERRUPTED:
TRACE("B_INTERRUPTED\n");
break;
case B_BAD_VALUE:
TRACE("B_BAD_VALUE\n");
break;
case B_WOULD_BLOCK:
TRACE("B_WOULD_BLOCK\n");
break;
case B_TIMED_OUT:
TRACE("B_TIMED_OUT\n");
start_DMA(card);
cpu_status = lock();
data->played_real_time = card->played_time;
data->playback_buffer_cycle = 0;
data->played_frames_count += card->buffer_size;
data->recorded_real_time = card->played_time;
data->record_buffer_cycle = 0;
data->recorded_frames_count += card->buffer_size;
data->flags = B_MULTI_BUFFER_PLAYBACK | B_MULTI_BUFFER_RECORD;
unlock(cpu_status);
break;
default:
TRACE("Default\n");
break;
}
if ((card->buffer % 1500) == 0) {
uint8 reg8, reg8_dir;
reg8 = read_gpio(card);
reg8_dir = read_cci_uint8(card, CCI_GPIO_DIRECTION_CONTROL);
TRACE("DEBUG === GPIO = %d (dir %d)\n", reg8, reg8_dir);
reg8 = spdif_read(card, CS84xx_VERSION_AND_CHIP_ID);
TRACE("DEBUG === S/PDif Version : 0x%x\n", reg8);
}
return B_OK;
}
for (ih = TAILQ_FIRST(&iq->iq_list); ih != NULL;
ih = TAILQ_NEXT(ih, ih_list)) {
vic1_irqs |= vic1_imask[ih->ih_ipl];
vic2_irqs |= vic2_imask[ih->ih_ipl];
}
iq->iq_vic1_mask = vic1_irqs;
iq->iq_vic2_mask = vic2_irqs;
}
}
inline void
splx(int new)
{
u_int oldirqstate;
oldirqstate = disable_interrupts(I32_bit);
set_curcpl(new);
if (new != hardware_spl_level) {
hardware_spl_level = new;
ep93xx_set_intrmask(vic1_imask[new], vic2_imask[new]);
}
restore_interrupts(oldirqstate);
#ifdef __HAVE_FAST_SOFTINTS
cpu_dosoftints();
#endif
}
int
_splraise(int ipl)
{
static int flash_erase_16(flash_info_t * info, int s_first, int s_last)
{
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[0]);
volatile CONFIG_SYS_FLASH_WORD_SIZE *addr2;
int flag, prot, sect;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN)
printf("- missing\n");
else
printf("- no sectors to erase\n");
return 1;
}
if (info->flash_id == FLASH_UNKNOWN) {
printf("Can't erase unknown flash type - aborted\n");
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect])
prot++;
}
if (prot)
printf("- Warning: %d protected sectors will not be erased!", prot);
printf("\n");
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr2 = (CONFIG_SYS_FLASH_WORD_SIZE *) (info->start[sect]);
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x80008000;
addr[CONFIG_SYS_FLASH_ADDR0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xAA00AA00;
addr[CONFIG_SYS_FLASH_ADDR1] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x55005500;
addr2[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0x30003000; /* sector erase */
/*
* Wait for each sector to complete, it's more
* reliable. According to AMD Spec, you must
* issue all erase commands within a specified
* timeout. This has been seen to fail, especially
* if printf()s are included (for debug)!!
*/
wait_for_DQ7_16(info, sect);
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
/* reset to read mode */
addr = (CONFIG_SYS_FLASH_WORD_SIZE *) info->start[0];
addr[0] = (CONFIG_SYS_FLASH_WORD_SIZE) 0xF000F000; /* reset bank */
printf(" done\n");
return 0;
}
void watchdog_reset(void)
{
int re_enable = disable_interrupts();
reset_4xx_watchdog();
if (re_enable) enable_interrupts();
}
int flash_erase(flash_info_t * info, int s_first, int s_last)
{
vu_char *addr = (vu_char *) (info->start[0]);
int flag, prot, sect, l_sect;
ulong start, now, last;
if ((s_first < 0) || (s_first > s_last)) {
if (info->flash_id == FLASH_UNKNOWN) {
printf("- missing\n");
} else {
printf("- no sectors to erase\n");
}
return 1;
}
if ((info->flash_id == FLASH_UNKNOWN) ||
(info->flash_id > FLASH_AMD_COMP)) {
printf("Can't erase unknown flash type %08lx - aborted\n", info->flash_id);
return 1;
}
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect]) {
prot++;
}
}
if (prot) {
printf("- Warning: %d protected sectors will not be erased!\n", prot);
} else {
printf("\n");
}
l_sect = -1;
/* Disable interrupts which might cause a timeout here */
flag = disable_interrupts();
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
addr[0x0555] = 0x80;
addr[0x0555] = 0xAA;
addr[0x02AA] = 0x55;
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last; sect++) {
if (info->protect[sect] == 0) { /* not protected */
addr = (vu_char *) (info->start[sect]);
addr[0] = 0x30;
l_sect = sect;
}
}
/* re-enable interrupts if necessary */
if (flag)
enable_interrupts();
/* wait at least 80us - let's wait 1 ms */
udelay(1000);
/*
* We wait for the last triggered sector
*/
if (l_sect < 0)
goto DONE;
start = get_timer(0);
last = start;
addr = (vu_char *) (info->start[l_sect]);
while ((addr[0] & 0x80) != 0x80) {
if ((now = get_timer(start)) > CONFIG_SYS_FLASH_ERASE_TOUT) {
printf("Timeout\n");
return 1;
}
/* show that we're waiting */
if ((now - last) > 1000) { /* every second */
putc('.');
last = now;
}
}
DONE:
/* reset to read mode */
addr = (vu_char *) info->start[0];
addr[0] = 0xF0; /* reset bank */
printf(" done\n");
return 0;
}
void PwmMngr::init(void)
{
uint8_t timers = 0;
// discover which timers must be configured
for(int b = 0; b < BoosterMngr::nboosters; b++)
timers |= get_timer(BoosterMngr::boosters[b].pwmSignalPin);
// CONFIGURE TIMERS
disable_interrupts();
#ifndef SIMULATOR
if(timers & (1 << 1)) {
// timer 1
TCCR1A = (TCCR1A & 0b00001100)
// 0b00______ Normal port operation, OC1A disconnected
// 0b__00____ Normal port operation, OC1B disconnected
// 0b____**__ Reserved
| 0b00000001; // 0b______01 Fast PWM 8-bit (!WGM13, WGM12, !WGM11, WGM10)
TCCR1B = (TCCR1B & 0b11100000)
// 0b***_____ ICNC1, ICES1, Reserved
| 0b00001000 // 0b___01___ Fast PWM 8-bit (!WGM13, WGM12, !WGM11, WGM10)
| 0x04; // 0b_____100 clock prescaler 0x04 (16e6/256 = 62.5 khz)
TIMSK1 &= 0b11011000; // disable all timer 1 interrupts
// 0b**_**___ Reserved
// 0b__0_____ input capture interrupt enable
// 0b_____0__ OCIE1B: output compare B match interrupt enable
// 0b______0_ OCIE1A: output compare A match interrupt enable
// 0b_______0 TOIE1: overflow interrupt enable
OCR1A = OCR1B = 0;
}
if(timers & (1 << 2)) {
// timer 2
TCCR2A = (TCCR2A & 0b00001100)
// 0b00______ Normal port operation, OC2A disconnected
// 0b__00____ Normal port operation, OC2B disconnected
// 0b____**__ reserved
| 0b00000011; // 0b00000011 Fast PWM (!WGM22, WGM21, WGM20)
TCCR2B = (TCCR2B & 0b11110000)
// 0b****____ FOC2A, FOC2B, Reserved, Reserved
| 0b00000000 // 0b____0___ Fast PWM (!WGM22, WGM21, WGM20)
| 0x6; // 0b_____110 clock prescaler 0x6 (16e6/256 = 62.5 khz)
TIMSK2 &= 0b11111000; // disable all timer 2 interrupts
OCR2A = OCR2B = 0;
}
#if defined (__AVR_ATmega2560__)
if(timers & (1 << 3)) {
// timer 1
TCCR3A = (TCCR3A & 0b00000000)
// 0b00______ Normal port operation, OC3A disconnected
// 0b__00____ Normal port operation, OC3B disconnected
// 0b____00__ Normal port operation, OC3C disconnected
| 0b00000001; // 0b______01 Fast PWM 8-bit (!WGM33, WGM32, !WGM31, WGM30)
TCCR3B = (TCCR3B & 0b11100000)
// 0b***_____ ICNC3, ICES3, Reserved
| 0b00001000 // 0b___01___ Fast PWM 8-bit (!WGM33, WGM32, !WGM31, WGM30)
| 0x04; // 0b_____100 clock prescaler 0x04 (16e6/256 = 62.5 khz)
TIMSK3 &= 0b11010000; // disable all timer 1 interrupts
// 0b**_*____ Reserved
// 0b__0_____ input capture interrupt enable
// 0b____0___ OCIE3C: output compare B match interrupt enable
// 0b_____0__ OCIE3B: output compare B match interrupt enable
// 0b______0_ OCIE3A: output compare A match interrupt enable
// 0b_______0 TOIE3: overflow interrupt enable
OCR3A = OCR3B = OCR3C = 0;
}
#endif
#endif
enable_interrupts();
//-------------------------------------------
// RESET PWM STATUS
for(int b = 0; b < BoosterMngr::nboosters; b++) {
booster_activate(b);
BoosterMngr::boosters[b].reset();
}
}
void ksystime_get_uptime(SYSTIME* res)
{
disable_interrupts();
ksystime_get_uptime_internal(res);
enable_interrupts();
}
int do_bootm_subcommand(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
int ret = 0;
long state;
cmd_tbl_t *c;
boot_os_fn *boot_fn;
c = find_cmd_tbl(argv[1], &cmd_bootm_sub[0], ARRAY_SIZE(cmd_bootm_sub));
if (c) {
state = (long)c->cmd;
/* treat start special since it resets the state machine */
if (state == BOOTM_STATE_START) {
argc--;
argv++;
return bootm_start(cmdtp, flag, argc, argv);
}
} else {
/* Unrecognized command */
return CMD_RET_USAGE;
}
if (images.state >= state) {
printf("Trying to execute a command out of order\n");
return CMD_RET_USAGE;
}
images.state |= state;
boot_fn = boot_os[images.os.os];
switch (state) {
ulong load_end;
case BOOTM_STATE_START:
/* should never occur */
break;
case BOOTM_STATE_LOADOS:
ret = bootm_load_os(images.os, &load_end, 0);
if (ret)
return ret;
lmb_reserve(&images.lmb, images.os.load,
(load_end - images.os.load));
break;
#ifdef CONFIG_SYS_BOOT_RAMDISK_HIGH
case BOOTM_STATE_RAMDISK:
{
ulong rd_len = images.rd_end - images.rd_start;
char str[17];
ret = boot_ramdisk_high(&images.lmb, images.rd_start,
rd_len, &images.initrd_start, &images.initrd_end);
if (ret)
return ret;
sprintf(str, "%lx", images.initrd_start);
setenv("initrd_start", str);
sprintf(str, "%lx", images.initrd_end);
setenv("initrd_end", str);
}
break;
#endif
#if defined(CONFIG_OF_LIBFDT)
case BOOTM_STATE_FDT:
{
boot_fdt_add_mem_rsv_regions(&images.lmb,
images.ft_addr);
ret = boot_relocate_fdt(&images.lmb,
&images.ft_addr, &images.ft_len);
break;
}
#endif
case BOOTM_STATE_OS_CMDLINE:
ret = boot_fn(BOOTM_STATE_OS_CMDLINE, argc, argv, &images);
if (ret)
printf("cmdline subcommand not supported\n");
break;
case BOOTM_STATE_OS_BD_T:
ret = boot_fn(BOOTM_STATE_OS_BD_T, argc, argv, &images);
if (ret)
printf("bdt subcommand not supported\n");
break;
case BOOTM_STATE_OS_PREP:
ret = boot_fn(BOOTM_STATE_OS_PREP, argc, argv, &images);
if (ret)
printf("prep subcommand not supported\n");
break;
case BOOTM_STATE_OS_GO:
disable_interrupts();
arch_preboot_os();
boot_fn(BOOTM_STATE_OS_GO, argc, argv, &images);
break;
}
return ret;
}
/*
* This function is called from accdesk_start (in gemstart.S) which
* is itself called from gem_main() below.
*
* It runs under a separate process which terminates on shutdown or
* resolution change (see accdesk_start). This ensures that all
* memory allocated to or by desk accessories is automatically freed
* on resolution change.
*/
void run_accs_and_desktop(void)
{
WORD i;
BOOL isgem;
/* load gem resource and fix it up before we go */
gem_rsc_init();
/* get mice forms */
ad_armice = (MFORM *)rs_bitblk[MICE00].bi_pdata;
ad_hgmice = (MFORM *)rs_bitblk[MICE02].bi_pdata;
/* init button stuff */
gl_btrue = 0x0;
gl_bdesired = 0x0;
gl_bdely = 0x0;
gl_bclick = 0x0;
gl_logdrv = dos_gdrv() + 'A'; /* boot directory */
gsx_init(); /* do gsx open work station */
load_accs(num_accs); /* load up to 'num_accs' desk accessories */
/* fix up icons */
for (i = 0; i < 3; i++) {
memcpy(&bi, &rs_bitblk[NOTEBB+i], sizeof(BITBLK));
gsx_trans(bi.bi_pdata, bi.bi_wb, bi.bi_pdata, bi.bi_wb, bi.bi_hl);
}
/* take the critical err handler int. */
disable_interrupts();
takeerr();
enable_interrupts();
sh_tographic(); /* go into graphic mode */
/* take the tick interrupt */
disable_interrupts();
gl_ticktime = gsx_tick(tikaddr, &tiksav);
enable_interrupts();
/* set initial click rate: must do this after setting gl_ticktime */
ev_dclick(3, TRUE);
/* fix up the GEM rsc file now that we have an open WS */
gem_rsc_fixit();
wm_start(); /* initialise window vars */
fs_start(); /* startup gem libs */
sh_curdir(D.s_cdir); /* remember current desktop directory */
isgem = process_inf2(); /* process emudesk.inf part 2 */
dsptch(); /* off we go !!! */
all_run(); /* let them run */
sh_init(); /* init for shell loop */
sh_main(isgem); /* main shell loop */
/* give back the tick */
disable_interrupts();
gl_ticktime = gsx_tick(tiksav, &tiksav);
enable_interrupts();
/* close workstation */
gsx_wsclose();
}
int flash_erase (flash_info_t *info, int s_first, int s_last) {
int iflag, cflag, prot, sect;
int rc = ERR_OK;
/* first look for protection bits */
if (info->flash_id == FLASH_UNKNOWN)
return ERR_UNKNOWN_FLASH_TYPE;
if ((s_first < 0) || (s_first > s_last))
return ERR_INVAL;
if ((info->flash_id & FLASH_VENDMASK) != (FLASH_MAN_MT & FLASH_VENDMASK))
return ERR_UNKNOWN_FLASH_VENDOR;
prot = 0;
for (sect = s_first; sect <= s_last; ++sect) {
if (info->protect[sect])
prot++;
}
if (prot) {
printf("protected!\n");
return ERR_PROTECTED;
}
/*
* Disable interrupts which might cause a timeout
* here. Remember that our exception vectors are
* at address 0 in the flash, and we don't want a
* (ticker) exception to happen while the flash
* chip is in programming mode.
*/
cflag = icache_status();
icache_disable();
iflag = disable_interrupts();
/* Start erase on unprotected sectors */
for (sect = s_first; sect <= s_last && !ctrlc(); sect++) {
printf("Erasing sector %2d ... ", sect);
/* arm simple, non interrupt dependent timer */
reset_timer_masked();
SF_NvmodeErase();
SF_NvmodeWrite();
SF_Erase(CFG_FLASH_BASE + (0x0100000 * sect));
SF_Normal();
printf("ok.\n");
}
if (ctrlc())
printf("User Interrupt!\n");
if (iflag)
enable_interrupts();
if (cflag)
icache_enable();
return rc;
}
void gem_main(void)
{
WORD i;
sh_rdinf(); /* get start of emudesk.inf */
if (!gl_changerez) /* can't be here because of rez change, */
process_inf1(); /* so see if .inf says we need to change rez */
if (gl_changerez) {
switch(gl_changerez) {
#if CONF_WITH_ATARI_VIDEO
case 1: /* ST(e) or TT display */
Setscreen(-1L,-1L,gl_nextrez-2,0);
initialise_palette_registers(gl_nextrez-2,0);
break;
#endif
#if CONF_WITH_VIDEL
case 2: /* Falcon display */
Setscreen(-1L, -1L, FALCON_REZ, gl_nextrez);
initialise_palette_registers(FALCON_REZ,gl_nextrez);
break;
#endif
}
gsx_wsclear(); /* avoid artefacts that may show briefly */
/*
* resolution change always resets the default drive to the
* boot device. TOS3 issues a Dsetdrv() when this happens,
* which Hatari's GEMDOS drive emulation uses to keep track
* of the current drive. we do the same.
*/
dos_sdrv(bootdev);
}
ml_ocnt = 0;
gl_changerez = FALSE;
mn_init(); /* initialise variables for menu_register() */
num_accs = count_accs(); /* puts ACC names in acc_name[] */
D.g_acc = NULL;
if (num_accs)
D.g_acc = dos_alloc(num_accs*sizeof(AESPROCESS));
if (D.g_acc)
memset(D.g_acc,0x00,num_accs*sizeof(AESPROCESS));
else num_accs = 0;
totpds = num_accs + 2;
disable_interrupts();
set_aestrap(); /* set trap#2 -> aestrap */
/* init event recorder */
gl_recd = FALSE;
gl_rlen = 0;
gl_rbuf = NULL;
/* link up all the evb's to the event unused list */
eul = NULL;
for (i = 0; i < 2; i++)
ev_init(D.g_int[i].a_evb,EVBS_PER_PD);
for (i = 0; i < num_accs; i++)
ev_init(D.g_acc[i].a_evb,EVBS_PER_PD);
/* initialize sync blocks */
wind_spb.sy_tas = 0;
wind_spb.sy_owner = NULL;
wind_spb.sy_wait = 0;
/*
* init processes - TODO: should go in gempd or gemdisp.
*/
/* initialize list and unused lists */
nrl = drl = NULL;
dlr = zlr = NULL;
fph = fpt = fpcnt = 0;
/* init initial process */
for(i=totpds-1; i>=0; i--)
{
rlr = pd_index(i);
if (i < 2)
{
rlr->p_uda = &D.g_int[i].a_uda;
rlr->p_cda = &D.g_int[i].a_cda;
}
else
{
rlr->p_uda = &D.g_acc[i-2].a_uda;
rlr->p_cda = &D.g_acc[i-2].a_cda;
}
rlr->p_qaddr = rlr->p_queue;
rlr->p_qindex = 0;
memset(rlr->p_name, ' ', AP_NAMELEN);
rlr->p_appdir[0] = '\0'; /* by default, no application directory */
/* if not rlr then initialize his stack pointer */
if (i != 0)
rlr->p_uda->u_spsuper = &rlr->p_uda->u_supstk;
rlr->p_pid = i;
rlr->p_stat = 0;
}
curpid = 0;
rlr->p_pid = curpid++;
rlr->p_link = NULL;
/* end of process init */
/* restart the tick */
enable_interrupts();
/*
* screen manager process init. this process starts out owning the mouse
* and the keyboard. it has a pid == 1
*/
gl_mowner = ctl_pd = iprocess("SCRENMGR", ctlmgr);
/*
* run the accessories and the desktop until termination
* (for shutdown or resolution change)
*/
aes_run_rom_program(accdesk_start);
/* restore previous trap#2 address */
disable_interrupts();
unset_aestrap();
enable_interrupts();
if (D.g_acc)
dos_free((LONG)D.g_acc);
}
void main()
{
disable_interrupts(GLOBAL);
setup_spi(SPI_MASTER | SPI_MODE_0_0 | SPI_CLK_DIV_16 );
setup_spi2(SPI_MASTER | SPI_MODE_0_0 | SPI_CLK_DIV_16 );
setup_adc_ports(sAN0|sAN1|sAN2|sAN3|sAN4|VSS_4V096);
setup_adc(ADC_CLOCK_INTERNAL|ADC_TAD_MUL_0);
// TIMER 0 is being used to service the WTD
setup_timer_0(T0_INTERNAL|T0_DIV_256);
/* sets the internal clock as source and prescale 256.
At 10 Mhz timer0 will increment every 0.4us (Fosc*4) in this setup and overflows every
6.71 seconds. Timer0 defaults to 16-bit if RTCC_8_BIT is not used.
Fosc = 10 MHz, Fosc/4 = 2.5 Mhz, div 256 = 0.0001024 s, 65536 increments = 6.71 sec
Fosc = 64 MHz, Fosc/4 = 16 Mhz, div 256 = 0.000016 s, 65536 increments = 1.05 sec
.. pre-load with 3036 to get exact 1.0000 sec value
*/
// TIMER 1 is used to extinguish the LED
setup_timer_1(T1_INTERNAL|T1_DIV_BY_8);
/* sets the internal clock as source and prescale 4.
At 10Mhz timer0 will increment every 0.4us in this setup and overflows every
104.8 ms. Timer1 is 16-bit.
Fosc = 10 Mhz ... 2.5 MHz / div 4 = 0.00000160 s * 65536 = 0.104858 sec
Fosc = 64 Mhz ... 16 MHz / div 4 = 0.00000025 s * 65536 = 0.016384 sec
Fosc = 64 Mhz ... 16 MHz / div 8 = 0.00000200 s * 65536 = 0.032768 sec
*/
setup_stepper_pwm(); // Uses TIMER 2
// TIMER 3 is used for stepper motor intervals
setup_timer_3(T3_INTERNAL | T3_DIV_BY_1); // 16 bit timer
// TIMER 4 is use for serial time-outs. 8-bit timer.
setup_timer_4(T4_DIV_BY_4, 127, 1);
setup_comparator(NC_NC_NC_NC);
setup_oscillator(OSC_16MHZ | OSC_PLL_ON); // Fosc = 64 MHz
ext_int_edge(0, H_TO_L); // Set up PIC18 EXT0
enable_interrupts(INT_EXT);
start_heartbeat();
enable_interrupts(GLOBAL);
init_hardware();
motor_sleep_rdy();
sleep_mode = FALSE;
busy_set();
init_nv_vars();
get_step_vars();
init_aws();
blink();
//Add for TCP/IP interface
//delay_ms(15000);
signon();
RTC_read();
RTC_last_power();
RTC_reset_HT();
RTC_read();
RTC_read_flags();
if(nv_sd_status>0) fprintf(COM_A,"@SD=%Lu\r\n", nv_sd_status);
init_rtc(); // This is the FAT RTC
sd_status = init_sdcard();
if(sd_status>0) msg_card_fail();
reset_event();
if(m_error[0] > 0 || m_error[1] > 0) msg_mer();
if (m_comp[0]==FALSE) {
e_port[0]=0;
write16(ADDR_E1_PORT,0);
fprintf(COM_A, "@MC1,%Lu,%Ld\r\n", m_comp[0],e_port[0]);
}
if (m_comp[1]==FALSE) {
m_lin_pos[1]=-1;
write16(ADDR_M2_LIN_POS, -1);
fprintf(COM_A, "@MC2,%Lu,%Ld\r\n", m_comp[1],m_lin_pos[1]);
}
if (nv_cmd_mode == FALSE){
for(dt=0; dt<100; ++dt){
blip();
if (nv_cmd_mode == TRUE) {
busy_clear();
fputs("@OK!", COM_A);
command_prompt();
dt = 100;
}
}
}
else command_prompt();
user_quit = auto_sample_ready();
reset_cpu();
}
/*
* void cpu_reboot(int howto, char *bootstr)
*
* Reboots the system
*
* Deal with any syncing, unmounting, dumping and shutdown hooks,
* then reset the CPU.
*/
void
cpu_reboot(int howto, char *bootstr)
{
/*
* If we are still cold then hit the air brakes
* and crash to earth fast
*/
if (cold) {
doshutdownhooks();
pmf_system_shutdown(boothowto);
printf("The operating system has halted.\n");
printf("Please press any key to reboot.\n\n");
cngetc();
printf("rebooting...\n");
goto reset;
}
/* Disable console buffering */
/*
* If RB_NOSYNC was not specified sync the discs.
* Note: Unless cold is set to 1 here, syslogd will die during the
* unmount. It looks like syslogd is getting woken up only to find
* that it cannot page part of the binary in as the filesystem has
* been unmounted.
*/
if (!(howto & RB_NOSYNC))
bootsync();
/* Say NO to interrupts */
splhigh();
/* Do a dump if requested. */
if ((howto & (RB_DUMP | RB_HALT)) == RB_DUMP)
dumpsys();
/* Run any shutdown hooks */
doshutdownhooks();
pmf_system_shutdown(boothowto);
/* Make sure IRQ's are disabled */
IRQdisable;
if (howto & RB_HALT) {
printf("The operating system has halted.\n");
printf("Please press any key to reboot.\n\n");
cngetc();
}
printf("rebooting...\n\r");
reset:
/*
* Make really really sure that all interrupts are disabled,
* and poke the Internal Bus and Peripheral Bus reset lines.
*/
(void) disable_interrupts(I32_bit|F32_bit);
*(volatile uint32_t *)(IYONIX_80321_VBASE + VERDE_ATU_BASE +
ATU_PCSR) = PCSR_RIB | PCSR_RPB;
/* ...and if that didn't work, just croak. */
printf("RESET FAILED!\n");
for (;;);
}
status_t
device_read(void *data, off_t pos, void *buffer, size_t *_length)
{
struct sis_info *info;
status_t status;
size_t size;
int32 blockFlag;
uint32 check;
int16 current;
if (checkDeviceInfo(info = data) != B_OK) {
#ifndef __HAIKU__
*_length = 0;
// net_server work-around; it obviously doesn't care about error conditions
// For Haiku, this can be removed
#endif
return B_BAD_VALUE;
}
blockFlag = info->blockFlag;
TRACE(("read: rx: isr = %d, free = %d, current = %d, blockFlag = %lx\n",
info->rxInterruptIndex, info->rxFree, info->rxCurrent, blockFlag));
// read is not reentrant
if (atomic_or(&info->rxLock, 1)) {
#ifndef __HAIKU__
*_length = 0;
#endif
return B_ERROR;
}
// block until data is available (if blocking is allowed)
if ((status = acquire_sem_etc(info->rxSem, 1, B_CAN_INTERRUPT | blockFlag, 0)) != B_NO_ERROR) {
TRACE(("cannot acquire read sem: %lx, %s\n", status, strerror(status)));
atomic_and(&info->rxLock, 0);
#ifndef __HAIKU__
*_length = 0;
#endif
return status;
}
/* three cases, frame is good, bad, or we don't own the descriptor */
current = info->rxCurrent;
check = info->rxDescriptor[current].status;
if (!(check & SiS900_DESCR_OWN)) { // the buffer is still in use!
TRACE(("ERROR: read: buffer %d still in use: %lx\n", current, status));
atomic_and(&info->rxLock, 0);
#ifndef __HAIKU__
*_length = 0;
#endif
return B_BUSY;
}
if (check & (SiS900_DESCR_Rx_ABORT | SiS900_DESCR_Rx_OVERRUN |
SiS900_DESCR_Rx_LONG_PACKET | SiS900_DESCR_Rx_RUNT_PACKET |
SiS900_DESCR_Rx_INVALID_SYM | SiS900_DESCR_Rx_FRAME_ALIGN |
SiS900_DESCR_Rx_CRC_ERROR)) {
TRACE(("ERROR read: packet with errors: %ld\n", check));
*_length = 0;
} else {
// copy buffer
size = (check & SiS900_DESCR_SIZE_MASK) - CRC_SIZE;
if (size > MAX_FRAME_SIZE || size > *_length) {
TRACE(("ERROR read: bad frame size %ld\n", size));
size = *_length;
} else if (size < *_length)
*_length = size;
memcpy(buffer, (void *)info->rxBuffer[current], size);
}
info->rxCurrent = (current + 1) & NUM_Rx_MASK;
/* update indexes and buffer ownership */
{
cpu_status former;
former = disable_interrupts();
acquire_spinlock(&info->rxSpinlock);
// release buffer to ring
info->rxDescriptor[current].status = MAX_FRAME_SIZE + CRC_SIZE;
info->rxFree++;
release_spinlock(&info->rxSpinlock);
restore_interrupts(former);
}
atomic_and(&info->rxLock, 0);
return B_OK;
}
u_int
initarm(void *arg)
{
ofw_handle_t ofw_handle = arg;
paddr_t pclean;
vaddr_t isa_io_virtaddr, isa_mem_virtaddr;
paddr_t isadmaphysbufs;
extern char shark_fiq[], shark_fiq_end[];
/* Don't want to get hit with interrupts 'til we're ready. */
(void)disable_interrupts(I32_bit | F32_bit);
set_cpufuncs();
/* XXX - set these somewhere else? -JJK */
boothowto = 0;
/* Init the OFW interface. */
/* MUST do this before invoking any OFW client services! */
ofw_init(ofw_handle);
/* Configure ISA stuff: must be done before consinit */
ofw_configisa(&isa_io_physaddr, &isa_mem_physaddr);
/* Map-in ISA I/O and memory space. */
/* XXX - this should be done in the isa-bus attach routine! -JJK */
isa_mem_virtaddr = ofw_map(isa_mem_physaddr, L1_S_SIZE, 0);
isa_io_virtaddr = ofw_map(isa_io_physaddr, L1_S_SIZE, 0);
/* Set-up the ISA system: must be done before consinit */
isa_init(isa_io_virtaddr, isa_mem_virtaddr);
/* Initialize the console (which will call into OFW). */
/* This will allow us to see panic messages and other printf output. */
consinit();
/* Get boot info and process it. */
ofw_getbootinfo(&boot_file, &boot_args);
process_kernel_args();
ofw_configisadma(&isadmaphysbufs);
#if (NISADMA > 0)
isa_dma_init();
#endif
/* allocate a cache clean space */
if ((pclean = ofw_getcleaninfo()) != -1) {
sa1_cache_clean_addr = ofw_map(pclean, 0x4000 * 2,
L2_B | L2_C);
sa1_cache_clean_size = 0x4000;
}
/* Configure memory. */
ofw_configmem();
/*
* Set-up stacks.
* The kernel stack for SVC mode will be updated on return
* from this routine.
*/
set_stackptr(PSR_IRQ32_MODE, irqstack.pv_va + PAGE_SIZE);
set_stackptr(PSR_UND32_MODE, undstack.pv_va + PAGE_SIZE);
set_stackptr(PSR_ABT32_MODE, abtstack.pv_va + PAGE_SIZE);
/* Set-up exception handlers. */
/*
* Take control of selected vectors from OFW.
* We take: undefined, swi, pre-fetch abort, data abort, addrexc,
* irq, fiq
* OFW retains: reset
*/
arm32_vector_init(ARM_VECTORS_LOW, ARM_VEC_ALL & ~ARM_VEC_RESET);
data_abort_handler_address = (u_int)data_abort_handler;
prefetch_abort_handler_address = (u_int)prefetch_abort_handler;
undefined_handler_address =
(u_int)undefinedinstruction_bounce; /* why is this needed? -JJK */
/* Initialise the undefined instruction handlers. */
undefined_init();
/* Now for the SHARK-specific part of the FIQ set-up */
shark_fiqhandler.fh_func = shark_fiq;
shark_fiqhandler.fh_size = shark_fiq_end - shark_fiq;
shark_fiqhandler.fh_flags = 0;
shark_fiqhandler.fh_regs = &shark_fiqregs;
shark_fiqregs.fr_r8 = isa_io_virtaddr;
shark_fiqregs.fr_r9 = 0; /* no routine right now */
shark_fiqregs.fr_r10 = 0; /* no arg right now */
shark_fiqregs.fr_r11 = 0; /* scratch */
shark_fiqregs.fr_r12 = 0; /* scratch */
shark_fiqregs.fr_r13 = 0; /* must set a stack when r9 is set! */
if (fiq_claim(&shark_fiqhandler))
panic("Cannot claim FIQ vector.");
#if NKSYMS || defined(DDB) || defined(MODULAR)
#ifndef __ELF__
{
struct exec *kernexec = (struct exec *)KERNEL_TEXT_BASE;
extern int end;
extern char *esym;
ksyms_addsyms_elf(kernexec->a_syms, &end, esym);
}
#endif /* __ELF__ */
#endif /* NKSYMS || defined(DDB) || defined(MODULAR) */
#ifdef DDB
db_machine_init();
if (boothowto & RB_KDB)
Debugger();
#endif
/* Return the new stackbase. */
return(kernelstack.pv_va + USPACE_SVC_STACK_TOP);
}
