/* void DDR2_EMIF_Config(void); */ static void config_am335x_ddr2(void) { int data_macro_0 = 0; int data_macro_1 = 1; enable_ddr_clocks(); config_vtp(); Cmd_Macro_Config(); Data_Macro_Config(data_macro_0); Data_Macro_Config(data_macro_1); __raw_writel(PHY_RANK0_DELAY, DATA0_RANK0_DELAYS_0); __raw_writel(PHY_RANK0_DELAY, DATA1_RANK0_DELAYS_0); __raw_writel(DDR_IOCTRL_VALUE, DDR_CMD0_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, DDR_CMD1_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, DDR_CMD2_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, DDR_DATA0_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, DDR_DATA1_IOCTRL); __raw_writel(__raw_readl(DDR_IO_CTRL) & 0xefffffff, DDR_IO_CTRL); __raw_writel(__raw_readl(DDR_CKE_CTRL) | 0x00000001, DDR_CKE_CTRL); config_emif_ddr2(); }
static void config_am335x_mddr(void) { int data_macro_0 = 0; int data_macro_1 = 1; enable_ddr_clocks(); Cmd_Macro_Config(); Data_Macro_Config(data_macro_0); Data_Macro_Config(data_macro_1); __raw_writel(PHY_RANK0_DELAY, DATA0_RANK0_DELAYS_0); __raw_writel(PHY_RANK0_DELAY, DATA1_RANK0_DELAYS_0); /* set IO control registers */ __raw_writel(DDR_IOCTRL_VALUE, DDR_CMD0_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, DDR_CMD1_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, DDR_CMD2_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, DDR_DATA0_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, DDR_DATA1_IOCTRL); __raw_writel(__raw_readl(DDR_IO_CTRL) | 0x10000000, DDR_IO_CTRL); __raw_writel(__raw_readl(DDR_CKE_CTRL) | 0x00000001, DDR_CKE_CTRL); config_emif(); /* vtp enable is here */ }
static void beaglebone_config_ddr(void) { enable_ddr_clocks(); beaglebone_config_vtp(); beaglebone_cmd_macro_config(); beaglebone_data_macro_config(0); beaglebone_data_macro_config(1); __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA0_RANK0_DELAYS_0); __raw_writel(PHY_RANK0_DELAY, AM33XX_DATA1_RANK0_DELAYS_0); __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD0_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD1_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_CMD2_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA0_IOCTRL); __raw_writel(DDR_IOCTRL_VALUE, AM33XX_DDR_DATA1_IOCTRL); __raw_writel(__raw_readl(AM33XX_DDR_IO_CTRL) & 0xefffffff, AM33XX_DDR_IO_CTRL); __raw_writel(__raw_readl(AM33XX_DDR_CKE_CTRL) | 0x00000001, AM33XX_DDR_CKE_CTRL); beaglebone_config_emif_ddr2(); }