/*This function simulate a action on the cache
*@param cache * c, the cache we using
*@param cacheParam p, the current state of the cache
*@param memAddr a, the memory address
*@return new state of the cache
*/
cacheParam rSim(cache* c, cacheParam p, memAddr a, int * state){
int numLines = p.E;
int prevHits = p.hit;
//calculate tag size
int tagSize = 64 - (p.s + p.b);
//extract tag
memAddr input = a >> (p.s + p.b);
//caculate set Index
unsigned long long temp = (a << tagSize);
unsigned long long setIndex = temp >> (tagSize + p.b);
//search for hit cache
cache_set * set = c -> set;
cache_set cacheset= set[setIndex];
int lineIndex; //counter
block line;
int isFull = 1;
for (lineIndex = 0; lineIndex < numLines; lineIndex++){
line = cacheset.blocks[lineIndex];
if (line.v){
if (line.tag == input){
p.hit++;
line.lru++;
cacheset.blocks[lineIndex] = line;
*state = 0;
}
} else if (!(line.v) && (isFull)){
//set have an empty line
isFull = 0;
}
}
if (prevHits == p.hit) {
//a miss occur
p.miss++;
*state = 1;
} else return p;
int usedLines = highestLRU(cacheset, p);
int lruCache = findLRU(cacheset, p);
//if miss we have to evict a cache or fill a empty cache
if (isFull){
cacheset.blocks[lruCache].tag = input;
cacheset.blocks[lruCache].lru = usedLines + 1;
p.evict++;
*state = 2;
} else {
int empty = findEmpty(cacheset, p);
cacheset.blocks[empty].v = 1;
cacheset.blocks[empty].tag = input;
cacheset.blocks[empty].lru = usedLines + 1;
}
return p;
}
// Find free frame for pinning
BM_Frame* findFreeFrame(BM_BufferPool *const bm)
{
BM_Frame *frame = NULL;
RC findResult = RC_OK;
switch (bm->strategy) {
case RS_FIFO:
frame = findFIFO(bm);
findResult = RC_OK;
break;
case RS_LRU:
frame = findLRU(bm);
findResult = RC_OK;
break;
}
return frame;
}
