/* * FPGA post configuration function. Blip the FPGA reset line and then see if * the FPGA appears to be running. */ int fpga_post_config_fn(int cookie) { pmc440_fpga_t *fpga = (pmc440_fpga_t *)FPGA_BA; int rc=0; char *s; debug("%s:%d: FPGA post configuration\n", __FUNCTION__, __LINE__); /* enable PLD0..7 pins */ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) & ~GPIO1_IOEN_N); fpga_reset(TRUE); udelay (100); fpga_reset(FALSE); udelay (100); FPGA_OUT32(&fpga->status, (gd->board_type << STATUS_HWREV_SHIFT) & STATUS_HWREV_MASK); /* NGCC/CANDES only: enable ledlink */ if ((s = getenv("bd_type")) && ((!strcmp(s, "ngcc")) || (!strcmp(s, "candes")))) FPGA_SETBITS(&fpga->ctrla, 0x29f8c000); return rc; }
int fpga_post_config_fn(int cookie) { debug("%s:%d: FPGA post-configuration\n", __func__, __LINE__); fpga_reset(true); udelay(100); fpga_reset(false); return 0; }
static int fpga_download(int iobase, int bitrate) { int i, rc; unsigned char *pbits; pbits = get_mcs(bitrate); if (pbits == NULL) return -1; fpga_reset(iobase); for (i = 0; i < YAM_FPGA_SIZE; i++) { if (fpga_write(iobase, pbits[i])) { printk(KERN_ERR "yam: error in write cycle\n"); return -1; /* write... */ } } fpga_write(iobase, 0xFF); rc = inb(MSR(iobase)); /* check DONE signal */ /* Needed for some hardwares */ delay(50); return (rc & MSR_DSR) ? 0 : -1; }
/* * FPGA pre-configuration function. Just make sure that * FPGA reset is asserted to keep the FPGA from starting up after * configuration. */ int fpga_pre_config_fn(int cookie) { debug("%s:%d: FPGA pre-configuration\n", __FUNCTION__, __LINE__); fpga_reset(TRUE); /* release init# */ out_be32((void*)GPIO0_OR, in_be32((void*)GPIO0_OR) | GPIO0_FPGA_FORCEINIT); /* disable PLD IOs */ out_be32((void*)GPIO1_OR, in_be32((void*)GPIO1_OR) | GPIO1_IOEN_N); return 0; }
int main(int argc, char* argv[]) { if (argc < 2) { fprintf(stderr, "Supply data record file \n"); return(1); } long *QRSdelay; QRSdelay = (long *) malloc(sizeof(long)); FILE* frec = fopen(argv[1], "r"); FILE* fout = fopen("delay.txt", "w"); if (frec == NULL) { fprintf(stderr, "could not open the record file %s\n", argv[1]); return(1); } fpga = fpga_open(0); fpga_reset(fpga); long *datum; datum = (long *) malloc(sizeof(long)); int sampleSent, recv; sampleSent = fpga_send(fpga, 0, datum, 2, 0, 1, 0); recv = fpga_recv(fpga, 0, QRSdelay, 2, 0); fscanf(frec, "%ld", datum); long count = 1; while(!feof(frec)) { count++; sampleSent = fpga_send(fpga,0,datum,1, 0, 1, 1000); if (sampleSent < 1) { printf("in loop # %ld, the data sample was not sent", count); break; } recv = fpga_recv(fpga, 0, QRSdelay, 1, 1000); if (recv < 1) { printf("in loop # %ld, the delay output was not received", count); break; } if (*QRSdelay != 0) { fprintf(fout, "%ld, ", *QRSdelay); fprintf(fout, "%ld\n", count); } fscanf(frec, "%ld", datum); } fclose(frec); fclose(fout); fpga_close(fpga); return (0); }
int board_late_init(void) { #if (defined(CONFIG_KM_COGE5UN) | defined(CONFIG_KM_MGCOGE3UN)) u8 dip_switch = kw_gpio_get_value(KM_FLASH_ERASE_ENABLE); /* if pin 1 do full erase */ if (dip_switch != 0) { /* start bootloader */ puts("DIP: Enabled\n"); env_set("actual_bank", "0"); } #endif #if defined(CONFIG_KM_FPGA_CONFIG) wait_for_fpga_config(); fpga_reset(); toggle_eeprom_spi_bus(); #endif return 0; }
int main(int argc, char** argv) { fpga_t * fpga; fpga_info_list info; int option; int i; int id; int chnl; size_t numWords; int sent; int recvd; unsigned int * sendBuffer; unsigned int * recvBuffer; GET_TIME_INIT(3); if (argc < 2) { printf("Usage: %s <option>\n", argv[0]); return -1; } option = atoi(argv[1]); if (option == 0) { // List FPGA info // Populate the fpga_info_list struct if (fpga_list(&info) != 0) { printf("Error populating fpga_info_list\n"); return -1; } printf("Number of devices: %d\n", info.num_fpgas); for (i = 0; i < info.num_fpgas; i++) { printf("%d: id:%d\n", i, info.id[i]); printf("%d: num_chnls:%d\n", i, info.num_chnls[i]); printf("%d: name:%s\n", i, info.name[i]); printf("%d: vendor id:%04X\n", i, info.vendor_id[i]); printf("%d: device id:%04X\n", i, info.device_id[i]); } } else if (option == 1) { // Reset FPGA if (argc < 3) { printf("Usage: %s %d <fpga id>\n", argv[0], option); return -1; } id = atoi(argv[2]); // Get the device with id fpga = fpga_open(id); if (fpga == NULL) { printf("Could not get FPGA %d\n", id); return -1; } // Reset fpga_reset(fpga); // Done with device fpga_close(fpga); } else if (option == 2) { // Send data, receive data if (argc < 5) { printf("Usage: %s %d <fpga id> <chnl> <num words to transfer>\n", argv[0], option); return -1; } id = atoi(argv[2]); chnl = atoi(argv[3]); numWords = atoi(argv[4]); // Get the device with id fpga = fpga_open(id); if (fpga == NULL) { printf("Could not get FPGA %d\n", id); return -1; } // Malloc the arrays sendBuffer = (unsigned int *)malloc(numWords<<2); if (sendBuffer == NULL) { printf("Could not malloc memory for sendBuffer\n"); fpga_close(fpga); return -1; } recvBuffer = (unsigned int *)malloc(numWords<<2); if (recvBuffer == NULL) { printf("Could not malloc memory for recvBuffer\n"); free(sendBuffer); fpga_close(fpga); return -1; } // Initialize the data for (i = 0; i < numWords; i++) { sendBuffer[i] = i+1; recvBuffer[i] = 0; } GET_TIME_VAL(0); // Send the data sent = fpga_send(fpga, chnl, sendBuffer, numWords, 0, 1, 25000); printf("words sent: %d\n", sent); GET_TIME_VAL(1); if (sent != 0) { // Recv the data recvd = fpga_recv(fpga, chnl, recvBuffer, numWords, 25000); printf("words recv: %d\n", recvd); } GET_TIME_VAL(2); // Done with device fpga_close(fpga); // Display some data for (i = 0; i < 20; i++) { printf("recvBuffer[%d]: %d\n", i, recvBuffer[i]); } // Check the data if (recvd != 0) { for (i = 4; i < recvd; i++) { if (recvBuffer[i] != sendBuffer[i]) { printf("recvBuffer[%d]: %d, expected %d\n", i, recvBuffer[i], sendBuffer[i]); break; } } printf("send bw: %f MB/s %fms\n", sent*4.0/1024/1024/((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0))/1000.0), (TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)) ); printf("recv bw: %f MB/s %fms\n", recvd*4.0/1024/1024/((TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1))/1000.0), (TIME_VAL_TO_MS(2) - TIME_VAL_TO_MS(1)) ); } } return 0; }
/* * Handle our "Vendor Extension" commands on endpoint 0. * If we handle this one, return non-zero. */ unsigned char app_vendor_cmd (void) { if (bRequestType == VRT_VENDOR_IN) { ///////////////////////////////// // handle the IN requests ///////////////////////////////// switch (bRequest) { case VRQ_GET_STATUS: //this is no longer done via FX2 -- the FPGA will be queried instead return 0; break; case VRQ_I2C_READ: if (!i2c_read (wValueL, EP0BUF, wLengthL)) return 0; EP0BCH = 0; EP0BCL = wLengthL; break; case VRQ_SPI_READ: return 0; case VRQ_FW_COMPAT: EP0BCH = 0; EP0BCL = 3; break; default: return 0; } } else if (bRequestType == VRT_VENDOR_OUT) { ///////////////////////////////// // handle the OUT requests ///////////////////////////////// switch (bRequest) { case VRQ_SET_LED: switch (wIndexL) { case 0: set_led_0 (wValueL); break; case 1: set_led_1 (wValueL); break; default: return 0; } break; case VRQ_FPGA_LOAD: switch (wIndexL) { // sub-command case FL_BEGIN: return fpga_load_begin (); case FL_XFER: get_ep0_data (); return fpga_load_xfer (EP0BUF, EP0BCL); case FL_END: return fpga_load_end (); default: return 0; } break; case VRQ_FPGA_SET_RESET: fpga_reset(wValueL); break; case VRQ_I2C_WRITE: get_ep0_data (); if (!i2c_write (wValueL, EP0BUF, EP0BCL)) return 0; //SMINI_LED_REG ^= bmLED1; break; case VRQ_RESET_GPIF: clear_fifo(wValueL); break; case VRQ_ENABLE_GPIF: enable_xfers(wValueL); break; case VRQ_CLEAR_FPGA_FIFO: //clear_fpga_data_fifo(); break; default: return 0; } } else return 0; // invalid bRequestType return 1; }
int main(int argc, char** argv) { fpga_t * fpga; fpga_info_list info; int option; int i; int id; int chnl; int ch_size; size_t numWords, numLoops, remWords; int sent; int recvd; int failure = 0; //unsigned int * sendBuffer; //unsigned int * recvBuffer; int err; int idx,jdx,k; GET_TIME_INIT(3); if (argc < 2) { printf("Usage: %s <option>\n", argv[0]); return -1; } option = atoi(argv[1]); if (option == 0) { // List FPGA info // Populate the fpga_info_list struct if (fpga_list(&info) != 0) { printf("Error populating fpga_info_list\n"); return -1; } printf("Number of devices: %d\n", info.num_fpgas); for (i = 0; i < info.num_fpgas; i++) { printf("%d: id:%d\n", i, info.id[i]); printf("%d: num_chnls:%d\n", i, info.num_chnls[i]); printf("%d: name:%s\n", i, info.name[i]); printf("%d: vendor id:%04X\n", i, info.vendor_id[i]); printf("%d: device id:%04X\n", i, info.device_id[i]); } } else if (option == 1) { // Reset FPGA if (argc < 3) { printf("Usage: %s %d <fpga id>\n", argv[0], option); return -1; } id = atoi(argv[2]); // Get the device with id fpga = fpga_open(id); if (fpga == NULL) { printf("Could not get FPGA %d\n", id); return -1; } // Reset fpga_reset(fpga); // Done with device fpga_close(fpga); } else if (option == 2) { // Send data, receive data if (argc < 5) { printf("Usage: %s %d <fpga id> <chnl> <channel size in channel tester in bytes> <num words to transfer>\n", argv[0], option); return -1; } //size_t maxWords, minWords; id = atoi(argv[2]); chnl = atoi(argv[3]); //numWords = atoi(argv[5]); ch_size = atoi(argv[4]); numLoops = 1; //remWords = numWords%ch_size; // Get the device with id fpga = fpga_open(id); //uint64_t result[ch_size]; if (fpga == NULL) { printf("Could not get FPGA %d\n", id); return -1; } k=0; sent_values[0] = 0x8000000000000000; sent_values[1] = 0x0000000000000000; for (idx =2; idx<256; idx=idx+2){ sent_values[idx]=sent_values[idx-2]; sent_values[idx+1]=sent_values[idx-1]; if(sent_values[idx+k-2]==0xffffffffffffffff){ k++; sent_values[idx+k]= 0x8000000000000000; } else sent_values[idx+k] = sent_values[idx+k]|(sent_values[idx+k]/2); } for (idx =0; idx<1024; idx++) sent_values[idx+256]=sent_values[idx]; //for (idx =0; idx<chsize/2; idx=idx+2) // printf("\n%d: %16llx%16llx",idx,sent_values[idx],sent_values[idx+1]); //printf("loops = %d",numLoops); GET_TIME_VAL(0); sent = fpga_send(fpga, chnl, sent_values, ch_size, 0, 1, 25000); recvd = fpga_recv(fpga, chnl, result, ch_size, 25000); GET_TIME_VAL(1); for (k =0; k<ch_size/2; k=k+2) printf("\n%16llx%16llx",result[k],result[k+1]); //for (idx =0; idx<256; idx=idx+2) // printf("\n%16llx%16llx",result[idx],result[idx+1]); printf("\ntime taken (latency) : %f ms, N= %d \n",(TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)),numWords); //printf("avg time taken by 1 set of data : %f ms\n",((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)))/numWords); // Done with device fpga_close(fpga); } else if (option == 3) { // Send data, receive data if (argc < 6) { printf("Usage: %s %d <fpga id> <chnl> <out channel size in channel tester in bytes> <num inputs to transfer>\n", argv[0], option); return -1; } //size_t maxWords, minWords; id = atoi(argv[2]); chnl = atoi(argv[3]); /////numWords: no. words of size 32 bits. ////numInputs: no. of inputs of length 128 bits. int numInputs = atoi(argv[5]); numWords = numInputs*4; ch_size = atoi(argv[4]); numLoops = numWords/ch_size; //remWords = numWords%ch_size; // Get the device with id fpga = fpga_open(id); //uint64_t result[ch_size]; if (fpga == NULL) { printf("Could not get FPGA %d\n", id); return -1; } k=0; sent_values[0] = 0x8000000000000000; sent_values[1] = 0x0000000000000000; for (idx =2; idx<256; idx=idx+2){ sent_values[idx]=sent_values[idx-2]; sent_values[idx+1]=sent_values[idx-1]; if(sent_values[idx+k-2]==0xffffffffffffffff){ k++; sent_values[idx+k]= 0x8000000000000000; } else sent_values[idx+k] = sent_values[idx+k]|(sent_values[idx+k]/2); } for (idx =0; idx<1024; idx++) sent_values[idx+256]=sent_values[idx]; //for (idx =0; idx<128; idx=idx+2) // printf("\n%d: %16llx%16llx",idx,sent_values[idx],sent_values[idx+1]); //printf("loops = %d",numLoops); GET_TIME_VAL(0); for(idx = 0; idx < numLoops; idx++) { sent = fpga_send(fpga, chnl, sent_values, ch_size, 0, 1, 25000); recvd = fpga_recv(fpga, chnl, result, ch_size, 25000); //for (k =0; k<128; k=k+2) // printf("\n%d: %16llx%16llx",k,result[k],result[k+1]); } GET_TIME_VAL(1); //for (idx =0; idx<256; idx=idx+2) // printf("\n%16llx%16llx",result[idx],result[idx+1]); printf("\ntime taken : %f ms, N= %d \n",(TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)),numInputs); printf("avg time taken by 1 set of data : %f ms\n",((TIME_VAL_TO_MS(1) - TIME_VAL_TO_MS(0)))/numInputs); // Done with device fpga_close(fpga); } return 0; }
int do_fpga (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { ulong addr = 0; int i; fpga_t* fpga; if (argc < 2) goto failure; if (strncmp(argv[1], "stat", 4) == 0) { /* status */ if (argc == 2) { for (i = 0; i < fpga_count; i++) { fpga_status (&fpga_list[i]); } } else if (argc == 3) { if ((fpga = fpga_get(argv[2])) == 0) goto failure; fpga_status (fpga); } else goto failure; } else if (strcmp(argv[1],"load") == 0) { /* load */ if (argc == 3 && fpga_count == 1) { fpga = &fpga_list[0]; } else if (argc == 4) { if ((fpga = fpga_get(argv[2])) == 0) goto failure; } else goto failure; addr = simple_strtoul(argv[argc-1], NULL, 16); printf ("FPGA load %s: addr %08lx: ", fpga->name, addr); fpga_load (fpga, addr, 1); } else if (strncmp(argv[1], "rese", 4) == 0) { /* reset */ if (argc == 2 && fpga_count == 1) { fpga = &fpga_list[0]; } else if (argc == 3) { if ((fpga = fpga_get(argv[2])) == 0) goto failure; } else goto failure; printf ("FPGA reset %s: ", fpga->name); if (fpga_reset(fpga)) printf ("ERROR: Timeout\n"); else printf ("done\n"); } else goto failure; return 0; failure: printf ("Usage:\n%s\n", cmdtp->usage); return 1; }
static int fpga_load (fpga_t* fpga, ulong addr, int checkall) { volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base; image_header_t hdr; ulong len, checksum; uchar *data = (uchar *)&hdr; char *s, msg[32]; int verify, i; /* * Check the image header and data of the net-list */ memcpy (&hdr, (char *)addr, sizeof(image_header_t)); if (hdr.ih_magic != IH_MAGIC) { strcpy (msg, "Bad Image Magic Number"); goto failure; } len = sizeof(image_header_t); checksum = hdr.ih_hcrc; hdr.ih_hcrc = 0; if (crc32 (0, data, len) != checksum) { strcpy (msg, "Bad Image Header CRC"); goto failure; } data = (uchar*)(addr + sizeof(image_header_t)); len = hdr.ih_size; s = getenv ("verify"); verify = (s && (*s == 'n')) ? 0 : 1; if (verify) { if (crc32 (0, data, len) != hdr.ih_dcrc) { strcpy (msg, "Bad Image Data CRC"); goto failure; } } if (checkall && fpga_get_version(fpga, hdr.ih_name) < 0) return 1; /* align length */ if (len & 1) ++len; /* * Reset FPGA and wait for completion */ if (fpga_reset(fpga)) { strcpy (msg, "Reset Timeout"); goto failure; } printf ("(%s)... ", hdr.ih_name); /* * Copy data to FPGA */ fpga_control (fpga, FPGA_LOAD_MODE); while (len--) { *fpga_addr = *data++; } fpga_control (fpga, FPGA_READ_MODE); /* * Wait for completion and check error status if timeout */ for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) { udelay (100); if (fpga_control (fpga, FPGA_DONE_IS_HIGH)) break; } if (i == FPGA_LOAD_TIMEOUT) { if (fpga_control(fpga, FPGA_INIT_IS_HIGH)) strcpy(msg, "Invalid Size"); else strcpy(msg, "CRC Error"); goto failure; } printf("done\n"); return 0; failure: printf("ERROR: %s\n", msg); return 1; }
static int fpga_load (fpga_t* fpga, ulong addr, int checkall) { volatile uchar *fpga_addr = (volatile uchar *)fpga->conf_base; image_header_t *hdr = (image_header_t *)addr; ulong len; uchar *data; char msg[32]; int verify, i; #if defined(CONFIG_FIT) if (genimg_get_format ((void *)hdr) != IMAGE_FORMAT_LEGACY) { puts ("Non legacy image format not supported\n"); return -1; } #endif /* * Check the image header and data of the net-list */ if (!image_check_magic (hdr)) { strcpy (msg, "Bad Image Magic Number"); goto failure; } if (!image_check_hcrc (hdr)) { strcpy (msg, "Bad Image Header CRC"); goto failure; } data = (uchar*)image_get_data (hdr); len = image_get_data_size (hdr); verify = getenv_yesno ("verify"); if (verify) { if (!image_check_dcrc (hdr)) { strcpy (msg, "Bad Image Data CRC"); goto failure; } } if (checkall && fpga_get_version(fpga, image_get_name (hdr)) < 0) return 1; /* align length */ if (len & 1) ++len; /* * Reset FPGA and wait for completion */ if (fpga_reset(fpga)) { strcpy (msg, "Reset Timeout"); goto failure; } printf ("(%s)... ", image_get_name (hdr)); /* * Copy data to FPGA */ fpga_control (fpga, FPGA_LOAD_MODE); while (len--) { *fpga_addr = *data++; } fpga_control (fpga, FPGA_READ_MODE); /* * Wait for completion and check error status if timeout */ for (i = 0; i < FPGA_LOAD_TIMEOUT; i++) { udelay (100); if (fpga_control (fpga, FPGA_DONE_IS_HIGH)) break; } if (i == FPGA_LOAD_TIMEOUT) { if (fpga_control(fpga, FPGA_INIT_IS_HIGH)) strcpy(msg, "Invalid Size"); else strcpy(msg, "CRC Error"); goto failure; } printf("done\n"); return 0; failure: printf("ERROR: %s\n", msg); return 1; }
int main(void) { int i, fp_id, num_bytes, pagesize, buf_size, memali; const char *loadfile = "top.bin.ufp"; err_e err, e; void * bp; u_64 val; long long data[2][1024]; char line_in[256]; FILE* file; char* filename; int k; printf("Start program\n"); filename="mas_input_int32.New.txt"; file = fopen(filename, "r"); if (file == NULL) { printf ("ERROR: Could not open input file %s for reading.\n", filename); return(-1); } k=0; while(fgets(line_in, 255, file) != NULL) { sscanf(line_in,"%ld %ld", &data[0][k],&data[1][k]); if(data[0][k]<0) data[0][k]=-1*data[0][k]; if(data[1][k]<0) data[1][k]=-1*data[1][k]; if(k<5) printf("Data read = %d %d %d\n", k, data[0][k], data[1][k]); k++; } // Set FPGA ready fp_id = fpga_open("/dev/ufp0", O_RDWR|O_SYNC, &e); num_bytes = fpga_load(fp_id, loadfile, &err); fpga_reset(fp_id, &e); fpga_start(fp_id, &e); // Set RAMS ready rams[0] = fpga_memmap(fp_id, MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, MEM_OFFSET + 0*MEM_DISTANCE, &e); rams[1] = fpga_memmap(fp_id, MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, MEM_OFFSET + 1*MEM_DISTANCE, &e); rams[2] = fpga_memmap(fp_id, MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, MEM_OFFSET + 2*MEM_DISTANCE, &e); rams[3] = fpga_memmap(fp_id, MEM_SIZE, PROT_READ | PROT_WRITE, MAP_SHARED, MEM_OFFSET + 3*MEM_DISTANCE, &e); // Initalize vectors and input data on rams u_64 word0 = (u_64) data[0][0]; u_64 word1 = (u_64) data[1][0]; u_64 word2 = 0; u_64 *word_0 = rams[0]; u_64 *word_1 = rams[1]; u_64 *word_2 = rams[2]; for( i = 0; i < 128; i++) { *word_0 ++= (u_64) data[0][i]; *word_1 ++= (u_64) data[1][i]; *word_2 ++= 0; } // Set memory for FPGA use pagesize = getpagesize(); buf_size = ((128*1024*1024 + (pagesize - 1)) / pagesize) * pagesize; memali = posix_memalign(&bp, pagesize, buf_size); fpga_register_ftrmem(fp_id, bp, buf_size, &e); ftr_mem = bp; // Setup Mitrion run void * addr = ftr_mem; fpga_wrt_appif_val(fp_id, 0x00000000000000001UL, (0x01*sizeof(u_64)) + 0, TYPE_VAL, &e); fpga_wrt_appif_val(fp_id, 88, ((0x40+1)*sizeof(u_64)), TYPE_VAL, &e); fpga_wrt_appif_val(fp_id, (u_64)addr, (0x40*sizeof(u_64)), TYPE_ADDR, &e); fpga_wrt_appif_val(fp_id, 0x000000000000000000UL, (0x02 * sizeof(u_64)), TYPE_VAL, &e); fpga_wrt_appif_val(fp_id, 0x000000000000000000UL, (0x01 * sizeof(u_64)), TYPE_VAL, &e); // Loop and wait until FPGA calculation is done do { fpga_rd_appif_val(fp_id, (void*)&val, (0x02 * sizeof(u_64)), &e); } while((val&1) == 0); // Print the final result u_64 * word_dst = rams[3]; u_64 wordp = *word_dst; for(i = 0;i < 128; i++) { wordp = *word_dst; word_dst++; printf("FPGA %d: %d + %d = %ld\n", i, data[0][i], data[1][i], wordp); } printf("End of program "); return 0; }