void amd64_supply_native_gregset (struct regcache *regcache, const void *gregs, int regnum) { const char *regs = gregs; struct gdbarch *gdbarch = get_regcache_arch (regcache); int num_regs = amd64_native_gregset64_num_regs; int i; if (gdbarch_ptr_bit (gdbarch) == 32) num_regs = amd64_native_gregset32_num_regs; if (num_regs > gdbarch_num_regs (gdbarch)) num_regs = gdbarch_num_regs (gdbarch); for (i = 0; i < num_regs; i++) { if (regnum == -1 || regnum == i) { int offset = amd64_native_gregset_reg_offset (gdbarch, i); if (offset != -1) regcache_raw_supply (regcache, i, regs + offset); } } }
void legacy_virtual_frame_pointer (struct gdbarch *gdbarch, CORE_ADDR pc, int *frame_regnum, LONGEST *frame_offset) { /* FIXME: cagney/2002-09-13: This code is used when identifying the frame pointer of the current PC. It is assuming that a single register and an offset can determine this. I think it should instead generate a byte code expression as that would work better with things like Dwarf2's CFI. */ if (gdbarch_deprecated_fp_regnum (gdbarch) >= 0 && gdbarch_deprecated_fp_regnum (gdbarch) < gdbarch_num_regs (gdbarch)) *frame_regnum = gdbarch_deprecated_fp_regnum (gdbarch); else if (gdbarch_sp_regnum (gdbarch) >= 0 && gdbarch_sp_regnum (gdbarch) < gdbarch_num_regs (gdbarch)) *frame_regnum = gdbarch_sp_regnum (gdbarch); else /* Should this be an internal error? I guess so, it is reflecting an architectural limitation in the current design. */ internal_error (__FILE__, __LINE__, _("No virtual frame pointer available")); *frame_offset = 0; }
static int gdb_regformat (ClientData clientData, Tcl_Interp *interp, int objc, Tcl_Obj **objv) { int fm, regno, numregs; struct type *type; if (objc != 3) { Tcl_WrongNumArgs (interp, 0, objv, "gdb_reginfo regno type format"); return TCL_ERROR; } if (Tcl_GetIntFromObj (interp, objv[0], ®no) != TCL_OK) return TCL_ERROR; type = (struct type *)strtol (Tcl_GetStringFromObj (objv[1], NULL), NULL, 16); fm = (int)*(Tcl_GetStringFromObj (objv[2], NULL)); numregs = (gdbarch_num_regs (get_current_arch ()) + gdbarch_num_pseudo_regs (get_current_arch ())); if (regno >= numregs) { gdbtk_set_result (interp, "Register number %d too large", regno); return TCL_ERROR; } regformat[regno] = fm; regtype[regno] = type; return TCL_OK; }
static int ia64_cannot_fetch_register (struct gdbarch *gdbarch, int regno) { return regno < 0 || regno >= gdbarch_num_regs (gdbarch) || u_offsets[regno] == -1; }
/* Assemble code to push the value of register number REG on the stack. */ void ax_reg (struct agent_expr *x, int reg) { if (reg >= gdbarch_num_regs (x->gdbarch)) { /* This is a pseudo-register. */ if (!gdbarch_ax_pseudo_register_push_stack_p (x->gdbarch)) error (_("'%s' is a pseudo-register; " "GDB cannot yet trace its contents."), user_reg_map_regnum_to_name (x->gdbarch, reg)); if (gdbarch_ax_pseudo_register_push_stack (x->gdbarch, x, reg)) error (_("Trace '%s' failed."), user_reg_map_regnum_to_name (x->gdbarch, reg)); } else { /* Make sure the register number is in range. */ if (reg < 0 || reg > 0xffff) error (_("GDB bug: ax-general.c (ax_reg): " "register number out of range")); grow_expr (x, 3); x->buf[x->len] = aop_reg; x->buf[x->len + 1] = (reg >> 8) & 0xff; x->buf[x->len + 2] = (reg) & 0xff; x->len += 3; } }
static void ppc_ravenscar_generic_fetch_registers (const struct ravenscar_reg_info *reg_info, struct regcache *regcache, int regnum) { struct gdbarch *gdbarch = get_regcache_arch (regcache); const int sp_regnum = gdbarch_sp_regnum (gdbarch); const int num_regs = gdbarch_num_regs (gdbarch); int current_regnum; CORE_ADDR current_address; CORE_ADDR thread_descriptor_address; /* The tid is the thread_id field, which is a pointer to the thread. */ thread_descriptor_address = (CORE_ADDR) ptid_get_tid (inferior_ptid); /* Read registers. */ for (current_regnum = 0; current_regnum < num_regs; current_regnum++) { if (register_in_thread_descriptor_p (reg_info, current_regnum)) { current_address = thread_descriptor_address + reg_info->context_offsets[current_regnum]; supply_register_at_address (regcache, current_regnum, current_address); } } }
static void gdbsim_store_register (struct target_ops *ops, struct regcache *regcache, int regno) { struct gdbarch *gdbarch = get_regcache_arch (regcache); if (regno == -1) { for (regno = 0; regno < gdbarch_num_regs (gdbarch); regno++) gdbsim_store_register (ops, regcache, regno); return; } else if (gdbarch_register_sim_regno (gdbarch, regno) >= 0) { char tmp[MAX_REGISTER_SIZE]; int nr_bytes; regcache_cooked_read (regcache, regno, tmp); nr_bytes = sim_store_register (gdbsim_desc, gdbarch_register_sim_regno (gdbarch, regno), tmp, register_size (gdbarch, regno)); if (nr_bytes > 0 && nr_bytes != register_size (gdbarch, regno)) internal_error (__FILE__, __LINE__, _("Register size different to expected")); /* FIXME: cagney/2002-05-27: Should check `nr_bytes == 0' indicating that GDB and the SIM have different ideas about which registers are fetchable. */ if (remote_debug) { printf_filtered ("gdbsim_store_register: %d", regno); /* FIXME: We could print something more intelligible. */ dump_mem (tmp, register_size (gdbarch, regno)); } } }
int one2one_register_sim_regno (struct gdbarch *gdbarch, int regnum) { /* Only makes sense to supply raw registers. */ gdb_assert (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch)); return regnum; }
static CORE_ADDR mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store) { CORE_ADDR regaddr; if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) error (_("Bogon register number %d."), regno); if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32) regaddr = regno; else if ((regno >= mips_regnum (gdbarch)->fp0) && (regno < mips_regnum (gdbarch)->fp0 + 32)) regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0); else if (regno == mips_regnum (gdbarch)->pc) regaddr = PC; else if (regno == mips_regnum (gdbarch)->cause) regaddr = store? (CORE_ADDR) -1 : CAUSE; else if (regno == mips_regnum (gdbarch)->badvaddr) regaddr = store? (CORE_ADDR) -1 : BADVADDR; else if (regno == mips_regnum (gdbarch)->lo) regaddr = MMLO; else if (regno == mips_regnum (gdbarch)->hi) regaddr = MMHI; else if (regno == mips_regnum (gdbarch)->fp_control_status) regaddr = FPC_CSR; else if (regno == mips_regnum (gdbarch)->fp_implementation_revision) regaddr = store? (CORE_ADDR) -1 : FPC_EIR; else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM) regaddr = 0; else regaddr = (CORE_ADDR) -1; return regaddr; }
static void fetch_register (struct regcache *regcache, int regno) { struct gdbarch *gdbarch = get_regcache_arch (regcache); int addr[MAX_REGISTER_SIZE]; int nr, isfloat; /* Retrieved values may be -1, so infer errors from errno. */ errno = 0; nr = regmap (gdbarch, regno, &isfloat); /* Floating-point registers. */ if (isfloat) rs6000_ptrace32 (PT_READ_FPR, ptid_get_pid (inferior_ptid), addr, nr, 0); /* Bogus register number. */ else if (nr < 0) { if (regno >= gdbarch_num_regs (gdbarch)) fprintf_unfiltered (gdb_stderr, "gdb error: register no %d not implemented.\n", regno); return; } /* Fixed-point registers. */ else { if (!ARCH64 ()) *addr = rs6000_ptrace32 (PT_READ_GPR, ptid_get_pid (inferior_ptid), (int *) nr, 0, 0); else { /* PT_READ_GPR requires the buffer parameter to point to long long, even if the register is really only 32 bits. */ long long buf; rs6000_ptrace64 (PT_READ_GPR, ptid_get_pid (inferior_ptid), nr, 0, &buf); if (register_size (gdbarch, regno) == 8) memcpy (addr, &buf, 8); else *addr = buf; } } if (!errno) regcache_raw_supply (regcache, regno, (char *) addr); else { #if 0 /* FIXME: this happens 3 times at the start of each 64-bit program. */ perror (_("ptrace read")); #endif errno = 0; } }
static void store_register (struct regcache *regcache, int regno) { struct gdbarch *gdbarch = get_regcache_arch (regcache); int addr[MAX_REGISTER_SIZE]; int nr, isfloat; /* Fetch the register's value from the register cache. */ regcache_raw_collect (regcache, regno, addr); /* -1 can be a successful return value, so infer errors from errno. */ errno = 0; nr = regmap (gdbarch, regno, &isfloat); /* Floating-point registers. */ if (isfloat) rs6000_ptrace32 (PT_WRITE_FPR, ptid_get_pid (inferior_ptid), addr, nr, 0); /* Bogus register number. */ else if (nr < 0) { if (regno >= gdbarch_num_regs (gdbarch)) fprintf_unfiltered (gdb_stderr, "gdb error: register no %d not implemented.\n", regno); } /* Fixed-point registers. */ else { /* The PT_WRITE_GPR operation is rather odd. For 32-bit inferiors, the register's value is passed by value, but for 64-bit inferiors, the address of a buffer containing the value is passed. */ if (!ARCH64 ()) rs6000_ptrace32 (PT_WRITE_GPR, ptid_get_pid (inferior_ptid), (int *) nr, *addr, 0); else { /* PT_WRITE_GPR requires the buffer parameter to point to an 8-byte area, even if the register is really only 32 bits. */ long long buf; if (register_size (gdbarch, regno) == 8) memcpy (&buf, addr, 8); else buf = *addr; rs6000_ptrace64 (PT_WRITE_GPR, ptid_get_pid (inferior_ptid), nr, 0, &buf); } } if (errno) { perror (_("ptrace write")); errno = 0; } }
/* Store register REGNO back into the child process. If REGNO is -1, do this for all registers (including the floating point and SSE registers). */ static void i386_linux_store_inferior_registers (struct target_ops *ops, struct regcache *regcache, int regno) { int tid; /* Use the old method of poking around in `struct user' if the SETREGS request isn't available. */ if (!have_ptrace_getregs) { int i; for (i = 0; i < gdbarch_num_regs (get_regcache_arch (regcache)); i++) if (regno == -1 || regno == i) store_register (regcache, i); return; } /* GNU/Linux LWP ID's are process ID's. */ tid = TIDGET (inferior_ptid); if (tid == 0) tid = PIDGET (inferior_ptid); /* Not a threaded program. */ /* Use the PTRACE_SETFPXREGS requests whenever possible, since it transfers more registers in one system call. But remember that store_fpxregs can fail, and return zero. */ if (regno == -1) { store_regs (regcache, tid, regno); if (store_fpxregs (regcache, tid, regno)) return; store_fpregs (regcache, tid, regno); return; } if (GETREGS_SUPPLIES (regno)) { store_regs (regcache, tid, regno); return; } if (GETFPXREGS_SUPPLIES (regno)) { if (store_fpxregs (regcache, tid, regno)) return; /* Either our processor or our kernel doesn't support the SSE registers, so just write the FP registers in the traditional way. */ store_fpregs (regcache, tid, regno); return; } internal_error (__FILE__, __LINE__, _("Got request to store bad register number %d."), regno); }
static void mips64obsd_sigframe_init (const struct tramp_frame *self, struct frame_info *next_frame, struct trad_frame_cache *cache, CORE_ADDR func) { struct gdbarch *gdbarch = get_frame_arch (next_frame); CORE_ADDR sp, sigcontext_addr, addr; int regnum; /* We find the appropriate instance of `struct sigcontext' at a fixed offset in the signal frame. */ sp = frame_unwind_register_signed (next_frame, MIPS_SP_REGNUM + gdbarch_num_regs (current_gdbarch)); sigcontext_addr = sp + 32; /* PC. */ regnum = mips_regnum (gdbarch)->pc; trad_frame_set_reg_addr (cache, regnum + gdbarch_num_regs (current_gdbarch), sigcontext_addr + 16); /* GPRs. */ for (regnum = MIPS_AT_REGNUM, addr = sigcontext_addr + 32; regnum <= MIPS_RA_REGNUM; regnum++, addr += 8) trad_frame_set_reg_addr (cache, regnum + gdbarch_num_regs (current_gdbarch), addr); /* HI and LO. */ regnum = mips_regnum (gdbarch)->lo; trad_frame_set_reg_addr (cache, regnum + gdbarch_num_regs (current_gdbarch), sigcontext_addr + 280); regnum = mips_regnum (gdbarch)->hi; trad_frame_set_reg_addr (cache, regnum + gdbarch_num_regs (current_gdbarch), sigcontext_addr + 288); /* TODO: Handle the floating-point registers. */ trad_frame_set_id (cache, frame_id_build (sp, func)); }
void amd64_collect_native_gregset (const struct regcache *regcache, void *gregs, int regnum) { char *regs = gregs; struct gdbarch *gdbarch = get_regcache_arch (regcache); int num_regs = amd64_native_gregset64_num_regs; int i; if (gdbarch_ptr_bit (gdbarch) == 32) { num_regs = amd64_native_gregset32_num_regs; /* Make sure %eax, %ebx, %ecx, %edx, %esi, %edi, %ebp, %esp and %eip get zero-extended to 64 bits. */ for (i = 0; i <= I386_EIP_REGNUM; i++) { if (regnum == -1 || regnum == i) memset (regs + amd64_native_gregset_reg_offset (gdbarch, i), 0, 8); } /* Ditto for %cs, %ss, %ds, %es, %fs, and %gs. */ for (i = I386_CS_REGNUM; i <= I386_GS_REGNUM; i++) { if (regnum == -1 || regnum == i) memset (regs + amd64_native_gregset_reg_offset (gdbarch, i), 0, 8); } } if (num_regs > gdbarch_num_regs (gdbarch)) num_regs = gdbarch_num_regs (gdbarch); for (i = 0; i < num_regs; i++) { if (regnum == -1 || regnum == i) { int offset = amd64_native_gregset_reg_offset (gdbarch, i); if (offset != -1) regcache_raw_collect (regcache, i, regs + offset); } } }
void ia64_linux_nat_target::store_registers (struct regcache *regcache, int regnum) { if (regnum == -1) for (regnum = 0; regnum < gdbarch_num_regs (regcache->arch ()); regnum++) ia64_linux_store_register (regcache, regnum); else ia64_linux_store_register (regcache, regnum); }
enum mi_cmd_result mi_cmd_data_list_register_names (char *command, char **argv, int argc) { int regnum, numregs; int i; struct cleanup *cleanup; /* Note that the test for a valid register must include checking the gdbarch_register_name because gdbarch_num_regs may be allocated for the union of the register sets within a family of related processors. In this case, some entries of gdbarch_register_name will change depending upon the particular processor being debugged. */ numregs = gdbarch_num_regs (current_gdbarch) + gdbarch_num_pseudo_regs (current_gdbarch); cleanup = make_cleanup_ui_out_list_begin_end (uiout, "register-names"); if (argc == 0) /* No args, just do all the regs. */ { for (regnum = 0; regnum < numregs; regnum++) { if (gdbarch_register_name (current_gdbarch, regnum) == NULL || *(gdbarch_register_name (current_gdbarch, regnum)) == '\0') ui_out_field_string (uiout, NULL, ""); else ui_out_field_string (uiout, NULL, gdbarch_register_name (current_gdbarch, regnum)); } } /* Else, list of register #s, just do listed regs. */ for (i = 0; i < argc; i++) { regnum = atoi (argv[i]); if (regnum < 0 || regnum >= numregs) { do_cleanups (cleanup); mi_error_message = xstrprintf ("bad register number"); return MI_CMD_ERROR; } if (gdbarch_register_name (current_gdbarch, regnum) == NULL || *(gdbarch_register_name (current_gdbarch, regnum)) == '\0') ui_out_field_string (uiout, NULL, ""); else ui_out_field_string (uiout, NULL, gdbarch_register_name (current_gdbarch, regnum)); } do_cleanups (cleanup); return MI_CMD_DONE; }
static int map_arg_registers (Tcl_Interp *interp, int objc, Tcl_Obj **objv, map_func func, map_arg arg) { int regnum, numregs; /* Note that the test for a valid register must include checking the gdbarch_register_name because gdbarch_num_regs may be allocated for the union of the register sets within a family of related processors. In this case, some entries of gdbarch_register_name will change depending upon the particular processor being debugged. */ numregs = (gdbarch_num_regs (get_current_arch ()) + gdbarch_num_pseudo_regs (get_current_arch ())); if (objc == 0) /* No args, just do all the regs */ { result_ptr->flags |= GDBTK_MAKES_LIST; for (regnum = 0; regnum < numregs; regnum++) { if (gdbarch_register_name (get_current_arch (), regnum) == NULL || *(gdbarch_register_name (get_current_arch (), regnum)) == '\0') continue; func (regnum, arg); } return TCL_OK; } if (objc == 1) if (Tcl_ListObjGetElements (interp, *objv, &objc, &objv ) != TCL_OK) return TCL_ERROR; if (objc > 1) result_ptr->flags |= GDBTK_MAKES_LIST; /* Else, list of register #s, just do listed regs */ for (; objc > 0; objc--, objv++) { if (Tcl_GetIntFromObj (NULL, *objv, ®num) != TCL_OK) { result_ptr->flags |= GDBTK_IN_TCL_RESULT; return TCL_ERROR; } if (regnum >= 0 && regnum < numregs) func (regnum, arg); else { Tcl_SetStringObj (result_ptr->obj_ptr, "bad register number", -1); return TCL_ERROR; } } return TCL_OK; }
static void ia64_linux_store_registers (struct target_ops *ops, struct regcache *regcache, int regnum) { if (regnum == -1) for (regnum = 0; regnum < gdbarch_num_regs (get_regcache_arch (regcache)); regnum++) ia64_linux_store_register (regcache, regnum); else ia64_linux_store_register (regcache, regnum); }
static void hppa_hpux_store_inferior_registers (struct target_ops *ops, struct regcache *regcache, int regnum) { if (regnum == -1) for (regnum = 0; regnum < gdbarch_num_regs (get_regcache_arch (regcache)); regnum++) hppa_hpux_store_register (regcache, regnum); else hppa_hpux_store_register (regcache, regnum); }
static void inf_ptrace_fetch_registers (struct target_ops *ops, struct regcache *regcache, int regnum) { if (regnum == -1) for (regnum = 0; regnum < gdbarch_num_regs (get_regcache_arch (regcache)); regnum++) inf_ptrace_fetch_register (regcache, regnum); else inf_ptrace_fetch_register (regcache, regnum); }
static void mips64_fbsd_sigframe_init (const struct tramp_frame *self, struct frame_info *this_frame, struct trad_frame_cache *cache, CORE_ADDR func) { struct gdbarch *gdbarch = get_frame_arch (this_frame); enum bfd_endian byte_order = gdbarch_byte_order (gdbarch); CORE_ADDR sp, ucontext_addr, addr; int regnum; gdb_byte buf[4]; /* We find the appropriate instance of `ucontext_t' at a fixed offset in the signal frame. */ sp = get_frame_register_signed (this_frame, MIPS_SP_REGNUM + gdbarch_num_regs (gdbarch)); ucontext_addr = sp + N64_SIGFRAME_UCONTEXT_OFFSET; /* PC. */ regnum = mips_regnum (gdbarch)->pc; trad_frame_set_reg_addr (cache, regnum + gdbarch_num_regs (gdbarch), ucontext_addr + N64_UCONTEXT_PC); /* GPRs. */ for (regnum = MIPS_ZERO_REGNUM, addr = ucontext_addr + N64_UCONTEXT_REGS; regnum <= MIPS_RA_REGNUM; regnum++, addr += N64_UCONTEXT_REG_SIZE) trad_frame_set_reg_addr (cache, regnum + gdbarch_num_regs (gdbarch), addr); regnum = MIPS_PS_REGNUM; trad_frame_set_reg_addr (cache, regnum + gdbarch_num_regs (gdbarch), ucontext_addr + N64_UCONTEXT_SR); /* HI and LO. */ regnum = mips_regnum (gdbarch)->lo; trad_frame_set_reg_addr (cache, regnum + gdbarch_num_regs (gdbarch), ucontext_addr + N64_UCONTEXT_LO); regnum = mips_regnum (gdbarch)->hi; trad_frame_set_reg_addr (cache, regnum + gdbarch_num_regs (gdbarch), ucontext_addr + N64_UCONTEXT_HI); if (target_read_memory (ucontext_addr + N64_UCONTEXT_FPUSED, buf, 4) == 0 && extract_unsigned_integer (buf, 4, byte_order) != 0) { for (regnum = 0, addr = ucontext_addr + N64_UCONTEXT_FPREGS; regnum < 32; regnum++, addr += N64_UCONTEXT_REG_SIZE) trad_frame_set_reg_addr (cache, regnum + gdbarch_fp0_regnum (gdbarch), addr); trad_frame_set_reg_addr (cache, mips_regnum (gdbarch)->fp_control_status, addr); } trad_frame_set_id (cache, frame_id_build (sp, func)); }
static void mips_linux_n32n64_sigframe_init (const struct tramp_frame *self, struct frame_info *this_frame, struct trad_frame_cache *this_cache, CORE_ADDR func) { struct gdbarch *gdbarch = get_frame_arch (this_frame); int ireg, reg_position; CORE_ADDR frame_sp = get_frame_sp (this_frame); CORE_ADDR sigcontext_base; const struct mips_regnum *regs = mips_regnum (gdbarch); if (self == &mips_linux_n32_rt_sigframe) sigcontext_base = frame_sp + N32_SIGFRAME_SIGCONTEXT_OFFSET; else sigcontext_base = frame_sp + N64_SIGFRAME_SIGCONTEXT_OFFSET; if (mips_linux_restart_reg_p (gdbarch)) trad_frame_set_reg_addr (this_cache, (MIPS_RESTART_REGNUM + gdbarch_num_regs (gdbarch)), sigcontext_base + N64_SIGCONTEXT_REGS); for (ireg = 1; ireg < 32; ireg++) trad_frame_set_reg_addr (this_cache, ireg + MIPS_ZERO_REGNUM + gdbarch_num_regs (gdbarch), sigcontext_base + N64_SIGCONTEXT_REGS + ireg * N64_SIGCONTEXT_REG_SIZE); for (ireg = 0; ireg < 32; ireg++) trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + gdbarch_num_regs (gdbarch), sigcontext_base + N64_SIGCONTEXT_FPREGS + ireg * N64_SIGCONTEXT_REG_SIZE); trad_frame_set_reg_addr (this_cache, regs->pc + gdbarch_num_regs (gdbarch), sigcontext_base + N64_SIGCONTEXT_PC); trad_frame_set_reg_addr (this_cache, regs->fp_control_status + gdbarch_num_regs (gdbarch), sigcontext_base + N64_SIGCONTEXT_FPCSR); trad_frame_set_reg_addr (this_cache, regs->hi + gdbarch_num_regs (gdbarch), sigcontext_base + N64_SIGCONTEXT_HI); trad_frame_set_reg_addr (this_cache, regs->lo + gdbarch_num_regs (gdbarch), sigcontext_base + N64_SIGCONTEXT_LO); /* Choice of the bottom of the sigframe is somewhat arbitrary. */ trad_frame_set_id (this_cache, frame_id_build (frame_sp, func)); }
static void inf_child_fetch_inferior_registers (struct regcache *regcache, int regnum) { if (regnum == -1) { for (regnum = 0; regnum < gdbarch_num_regs (get_regcache_arch (regcache)); regnum++) regcache_raw_supply (regcache, regnum, NULL); } else regcache_raw_supply (regcache, regnum, NULL); }
static int amd64_native_gregset_reg_offset (struct gdbarch *gdbarch, int regnum) { int *reg_offset = amd64_native_gregset64_reg_offset; int num_regs = amd64_native_gregset64_num_regs; gdb_assert (regnum >= 0); if (gdbarch_ptr_bit (gdbarch) == 32) { reg_offset = amd64_native_gregset32_reg_offset; num_regs = amd64_native_gregset32_num_regs; } if (num_regs > gdbarch_num_regs (gdbarch)) num_regs = gdbarch_num_regs (gdbarch); if (regnum < num_regs && regnum < gdbarch_num_regs (gdbarch)) return reg_offset[regnum]; return -1; }
static struct lm32_frame_cache * lm32_frame_cache (struct frame_info *this_frame, void **this_prologue_cache) { CORE_ADDR prologue_pc; CORE_ADDR current_pc; ULONGEST prev_sp; ULONGEST this_base; struct lm32_frame_cache *info; int prefixed; unsigned long instruction; int op; int offsets[32]; int i; long immediate; if ((*this_prologue_cache)) return (*this_prologue_cache); info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache); (*this_prologue_cache) = info; info->saved_regs = trad_frame_alloc_saved_regs (this_frame); info->pc = get_frame_func (this_frame); current_pc = get_frame_pc (this_frame); lm32_analyze_prologue (get_frame_arch (this_frame), info->pc, current_pc, info); /* Compute the frame's base, and the previous frame's SP. */ this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM); prev_sp = this_base + info->size; info->base = this_base; /* Convert callee save offsets into addresses. */ for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++) { if (trad_frame_addr_p (info->saved_regs, i)) info->saved_regs[i].addr = this_base + info->saved_regs[i].addr; } /* The call instruction moves the caller's PC in the callee's RA register. Since this is an unwind, do the reverse. Copy the location of RA register into PC (the address / regnum) so that a request for PC will be converted into a request for the RA register. */ info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM]; /* The previous frame's SP needed to be computed. Save the computed value. */ trad_frame_set_value (info->saved_regs, SIM_LM32_SP_REGNUM, prev_sp); return info; }
void supply_gregset (struct regcache *regcache, const elf_gregset_t *gregsetp) { const elf_greg_t *regp = (const elf_greg_t *) gregsetp; int i; for (i = 0; i < I386_NUM_GREGS; i++) regcache_raw_supply (regcache, i, regp + regmap[i]); if (I386_LINUX_ORIG_EAX_REGNUM < gdbarch_num_regs (get_regcache_arch (regcache))) regcache_raw_supply (regcache, I386_LINUX_ORIG_EAX_REGNUM, regp + ORIG_EAX); }
/* Implement the "init" routine in struct tramp_frame for the N32 ABI on mips-irix. */ static void mips_irix_n32_tramp_frame_init (const struct tramp_frame *self, struct frame_info *this_frame, struct trad_frame_cache *this_cache, CORE_ADDR func) { struct gdbarch *gdbarch = get_frame_arch (this_frame); const int num_regs = gdbarch_num_regs (gdbarch); int sp_cooked_regno = num_regs + MIPS_SP_REGNUM; const CORE_ADDR sp = get_frame_register_signed (this_frame, sp_cooked_regno); const CORE_ADDR sigcontext_base = sp + 48; const struct mips_regnum *regs = mips_regnum (gdbarch); int ireg; trad_frame_set_reg_addr (this_cache, regs->pc + gdbarch_num_regs (gdbarch), sigcontext_base + SIGCONTEXT_PC_OFF); for (ireg = 1; ireg < 32; ireg++) trad_frame_set_reg_addr (this_cache, ireg + MIPS_ZERO_REGNUM + num_regs, sigcontext_base + SIGCONTEXT_REGS_OFF + ireg * 8); for (ireg = 0; ireg < 32; ireg++) trad_frame_set_reg_addr (this_cache, ireg + regs->fp0 + num_regs, sigcontext_base + SIGCONTEXT_FPREGS_OFF + ireg * 8); trad_frame_set_reg_addr (this_cache, regs->fp_control_status + num_regs, sigcontext_base + SIGCONTEXT_FPCSR_OFF); trad_frame_set_reg_addr (this_cache, regs->hi + num_regs, sigcontext_base + SIGCONTEXT_HI_OFF); trad_frame_set_reg_addr (this_cache, regs->lo + num_regs, sigcontext_base + SIGCONTEXT_LO_OFF); trad_frame_set_id (this_cache, frame_id_build (sigcontext_base, func)); }
static void fetch_core_registers (struct regcache *regcache, char *core_reg_sect, unsigned core_reg_size, int which, CORE_ADDR reg_addr) { char *srcp = core_reg_sect; struct gdbarch *gdbarch = get_regcache_arch (regcache); int regsize = mips_isa_regsize (gdbarch); int regno; /* If regsize is 8, this is a N32 or N64 core file. If regsize is 4, this is an O32 core file. */ if (core_reg_size != regsize * gdbarch_num_regs (gdbarch)) { warning (_("wrong size gregset struct in core file")); return; } for (regno = 0; regno < gdbarch_num_regs (gdbarch); regno++) { regcache_raw_supply (regcache, regno, srcp); srcp += regsize; } }
static CORE_ADDR ia64_register_addr (struct gdbarch *gdbarch, int regno) { CORE_ADDR addr; if (regno < 0 || regno >= gdbarch_num_regs (gdbarch)) error (_("Invalid register number %d."), regno); if (u_offsets[regno] == -1) addr = 0; else addr = (CORE_ADDR) u_offsets[regno]; return addr; }
void supply_gregset (struct regcache *regcache, const elf_gregset_t *gregsetp) { const gdb_byte *regp = (const gdb_byte *) gregsetp; int i; for (i = 0; i < I386_NUM_GREGS; i++) regcache_raw_supply (regcache, i, regp + i386_linux_gregset_reg_offset[i]); if (I386_LINUX_ORIG_EAX_REGNUM < gdbarch_num_regs (get_regcache_arch (regcache))) regcache_raw_supply (regcache, I386_LINUX_ORIG_EAX_REGNUM, regp + i386_linux_gregset_reg_offset[I386_LINUX_ORIG_EAX_REGNUM]); }