static int __init alchemy_gpiolib_init(void) { gpiochip_add(&alchemy_gpio_chip[0]); if (alchemy_get_cputype() != ALCHEMY_CPU_AU1000) gpiochip_add(&alchemy_gpio_chip[1]); return 0; }
static int vprbrd_gpio_probe(struct platform_device *pdev) { struct vprbrd *vb = dev_get_drvdata(pdev->dev.parent); struct vprbrd_gpio *vb_gpio; int ret; vb_gpio = devm_kzalloc(&pdev->dev, sizeof(*vb_gpio), GFP_KERNEL); if (vb_gpio == NULL) return -ENOMEM; vb_gpio->vb = vb; /* registering gpio a */ vb_gpio->gpioa.label = "viperboard gpio a"; vb_gpio->gpioa.dev = &pdev->dev; vb_gpio->gpioa.owner = THIS_MODULE; vb_gpio->gpioa.base = -1; vb_gpio->gpioa.ngpio = 16; vb_gpio->gpioa.can_sleep = 1; vb_gpio->gpioa.set = vprbrd_gpioa_set; vb_gpio->gpioa.get = vprbrd_gpioa_get; vb_gpio->gpioa.direction_input = vprbrd_gpioa_direction_input; vb_gpio->gpioa.direction_output = vprbrd_gpioa_direction_output; ret = gpiochip_add(&vb_gpio->gpioa); if (ret < 0) { dev_err(vb_gpio->gpioa.dev, "could not add gpio a"); goto err_gpioa; } /* registering gpio b */ vb_gpio->gpiob.label = "viperboard gpio b"; vb_gpio->gpiob.dev = &pdev->dev; vb_gpio->gpiob.owner = THIS_MODULE; vb_gpio->gpiob.base = -1; vb_gpio->gpiob.ngpio = 16; vb_gpio->gpiob.can_sleep = 1; vb_gpio->gpiob.set = vprbrd_gpiob_set; vb_gpio->gpiob.get = vprbrd_gpiob_get; vb_gpio->gpiob.direction_input = vprbrd_gpiob_direction_input; vb_gpio->gpiob.direction_output = vprbrd_gpiob_direction_output; ret = gpiochip_add(&vb_gpio->gpiob); if (ret < 0) { dev_err(vb_gpio->gpiob.dev, "could not add gpio b"); goto err_gpiob; } platform_set_drvdata(pdev, vb_gpio); return ret; err_gpiob: if (gpiochip_remove(&vb_gpio->gpioa)) dev_err(&pdev->dev, "%s gpiochip_remove failed\n", __func__); err_gpioa: return ret; }
static int __init mcf_gpio_init(void) { unsigned i = 0; while (i < ARRAY_SIZE(mcf_gpio_chips)) (void)gpiochip_add((struct gpio_chip *)&mcf_gpio_chips[i++]); return 0; }
void __init sa1100_init_gpio(void) { /* clear all GPIO edge detects */ GFER = 0; GRER = 0; GEDR = -1; gpiochip_add(&sa1100_gpio_chip); sa1100_gpio_irqdomain = irq_domain_add_simple(NULL, 28, IRQ_GPIO0, &sa1100_gpio_irqdomain_ops, NULL); /* * Install handlers for GPIO 0-10 edge detect interrupts */ irq_set_chained_handler(IRQ_GPIO0_SC, sa1100_gpio_handler); irq_set_chained_handler(IRQ_GPIO1_SC, sa1100_gpio_handler); irq_set_chained_handler(IRQ_GPIO2_SC, sa1100_gpio_handler); irq_set_chained_handler(IRQ_GPIO3_SC, sa1100_gpio_handler); irq_set_chained_handler(IRQ_GPIO4_SC, sa1100_gpio_handler); irq_set_chained_handler(IRQ_GPIO5_SC, sa1100_gpio_handler); irq_set_chained_handler(IRQ_GPIO6_SC, sa1100_gpio_handler); irq_set_chained_handler(IRQ_GPIO7_SC, sa1100_gpio_handler); irq_set_chained_handler(IRQ_GPIO8_SC, sa1100_gpio_handler); irq_set_chained_handler(IRQ_GPIO9_SC, sa1100_gpio_handler); irq_set_chained_handler(IRQ_GPIO10_SC, sa1100_gpio_handler); /* * Install handler for GPIO 11-27 edge detect interrupts */ irq_set_chained_handler(IRQ_GPIO11_27, sa1100_gpio_handler); }
static void __init samsung_gpiolib_add(struct samsung_gpio_chip *chip) { struct gpio_chip *gc = &chip->chip; int ret; BUG_ON(!chip->base); BUG_ON(!gc->label); BUG_ON(!gc->ngpio); spin_lock_init(&chip->lock); if (!gc->direction_input) gc->direction_input = samsung_gpiolib_2bit_input; if (!gc->direction_output) gc->direction_output = samsung_gpiolib_2bit_output; if (!gc->set) gc->set = samsung_gpiolib_set; if (!gc->get) gc->get = samsung_gpiolib_get; #ifdef CONFIG_PM if (chip->pm != NULL) { if (!chip->pm->save || !chip->pm->resume) pr_err("gpio: %s has missing PM functions\n", gc->label); } else pr_err("gpio: %s has no PM function\n", gc->label); #endif /* gpiochip_add() prints own failure message on error. */ ret = gpiochip_add(gc); if (ret >= 0) s3c_gpiolib_track(chip); }
/** * of_mm_gpiochip_add - Add memory mapped GPIO chip (bank) * @np: device node of the GPIO chip * @mm_gc: pointer to the of_mm_gpio_chip allocated structure * * To use this function you should allocate and fill mm_gc with: * * 1) In the gpio_chip structure: * - all the callbacks * - of_gpio_n_cells * - of_xlate callback (optional) * * 3) In the of_mm_gpio_chip structure: * - save_regs callback (optional) * * If succeeded, this function will map bank's memory and will * do all necessary work for you. Then you'll able to use .regs * to manage GPIOs from the callbacks. */ int of_mm_gpiochip_add(struct device_node *np, struct of_mm_gpio_chip *mm_gc) { int ret = -ENOMEM; struct gpio_chip *gc = &mm_gc->gc; gc->label = kstrdup(np->full_name, GFP_KERNEL); if (!gc->label) goto err0; mm_gc->regs = of_iomap(np, 0); if (!mm_gc->regs) goto err1; gc->base = -1; if (mm_gc->save_regs) mm_gc->save_regs(mm_gc); mm_gc->gc.of_node = np; ret = gpiochip_add(gc); if (ret) goto err2; return 0; err2: iounmap(mm_gc->regs); err1: kfree(gc->label); err0: pr_err("%s: GPIO chip registration failed with status %d\n", np->full_name, ret); return ret; }
static int __init msm_init_gpio(void) { int i, j = 0; for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { if (i - FIRST_GPIO_IRQ >= msm_gpio_chips[j].chip.base + msm_gpio_chips[j].chip.ngpio) j++; set_irq_chip_data(i, &msm_gpio_chips[j]); set_irq_chip(i, &msm_gpio_irq_chip); set_irq_handler(i, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { spin_lock_init(&msm_gpio_chips[i].lock); __raw_writel(0, msm_gpio_chips[i].regs.int_en); gpiochip_add(&msm_gpio_chips[i].chip); } mb(); set_irq_wake(INT_GPIO_GROUP1, 1); set_irq_wake(INT_GPIO_GROUP2, 2); proc_create_data("gdump", 0, NULL, &gdump_proc_fops, NULL); msm_gpio_buf = kzalloc(512, GFP_KERNEL); return 0; }
static int __init msm_init_gpio(void) { int i, j = 0; for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { if (i - FIRST_GPIO_IRQ >= msm_gpio_chips[j].chip.base + msm_gpio_chips[j].chip.ngpio) j++; set_irq_chip_data(i, &msm_gpio_chips[j]); set_irq_chip(i, &msm_gpio_irq_chip); set_irq_handler(i, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { spin_lock_init(&msm_gpio_chips[i].lock); writel(0, msm_gpio_chips[i].regs.int_en); gpiochip_add(&msm_gpio_chips[i].chip); } set_irq_chained_handler(INT_GPIO_GROUP1, msm_gpio_irq_handler); set_irq_chained_handler(INT_GPIO_GROUP2, msm_gpio_irq_handler); set_irq_wake(INT_GPIO_GROUP1, 1); set_irq_wake(INT_GPIO_GROUP2, 2); return 0; }
void __init ath79_gpio_init(void) { int err; if (soc_is_ar71xx()) ath79_gpio_count = AR71XX_GPIO_COUNT; else if (soc_is_ar7240()) ath79_gpio_count = AR7240_GPIO_COUNT; else if (soc_is_ar7241() || soc_is_ar7242()) ath79_gpio_count = AR7241_GPIO_COUNT; else if (soc_is_ar913x()) ath79_gpio_count = AR913X_GPIO_COUNT; else if (soc_is_ar933x()) ath79_gpio_count = AR933X_GPIO_COUNT; else if (soc_is_ar934x()) ath79_gpio_count = AR934X_GPIO_COUNT; else if (soc_is_qca955x()) ath79_gpio_count = QCA955X_GPIO_COUNT; else BUG(); ath79_gpio_base = ioremap_nocache(AR71XX_GPIO_BASE, AR71XX_GPIO_SIZE); ath79_gpio_chip.ngpio = ath79_gpio_count; if (soc_is_ar934x() || soc_is_qca955x()) { ath79_gpio_chip.direction_input = ar934x_gpio_direction_input; ath79_gpio_chip.direction_output = ar934x_gpio_direction_output; } err = gpiochip_add(&ath79_gpio_chip); if (err) panic("cannot add AR71xx GPIO chip, error=%d", err); }
/* * Called from the processor-specific init to enable GPIO pin support. */ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) { unsigned i; struct at91_gpio_chip *at91_gpio, *last = NULL; BUG_ON(nr_banks > MAX_GPIO_BANKS); if (of_have_populated_dt()) return; for (i = 0; i < nr_banks; i++) at91_gpio_init_one(i, data[i].regbase, data[i].id); for (i = 0; i < gpio_banks; i++) { at91_gpio = &gpio_chip[i]; /* * GPIO controller are grouped on some SoC: * PIOC, PIOD and PIOE can share the same IRQ line */ if (last && last->pioc_hwirq == at91_gpio->pioc_hwirq) last->next = at91_gpio; last = at91_gpio; gpiochip_add(&at91_gpio->chip); } }
void tps65910_gpio_init(struct tps65910 *tps65910, int gpio_base) { int ret; if (!gpio_base) return; tps65910->gpio.owner = THIS_MODULE; tps65910->gpio.label = tps65910->i2c_client->name; tps65910->gpio.dev = tps65910->dev; tps65910->gpio.base = gpio_base; switch(tps65910_chip_id(tps65910)) { case TPS65910: tps65910->gpio.ngpio = 6; break; case TPS65911: tps65910->gpio.ngpio = 9; break; default: return; } tps65910->gpio.can_sleep = 1; tps65910->gpio.direction_input = tps65910_gpio_input; tps65910->gpio.direction_output = tps65910_gpio_output; tps65910->gpio.set = tps65910_gpio_set; tps65910->gpio.get = tps65910_gpio_get; ret = gpiochip_add(&tps65910->gpio); if (ret) dev_warn(tps65910->dev, "GPIO registration failed: %d\n", ret); }
static int dc_gpiochip_add(struct dc_pinmap *pmap, struct device_node *np) { struct gpio_chip *chip = &pmap->chip; int ret; chip->label = DRIVER_NAME; chip->dev = pmap->dev; chip->request = gpiochip_generic_request; chip->free = gpiochip_generic_free; chip->direction_input = dc_gpio_direction_input; chip->direction_output = dc_gpio_direction_output; chip->get = dc_gpio_get; chip->set = dc_gpio_set; chip->base = -1; chip->ngpio = PINS_COUNT; chip->of_node = np; chip->of_gpio_n_cells = 2; spin_lock_init(&pmap->lock); ret = gpiochip_add(chip); if (ret < 0) return ret; ret = gpiochip_add_pin_range(chip, dev_name(pmap->dev), 0, 0, PINS_COUNT); if (ret < 0) { gpiochip_remove(chip); return ret; } return 0; }
static int platform_msic_gpio_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct intel_msic_gpio_pdata *pdata = dev_get_platdata(dev); struct msic_gpio *mg; int irq = platform_get_irq(pdev, 0); int retval; int i; if (irq < 0) { dev_err(dev, "no IRQ line\n"); return -EINVAL; } if (!pdata || !pdata->gpio_base) { dev_err(dev, "incorrect or missing platform data\n"); return -EINVAL; } mg = kzalloc(sizeof(*mg), GFP_KERNEL); if (!mg) return -ENOMEM; dev_set_drvdata(dev, mg); mg->pdev = pdev; mg->irq = irq; mg->irq_base = pdata->gpio_base + MSIC_GPIO_IRQ_OFFSET; mg->chip.label = "msic_gpio"; mg->chip.direction_input = msic_gpio_direction_input; mg->chip.direction_output = msic_gpio_direction_output; mg->chip.get = msic_gpio_get; mg->chip.set = msic_gpio_set; mg->chip.to_irq = msic_gpio_to_irq; mg->chip.base = pdata->gpio_base; mg->chip.ngpio = MSIC_NUM_GPIO; mg->chip.can_sleep = true; mg->chip.parent = dev; mutex_init(&mg->buslock); retval = gpiochip_add(&mg->chip); if (retval) { dev_err(dev, "Adding MSIC gpio chip failed\n"); goto err; } for (i = 0; i < mg->chip.ngpio; i++) { irq_set_chip_data(i + mg->irq_base, mg); irq_set_chip_and_handler(i + mg->irq_base, &msic_irqchip, handle_simple_irq); } irq_set_chained_handler_and_data(mg->irq, msic_gpio_irq_handler, mg); return 0; err: kfree(mg); return retval; }
static int __devinit ad7879_gpio_add(struct device *dev) { struct ad7879 *ts = dev_get_drvdata(dev); struct ad7879_platform_data *pdata = dev->platform_data; int ret = 0; if (pdata->gpio_export) { ts->gc.direction_input = ad7879_gpio_direction_input; ts->gc.direction_output = ad7879_gpio_direction_output; ts->gc.get = ad7879_gpio_get_value; ts->gc.set = ad7879_gpio_set_value; ts->gc.can_sleep = 1; ts->gc.base = pdata->gpio_base; ts->gc.ngpio = 1; ts->gc.label = "AD7879-GPIO"; ts->gc.owner = THIS_MODULE; ts->gc.dev = dev; ret = gpiochip_add(&ts->gc); if (ret) dev_err(dev, "failed to register gpio %d\n", ts->gc.base); } return ret; }
static int spics_gpio_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct spear_spics *spics; struct resource *res; int ret; spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL); if (!spics) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); spics->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(spics->base)) return PTR_ERR(spics->base); if (of_property_read_u32(np, "st-spics,peripcfg-reg", &spics->perip_cfg)) goto err_dt_data; if (of_property_read_u32(np, "st-spics,sw-enable-bit", &spics->sw_enable_bit)) goto err_dt_data; if (of_property_read_u32(np, "st-spics,cs-value-bit", &spics->cs_value_bit)) goto err_dt_data; if (of_property_read_u32(np, "st-spics,cs-enable-mask", &spics->cs_enable_mask)) goto err_dt_data; if (of_property_read_u32(np, "st-spics,cs-enable-shift", &spics->cs_enable_shift)) goto err_dt_data; platform_set_drvdata(pdev, spics); spics->chip.ngpio = NUM_OF_GPIO; spics->chip.base = -1; spics->chip.request = spics_request; spics->chip.free = spics_free; spics->chip.direction_input = spics_direction_input; spics->chip.direction_output = spics_direction_output; spics->chip.get = spics_get_value; spics->chip.set = spics_set_value; spics->chip.label = dev_name(&pdev->dev); spics->chip.dev = &pdev->dev; spics->chip.owner = THIS_MODULE; spics->last_off = -1; ret = gpiochip_add(&spics->chip); if (ret) { dev_err(&pdev->dev, "unable to add gpio chip\n"); return ret; } dev_info(&pdev->dev, "spear spics registered\n"); return 0; err_dt_data: dev_err(&pdev->dev, "DT probe failed\n"); return -EINVAL; }
static int __init simpad_init(void) { int ret; spin_lock_init(&cs3_lock); cs3_gpio.label = "simpad_cs3"; cs3_gpio.base = SIMPAD_CS3_GPIO_BASE; cs3_gpio.ngpio = 24; cs3_gpio.set = cs3_gpio_set; cs3_gpio.get = cs3_gpio_get; cs3_gpio.direction_input = cs3_gpio_direction_input; cs3_gpio.direction_output = cs3_gpio_direction_output; ret = gpiochip_add(&cs3_gpio); if (ret) printk(KERN_WARNING "simpad: Unable to register cs3 GPIO device"); pm_power_off = simpad_power_off; sa11x0_ppc_configure_mcp(); sa11x0_register_mtd(&simpad_flash_data, simpad_flash_resources, ARRAY_SIZE(simpad_flash_resources)); sa11x0_register_mcp(&simpad_mcp_data); ret = platform_add_devices(devices, ARRAY_SIZE(devices)); if(ret) printk(KERN_WARNING "simpad: Unable to register mq200 framebuffer device"); return 0; }
static int add_children(struct i2c_client *client) { static const struct { int offset; char *label; } config_inputs[] = { { 8 + 0, "sw6_1", }, { 8 + 1, "sw6_2", }, { 8 + 2, "sw6_3", }, { 8 + 3, "sw6_4", }, { 8 + 4, "NTSC/nPAL", }, }; struct device *child; int status; int i; dm355evm_msp_gpio.dev = &client->dev; status = gpiochip_add(&dm355evm_msp_gpio); if (status < 0) return status; if (msp_has_leds()) { #define GPIO_LED(l) .name = l, .active_low = true static struct gpio_led evm_leds[] = { { GPIO_LED("dm355evm::ds14"), .default_trigger = "heartbeat", }, { GPIO_LED("dm355evm::ds15"),
int pio2_gpio_init(struct pio2_card *card) { int retval = 0; char *label; label = kmalloc(PIO2_NUM_CHANNELS, GFP_KERNEL); if (label == NULL) return -ENOMEM; sprintf(label, "%s@%s", driver_name, dev_name(&card->vdev->dev)); card->gc.label = label; card->gc.ngpio = PIO2_NUM_CHANNELS; /* Dynamic allocation of base */ card->gc.base = -1; /* Setup pointers to chip functions */ card->gc.direction_input = pio2_gpio_dir_in; card->gc.direction_output = pio2_gpio_dir_out; card->gc.get = pio2_gpio_get; card->gc.set = pio2_gpio_set; /* This function adds a memory mapped GPIO chip */ retval = gpiochip_add(&(card->gc)); if (retval) { dev_err(&card->vdev->dev, "Unable to register GPIO\n"); kfree(card->gc.label); } return retval; };
static int ad7879_gpio_add(struct ad7879 *ts, const struct ad7879_platform_data *pdata) { int ret = 0; mutex_init(&ts->mutex); if (pdata->gpio_export) { ts->gc.direction_input = ad7879_gpio_direction_input; ts->gc.direction_output = ad7879_gpio_direction_output; ts->gc.get = ad7879_gpio_get_value; ts->gc.set = ad7879_gpio_set_value; ts->gc.can_sleep = 1; ts->gc.base = pdata->gpio_base; ts->gc.ngpio = 1; ts->gc.label = "AD7879-GPIO"; ts->gc.owner = THIS_MODULE; ts->gc.dev = ts->dev; ret = gpiochip_add(&ts->gc); if (ret) dev_err(ts->dev, "failed to register gpio %d\n", ts->gc.base); } return ret; }
int __init bcm63xx_gpio_init(void) { bcm63xx_gpio_chip.ngpio = bcm63xx_gpio_count(); pr_info("registering %d GPIOs\n", bcm63xx_gpio_chip.ngpio); return gpiochip_add(&bcm63xx_gpio_chip); }
static int gpo_twl6040_probe(struct platform_device *pdev) { struct device *twl6040_core_dev = pdev->dev.parent; struct twl6040 *twl6040 = dev_get_drvdata(twl6040_core_dev); int ret; twl6040gpo_chip.base = -1; if (twl6040_get_revid(twl6040) < TWL6041_REV_ES2_0) twl6040gpo_chip.ngpio = 3; /* twl6040 have 3 GPO */ else twl6040gpo_chip.ngpio = 1; /* twl6041 have 1 GPO */ twl6040gpo_chip.dev = &pdev->dev; #ifdef CONFIG_OF_GPIO twl6040gpo_chip.of_node = twl6040_core_dev->of_node; #endif ret = gpiochip_add(&twl6040gpo_chip); if (ret < 0) { dev_err(&pdev->dev, "could not register gpiochip, %d\n", ret); twl6040gpo_chip.ngpio = 0; } return ret; }
/* * Called from the processor-specific init to enable GPIO pin support. */ void __init at91_gpio_init(struct at91_gpio_bank *data, int nr_banks) { unsigned i; struct at91_gpio_chip *at91_gpio, *last = NULL; BUG_ON(nr_banks > MAX_GPIO_BANKS); gpio_banks = nr_banks; for (i = 0; i < nr_banks; i++) { at91_gpio = &gpio_chip[i]; at91_gpio->bank = &data[i]; at91_gpio->chip.base = PIN_BASE + i * 32; at91_gpio->regbase = at91_gpio->bank->offset + (void __iomem *)AT91_VA_BASE_SYS; #ifdef CONFIG_IPIPE at91_gpio->nonroot_gpios = &at91_gpio->nonroot_gpios_storage; #endif /* enable PIO controller's clock */ clk_enable(at91_gpio->bank->clock); /* AT91SAM9263_ID_PIOCDE groups PIOC, PIOD, PIOE */ if (last && last->bank->id == at91_gpio->bank->id) { last->next = at91_gpio; #ifdef CONFIG_IPIPE at91_gpio->nonroot_gpios = last->nonroot_gpios; #endif } last = at91_gpio; gpiochip_add(&at91_gpio->chip); } }
static int ucb1400_gpio_probe(struct platform_device *dev) { struct ucb1400_gpio *ucb = dev->dev.platform_data; int err = 0; if (!(ucbdata && ucbdata->gpio_offset)) { err = -EINVAL; goto err; } platform_set_drvdata(dev, ucb); ucb->gc.label = "ucb1400_gpio"; ucb->gc.base = ucbdata->gpio_offset; ucb->gc.ngpio = 10; ucb->gc.owner = THIS_MODULE; ucb->gc.direction_input = ucb1400_gpio_dir_in; ucb->gc.direction_output = ucb1400_gpio_dir_out; ucb->gc.get = ucb1400_gpio_get; ucb->gc.set = ucb1400_gpio_set; ucb->gc.can_sleep = 1; err = gpiochip_add(&ucb->gc); if (err) goto err; if (ucbdata && ucbdata->gpio_setup) err = ucbdata->gpio_setup(&dev->dev, ucb->gc.ngpio); err: return err; }
static int __devinit msm_gpio_probe(struct platform_device *dev) { int i, j = 0; int grp_irq; for (i = FIRST_GPIO_IRQ; i < FIRST_GPIO_IRQ + NR_GPIO_IRQS; i++) { if (i - FIRST_GPIO_IRQ >= msm_gpio_chips[j].chip.base + msm_gpio_chips[j].chip.ngpio) j++; irq_set_chip_data(i, &msm_gpio_chips[j]); irq_set_chip_and_handler(i, &msm_gpio_irq_chip, handle_edge_irq); set_irq_flags(i, IRQF_VALID); } for (i = 0; i < dev->num_resources; i++) { grp_irq = platform_get_irq(dev, i); if (grp_irq < 0) return -ENXIO; irq_set_chained_handler(grp_irq, msm_gpio_irq_handler); irq_set_irq_wake(grp_irq, (i + 1)); } for (i = 0; i < ARRAY_SIZE(msm_gpio_chips); i++) { spin_lock_init(&msm_gpio_chips[i].lock); __raw_writel(0, msm_gpio_chips[i].regs.int_en); gpiochip_add(&msm_gpio_chips[i].chip); } mb(); return 0; }
void __init ixp4xx_sys_init(void) { ixp4xx_exp_bus_size = SZ_16M; platform_add_devices(ixp4xx_devices, ARRAY_SIZE(ixp4xx_devices)); gpiochip_add(&ixp4xx_gpio_chip); if (cpu_is_ixp46x()) { int region; platform_add_devices(ixp46x_devices, ARRAY_SIZE(ixp46x_devices)); for (region = 0; region < 7; region++) { if((*(IXP4XX_EXP_REG(0x4 * region)) & 0x200)) { ixp4xx_exp_bus_size = SZ_32M; break; } } } printk("IXP4xx: Using %luMiB expansion bus window size\n", ixp4xx_exp_bus_size >> 20); }
static int __devinit palmas_gpio_probe(struct platform_device *pdev) { struct palmas *palmas = dev_get_drvdata(pdev->dev.parent); struct palmas_platform_data *pdata = palmas->dev->platform_data; struct palmas_gpio *gpio; int ret; gpio = kzalloc(sizeof(*gpio), GFP_KERNEL); if (!gpio) return -ENOMEM; gpio->palmas = palmas; gpio->gpio_chip = palmas_gpio_chip; gpio->gpio_chip.dev = &pdev->dev; if (pdata && pdata->gpio_base) gpio->gpio_chip.base = pdata->gpio_base; else gpio->gpio_chip.base = -1; ret = gpiochip_add(&gpio->gpio_chip); if (ret < 0) { dev_err(&pdev->dev, "Could not register gpiochip, %d\n", ret); goto err; } platform_set_drvdata(pdev, gpio); return ret; err: kfree(gpio); return ret; }
static int ssb_gpio_extif_init(struct ssb_bus *bus) { struct gpio_chip *chip = &bus->gpio; int err; chip->label = "ssb_extif_gpio"; chip->owner = THIS_MODULE; chip->get = ssb_gpio_extif_get_value; chip->set = ssb_gpio_extif_set_value; chip->direction_input = ssb_gpio_extif_direction_input; chip->direction_output = ssb_gpio_extif_direction_output; #if IS_ENABLED(CONFIG_SSB_EMBEDDED) chip->to_irq = ssb_gpio_to_irq; #endif chip->ngpio = 5; /* There is just one SoC in one device and its GPIO addresses should be * deterministic to address them more easily. The other buses could get * a random base number. */ if (bus->bustype == SSB_BUSTYPE_SSB) chip->base = 0; else chip->base = -1; err = ssb_gpio_irq_extif_domain_init(bus); if (err) return err; err = gpiochip_add(chip); if (err) { ssb_gpio_irq_extif_domain_exit(bus); return err; } return 0; }
static int __devinit ltq_stp_probe(struct platform_device *pdev) { struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); int ret = 0; if (!res) return -ENOENT; res = devm_request_mem_region(&pdev->dev, res->start, resource_size(res), dev_name(&pdev->dev)); if (!res) { dev_err(&pdev->dev, "failed to request STP memory\n"); return -EBUSY; } ltq_stp_membase = devm_ioremap_nocache(&pdev->dev, res->start, resource_size(res)); if (!ltq_stp_membase) { dev_err(&pdev->dev, "failed to remap STP memory\n"); return -ENOMEM; } ret = gpiochip_add(<q_stp_chip); if (!ret) ret = ltq_stp_hw_init(); return ret; }
int register_pinmux(struct pinmux_info *pip) { struct gpio_chip *chip = &pip->chip; pr_info("sh pinmux: %s handling gpio %d -> %d\n", pip->name, pip->first_gpio, pip->last_gpio); setup_data_regs(pip); chip->request = sh_gpio_request; chip->free = sh_gpio_free; chip->direction_input = sh_gpio_direction_input; chip->get = sh_gpio_get; chip->direction_output = sh_gpio_direction_output; chip->set = sh_gpio_set; WARN_ON(pip->first_gpio != 0); /* needs testing */ chip->label = pip->name; chip->owner = THIS_MODULE; chip->base = pip->first_gpio; chip->ngpio = (pip->last_gpio - pip->first_gpio) + 1; return gpiochip_add(chip); }
void __init puv3_init_gpio(void) { writel(GPIO_DIR, GPIO_GPDR); #if defined(CONFIG_PUV3_NB0916) || defined(CONFIG_PUV3_SMW0919) \ || defined(CONFIG_PUV3_DB0913) gpio_set_value(GPO_WIFI_EN, 1); gpio_set_value(GPO_HDD_LED, 1); gpio_set_value(GPO_VGA_EN, 1); gpio_set_value(GPO_LCD_EN, 1); gpio_set_value(GPO_CAM_PWR_EN, 0); gpio_set_value(GPO_LCD_VCC_EN, 1); gpio_set_value(GPO_SOFT_OFF, 1); gpio_set_value(GPO_BT_EN, 1); gpio_set_value(GPO_FAN_ON, 0); gpio_set_value(GPO_SPKR, 0); gpio_set_value(GPO_CPU_HEALTH, 1); gpio_set_value(GPO_LAN_SEL, 1); /* * DO NOT modify the GPO_SET_V1 and GPO_SET_V2 in kernel * gpio_set_value(GPO_SET_V1, 1); * gpio_set_value(GPO_SET_V2, 1); */ #endif gpiochip_add(&puv3_gpio_chip); }