Example #1
0
void mdp4_mddi_vsync_enable(struct msm_fb_data_type *mfd,
		struct mdp4_overlay_pipe *pipe, int which)
{
	uint32 start_y, data, tear_en;

	tear_en = (1 << which);

	if ((mfd->use_mdp_vsync) && (mfd->ibuf.vsync_enable) &&
		(mfd->panel_info.lcd.vsync_enable)) {

		if (mdp_hw_revision < MDP4_REVISION_V2_1) {
			/* need dmas dmap switch */
			if (which == 0 && dmap_vsync_enable == 0 &&
				mfd->panel_info.lcd.rev < 2) /* dma_p */
				return;
		}

		if (vsync_start_y_adjust <= pipe->dst_y)
			start_y = pipe->dst_y - vsync_start_y_adjust;
		else
			start_y = (mfd->total_lcd_lines - 1) -
				(vsync_start_y_adjust - pipe->dst_y);
		if (which == 0)
			MDP_OUTP(MDP_BASE + 0x210, start_y);	/* primary */
		else
			MDP_OUTP(MDP_BASE + 0x214, start_y);	/* secondary */

		data = inpdw(MDP_BASE + 0x20c);
		data |= tear_en;
		MDP_OUTP(MDP_BASE + 0x20c, data);
	} else {
		data = inpdw(MDP_BASE + 0x20c);
		data &= ~tear_en;
		MDP_OUTP(MDP_BASE + 0x20c, data);
	}
}
Example #2
0
void mdp4_overlay_dtv_vsync_push(struct msm_fb_data_type *mfd,
			struct mdp4_overlay_pipe *pipe)
{
	u32 data = inpdw(MDP_BASE + DTV_BASE);

	mdp4_overlay_reg_flush(pipe, 1);
	if (pipe->flags & MDP_OV_PLAY_NOWAIT)
		return;

	/* Return if DTV is not enabled */
	if (!(data & 0x1))
		return;

	mdp4_overlay_dtv_wait4vsync(mfd);
}
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int data;
	int change = 0;

	spin_lock_irqsave(&mdp_spin_lock, flag);
	if (enable && dsi_pipe->blt_addr == 0) {
		dsi_pipe->blt_addr = dsi_pipe->blt_base;
		dsi_pipe->blt_cnt = 0;
		dsi_pipe->ov_cnt = 0;
		dsi_pipe->dmap_cnt = 0;
		change++;
	} else if (enable == 0 && dsi_pipe->blt_addr) {
		dsi_pipe->blt_addr = 0;
		change++;
	}
	pr_info("%s: enable=%d blt_addr=%x\n", __func__,
				enable, (int)dsi_pipe->blt_addr);
	spin_unlock_irqrestore(&mdp_spin_lock, flag);

	if (!change)
		return;

	/*
	 * may need mutex here to sync with whom dsiable
	 * timing generator
	 */
	data = inpdw(MDP_BASE + DSI_VIDEO_BASE);
	if (data) {	/* timing generatore enabled */
		mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		msleep(20);	/* make sure last frame is finished */
		mipi_dsi_controller_cfg(0);
	}
	mdp4_overlayproc_cfg(dsi_pipe);
	mdp4_overlay_dmap_xy(dsi_pipe);

	if (data) {	/* timing generatore enabled */
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
		mdp4_overlay_dsi_video_wait4event(mfd, INTR_DMA_P_DONE);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		mipi_dsi_sw_reset();
		mipi_dsi_controller_cfg(1);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
	}
}
Example #4
0
static void mdp4_dtv_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int change = 0;

	if (!mfd->ov1_wb_buf->write_addr) {
		pr_debug("%s: no writeback buf assigned\n", __func__);
		return;
	}

	if (!dtv_pipe) {
		pr_debug("%s: no mixer1 base layer pipe allocated!\n",
			 __func__);
		return;
	}

	spin_lock_irqsave(&mdp_spin_lock, flag);
	if (enable && dtv_pipe->ov_blt_addr == 0) {
		dtv_pipe->ov_blt_addr = mfd->ov1_wb_buf->write_addr;
		dtv_pipe->dma_blt_addr = mfd->ov1_wb_buf->read_addr;
		change++;
		dtv_pipe->ov_cnt = 0;
		dtv_pipe->dmae_cnt = 0;
	} else if (enable == 0 && dtv_pipe->ov_blt_addr) {
		dtv_pipe->ov_blt_addr = 0;
		dtv_pipe->dma_blt_addr = 0;
		change++;
	}
	pr_debug("%s: ov_blt_addr=%x\n", __func__, (int)dtv_pipe->ov_blt_addr);
	spin_unlock_irqrestore(&mdp_spin_lock, flag);

	if (!change)
		return;

	if (dtv_enabled)
		mdp4_overlay_dtv_wait4dmae(mfd);

	while (inpdw(MDP_BASE + 0x0018) & 0x12)
		;

	if (enable) {
		mdp4_overlayproc_cfg(dtv_pipe);
		mdp4_overlay_dmae_xy(dtv_pipe);
	} else {
		mdp4_overlay_dmae_xy(dtv_pipe);
		mdp4_overlayproc_cfg(dtv_pipe);
	}
}
Example #5
0
void mdp4_dtv_set_black_screen()
{
	char *rgb_base;
	/*Black color*/
	uint32 color = 0x00000000;
	uint32 temp_src_format;
	int commit = 1, cndx = 0;
	int pipe_num = OVERLAY_PIPE_RGB1;
	struct vsycn_ctrl *vctrl;

	vctrl = &vsync_ctrl_db[cndx];
	if (!hdmi_prim_display)
		return;

	if (vctrl->base_pipe == NULL)
		commit = 0;
	else
		pipe_num = vctrl->base_pipe->pipe_num;

	rgb_base = MDP_BASE;
	rgb_base += (MDP4_RGB_OFF * (pipe_num + 2));

	/*
	* RGB Constant Color
	*/
	MDP_OUTP(rgb_base + 0x1008, color);
	/*
	* MDP_RGB_SRC_FORMAT
	*/
	temp_src_format = inpdw(rgb_base + 0x0050);
	MDP_OUTP(rgb_base + 0x0050, temp_src_format | BIT(22));
	mdp4_overlay_reg_flush(vctrl->base_pipe, 1);

	if (commit) {
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);

		mdp4_overlay_reg_flush(vctrl->base_pipe, 1);
		mdp4_mixer_stage_up(vctrl->base_pipe, 0);
		mdp4_mixer_stage_commit(vctrl->base_pipe->mixer_num);
	} else {
		/* MDP_OVERLAY_REG_FLUSH for pipe*/
		MDP_OUTP(MDP_BASE + 0x18000,
			BIT(pipe_num + 2) | BIT(MDP4_MIXER1));
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
	}
}
Example #6
0
void mdp4_dsi_video_overlay(struct msm_fb_data_type *mfd)
{
	struct fb_info *fbi = mfd->fbi;
	uint8 *buf;
	int bpp;
	int data = 0;
    int vg_active = 0; 
	struct mdp4_overlay_pipe *pipe;

	if (!mfd->panel_power_on)
		return;

	/* no need to power on cmd block since it's dsi mode */
	bpp = fbi->var.bits_per_pixel / 8;
	buf = (uint8 *) fbi->fix.smem_start;
    buf += fbi->var.xoffset * bpp +	fbi->var.yoffset * fbi->fix.line_length;

	mutex_lock(&mfd->dma->ov_mutex);

	pipe = dsi_pipe;
	pipe->srcp0_addr = (uint32) buf;
	mdp4_overlay_rgb_setup(pipe);
	mdp4_overlay_reg_flush(pipe, 1);
	mdp4_overlay_dsi_video_vsync_push(mfd, pipe);

    // This will check if there is any VG pipe connected to layermixer 0 
    mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);     
    data = inpdw(MDP_BASE + 0x10100); 
    
    rmb(); 
    if (data & 0xff) 
        vg_active = 1; 
    else 
        vg_active = 0; 
    
    mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE); 
	mutex_unlock(&mfd->dma->ov_mutex); 

    if (vg_active) 
	    yield();	
	mdp4_stat.kickoff_dsi++;
}
int mdp_lcdc_off(struct platform_device *pdev)
{
	int ret = 0;
	uint32 data;
	#ifdef CONFIG_FB_MSM_LCDC_LEAD_WVGA_PANEL    //ZTE_LCD_LHT_20100810_001
		if(LcdPanleID==72)
			lcdc_lead_sleep();
	#endif

	#ifdef CONFIG_FB_MSM_LCDC_WVGA_ARTHUR
		if(LcdPanleID==60)
			lcdc_lead_sleep();
		if(LcdPanleID==61)
			lcdc_truly_sleep();
	#endif
	/* MDP cmd block enable */
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
	MDP_OUTP(MDP_BASE + LCDC_BASE, 0);
	/* MDP cmd block disable */
	data = inpdw(MDP_BASE + 0x10100);
	data = data&0xffffff00;
	outpdw(MDP_BASE + 0x10100, data); 
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
	mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);

	mdp_histogram_ctrl(FALSE);
	ret = panel_next_off(pdev);

	/* delay to make sure the last frame finishes */
	msleep(16);

#ifdef LCDC_RGB_UNSTAGE
	/* dis-engage rgb0 from mixer0 */
	if (lcdc_pipe)
		mdp4_mixer_stage_down(lcdc_pipe);
#endif
#ifdef CONFIG_MSM_BUS_SCALING
	mdp_bus_scale_update_request(0);
#endif

	return ret;
}
static void mdp4_overlay_dtv_wait4_ov_done(struct msm_fb_data_type *mfd,
	struct mdp4_overlay_pipe *pipe)
{
	u32 data = inpdw(MDP_BASE + DTV_BASE);

	if (mfd->ov_start)
		mfd->ov_start = false;
	else
		return;
	if (!(data & 0x1) || (pipe == NULL))
		return;
	if (!dtv_pipe) {
		pr_debug("%s: no mixer1 base layer pipe allocated!\n",
			 __func__);
		return;
	}

	wait_for_completion_timeout(&dtv_pipe->comp,
			msecs_to_jiffies(VSYNC_PERIOD*2));
	mdp_disable_irq(MDP_OVERLAY1_TERM);
}
// QC_1205
void mdp4_dump_regs(void)
{
    int i, z, start, len;
    int offsets[] = {0x0, 0x200, 0x10000, 0x18000,  0x20000,  0x30000,  0x40000,  0x50000, 0x88000, 0x90000, 0xB0000, 0xD0000, 0xE0000};
    int length[]  = {24,     64,     101,     101,       32,       32,       32,       32,     101,      64,      64,      27,      64};

    for (i = 0; i < sizeof(offsets) / sizeof(int); i++) {
        start = offsets[i];
        len   = length[i];

        printk("-------- Address %05x: -------\n", start);
        for (z = 0; z < len; z++) {
            if ((z & 3) == 0)
                printk("%05x:", start + (z * 4));
            printk(" %08x", inpdw(MDP_BASE + start + (z * 4)));
            if ((z & 3) == 3)
                printk("\n");
        }
        if ((z & 3) != 0)
            printk("\n");
    }
}
/*
 * mdp4_overlay_lcdc_wait4event:
 * INTR_DMA_P_DONE and INTR_PRIMARY_VSYNC event only
 * no INTR_OVERLAY0_DONE event allowed.
 */
static void mdp4_overlay_lcdc_wait4event(struct msm_fb_data_type *mfd,
					int intr_done)
{
	unsigned long flag;
	unsigned int data;

	data = inpdw(MDP_BASE + LCDC_BASE);
	data &= 0x01;
	if (data == 0)	/* timing generator disabled */
		return;

	spin_lock_irqsave(&mdp_spin_lock, flag);
	INIT_COMPLETION(lcdc_comp);
	mfd->dma->waiting = TRUE;
	outp32(MDP_INTR_CLEAR, intr_done);
	mdp_intr_mask |= intr_done;
	outp32(MDP_INTR_ENABLE, mdp_intr_mask);
	mdp_enable_irq(MDP_DMA2_TERM);  /* enable intr */
	spin_unlock_irqrestore(&mdp_spin_lock, flag);
	wait_for_completion(&lcdc_comp);
	mdp_disable_irq(MDP_DMA2_TERM);
}
Example #11
0
int mdp4_overlay_writeback_off(struct platform_device *pdev)
{
	int ret;
	uint32 data;
	struct msm_fb_data_type *mfd =
			(struct msm_fb_data_type *)platform_get_drvdata(pdev);
	if (mfd && writeback_pipe) {
		mdp4_writeback_dma_busy_wait(mfd);
		mdp4_overlay_pipe_free(writeback_pipe);
		mdp4_overlay_panel_mode_unset(writeback_pipe->mixer_num,
						MDP4_PANEL_WRITEBACK);
		writeback_pipe = NULL;
	}
	ret = panel_next_off(pdev);
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
	/* MDP_LAYERMIXER_WB_MUX_SEL to restore
	 * mixer1 axi for mixer1 writeback */
	data = inpdw(MDP_BASE + 0x100F4);
	data &= ~0x02; /* clear the mixer1 mux bit */
	outpdw(MDP_BASE + 0x100F4, data);
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
	return ret;
}
static int mddi_reg_read(int ndx)
{
	struct mddi_reg *reg;
	unsigned char *base;
	int data;
	char *bp;
	int len = 0;
	int tot = 0;
	int dlen;

	if (ndx)
		base = msm_emdh_base;
	else
		base = msm_pmdh_base;

	reg = mddi_regs_list;
	bp = debug_buf;
	dlen = sizeof(debug_buf);

	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
	while (reg->name) {
		data = inpdw((u32)base + reg->off);
		rmb();
		len = snprintf(bp, dlen, "%s:0x%08x\t\t= 0x%08x\n",
					reg->name, reg->off, data);
		tot += len;
		bp += len;
		dlen -= len;
		reg++;
	}
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
	*bp = 0;
	tot++;

	return tot;
}
Example #13
0
/*
 * mdp4_overlay_dsi_video_wait4event:
 * INTR_DMA_P_DONE and INTR_PRIMARY_VSYNC event only
 * no INTR_OVERLAY0_DONE event allowed.
 */
static void mdp4_overlay_dsi_video_wait4event(struct msm_fb_data_type *mfd,
						int intr_done)
{
	unsigned long flag;
	unsigned int data;

	data = inpdw(MDP_BASE + DSI_VIDEO_BASE);
	data &= 0x01;
	if (data == 0)	/* timing generator disabled */
		return;

	spin_lock_irqsave(&mdp_spin_lock, flag);
	INIT_COMPLETION(dsi_video_comp);
	mfd->dma->waiting = TRUE;
	outp32(MDP_INTR_CLEAR, intr_done);
	mdp_intr_mask |= intr_done;
	outp32(MDP_INTR_ENABLE, mdp_intr_mask);
	mdp_enable_irq(MDP_DMA2_TERM);  /* enable intr */
	spin_unlock_irqrestore(&mdp_spin_lock, flag);

#if defined (LGE_BLT_LOCKUP_WR)
	if(!wait_for_completion_timeout(&dsi_video_comp, 1*HZ*0.5)) {
/*
		if(dsi_pipe->blt_addr) {
			mdp4_dsi_video_blt_stop(mfd);
			mdp4_dsi_video_blt_start(mfd);
		}
*/
		printk("Restoring BLT mode for interrupt %d \n", intr_done);
		printk("BLT mode change count  %u \n", blt_ent);
	}
#else
	wait_for_completion(&dsi_video_comp);
#endif
	mdp_disable_irq(MDP_DMA2_TERM);
}
static void mdp4_dump_status(void)
{
    PR_DISP_INFO("MDP_DISPLAY_STATUS:%x\n", inpdw(msm_mdp_base + 0x18));
    PR_DISP_INFO("MDP_INTR_STATUS:%x\n", inpdw(MDP_INTR_STATUS));
    PR_DISP_INFO("MDP_INTR_ENABLE:%x\n", inpdw(MDP_INTR_ENABLE));
    PR_DISP_INFO("MDP_LAYERMIXER_IN_CFG:%x\n", inpdw(msm_mdp_base + 0x10100));
    PR_DISP_INFO("MDP_OVERLAY_STATUS:%x\n", inpdw(msm_mdp_base + 0x10000));
    PR_DISP_INFO("MDP_OVERLAYPROC0_CFG:%x\n", inpdw(msm_mdp_base + 0x10004));
    PR_DISP_INFO("MDP_OVERLAYPROC1_CFG:%x\n", inpdw(msm_mdp_base + 0x18004));
    PR_DISP_INFO("RGB1(1):%x %x %x %x\n", inpdw(msm_mdp_base + 0x40000),
                 inpdw(msm_mdp_base + 0x40004), inpdw(msm_mdp_base + 0x40008),
                 inpdw(msm_mdp_base + 0x4000C));
    PR_DISP_INFO("RGB1(2):%x %x %x %x\n", inpdw(msm_mdp_base + 0x40010),
                 inpdw(msm_mdp_base + 0x40014), inpdw(msm_mdp_base + 0x40018),
                 inpdw(msm_mdp_base + 0x40040));
    PR_DISP_INFO("RGB1(3):%x %x %x %x\n", inpdw(msm_mdp_base + 0x40050),
                 inpdw(msm_mdp_base + 0x40054), inpdw(msm_mdp_base + 0x40058),
                 inpdw(msm_mdp_base + 0x4005C));
    PR_DISP_INFO("RGB1(4):%x %x %x %x\n", inpdw(msm_mdp_base + 0x40060),
                 inpdw(msm_mdp_base + 0x41000), inpdw(msm_mdp_base + 0x41004),
                 inpdw(msm_mdp_base + 0x41008));
    PR_DISP_INFO("RGB2(1):%x %x %x %x\n", inpdw(msm_mdp_base + 0x50000),
                 inpdw(msm_mdp_base + 0x50004), inpdw(msm_mdp_base + 0x50008),
                 inpdw(msm_mdp_base + 0x5000C));
    PR_DISP_INFO("RGB2(2):%x %x %x %x\n", inpdw(msm_mdp_base + 0x50010),
                 inpdw(msm_mdp_base + 0x50014), inpdw(msm_mdp_base + 0x50018),
                 inpdw(msm_mdp_base + 0x50040));
    PR_DISP_INFO("RGB2(3):%x %x %x %x\n", inpdw(msm_mdp_base + 0x50050),
                 inpdw(msm_mdp_base + 0x50054), inpdw(msm_mdp_base + 0x50058),
                 inpdw(msm_mdp_base + 0x5005C));
    PR_DISP_INFO("RGB2(4):%x %x %x %x\n", inpdw(msm_mdp_base + 0x50060),
                 inpdw(msm_mdp_base + 0x51000), inpdw(msm_mdp_base + 0x51004),
                 inpdw(msm_mdp_base + 0x51008));
    PR_DISP_INFO("VG1 (1):%x %x %x %x\n", inpdw(msm_mdp_base + 0x20000),
                 inpdw(msm_mdp_base + 0x20004), inpdw(msm_mdp_base + 0x20008),
                 inpdw(msm_mdp_base + 0x2000C));
    PR_DISP_INFO("VG1 (2):%x %x %x %x\n", inpdw(msm_mdp_base + 0x20010),
                 inpdw(msm_mdp_base + 0x20014), inpdw(msm_mdp_base + 0x20018),
                 inpdw(msm_mdp_base + 0x20040));
    PR_DISP_INFO("VG1 (3):%x %x %x %x\n", inpdw(msm_mdp_base + 0x20050),
                 inpdw(msm_mdp_base + 0x20054), inpdw(msm_mdp_base + 0x20058),
                 inpdw(msm_mdp_base + 0x2005C));
    PR_DISP_INFO("VG1 (4):%x %x %x %x\n", inpdw(msm_mdp_base + 0x20060),
                 inpdw(msm_mdp_base + 0x21000), inpdw(msm_mdp_base + 0x21004),
                 inpdw(msm_mdp_base + 0x21008));
    PR_DISP_INFO("VG2 (1):%x %x %x %x\n", inpdw(msm_mdp_base + 0x30000),
                 inpdw(msm_mdp_base + 0x30004), inpdw(msm_mdp_base + 0x30008),
                 inpdw(msm_mdp_base + 0x3000C));
    PR_DISP_INFO("VG2 (2):%x %x %x %x\n", inpdw(msm_mdp_base + 0x30010),
                 inpdw(msm_mdp_base + 0x30014), inpdw(msm_mdp_base + 0x30018),
                 inpdw(msm_mdp_base + 0x30040));
    PR_DISP_INFO("VG2 (3):%x %x %x %x\n",
                 inpdw(msm_mdp_base + 0x30050), inpdw(msm_mdp_base + 0x30054),
                 inpdw(msm_mdp_base + 0x30058), inpdw(msm_mdp_base + 0x3005C));
    PR_DISP_INFO("VG2 (4):%x %x %x %x\n",
                 inpdw(msm_mdp_base + 0x30060), inpdw(msm_mdp_base + 0x31000),
                 inpdw(msm_mdp_base + 0x31004), inpdw(msm_mdp_base + 0x31008));
}
int mdp_lcdc_on(struct platform_device *pdev)
{
	int lcdc_width;
	int lcdc_height;
	int lcdc_bpp;
	int lcdc_border_clr;
	int lcdc_underflow_clr;
	int lcdc_hsync_skew;

	int hsync_period;
	int hsync_ctrl;
	int vsync_period;
	int display_hctl;
	int display_v_start;
	int display_v_end;
	int active_hctl;
	int active_h_start;
	int active_h_end;
	int active_v_start;
	int active_v_end;
	int ctrl_polarity;
	int h_back_porch;
	int h_front_porch;
	int v_back_porch;
	int v_front_porch;
	int hsync_pulse_width;
	int vsync_pulse_width;
	int hsync_polarity;
	int vsync_polarity;
	int data_en_polarity;
	int hsync_start_x;
	int hsync_end_x;
	uint8 *buf;
	int bpp;
	uint32 dma2_cfg_reg;
	struct fb_info *fbi;
	struct fb_var_screeninfo *var;
	struct msm_fb_data_type *mfd;
	uint32 dma_base;
	uint32 timer_base = LCDC_BASE;
	uint32 block = MDP_DMA2_BLOCK;
	int ret;
	uint32_t mask, curr;

	mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);

	if (!mfd)
		return -ENODEV;

	if (mfd->key != MFD_KEY)
		return -EINVAL;

	fbi = mfd->fbi;
	var = &fbi->var;
	vsync_cntrl.dev = mfd->fbi->dev;
	atomic_set(&vsync_cntrl.suspend, 0);

	
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);

	bpp = fbi->var.bits_per_pixel / 8;
	buf = (uint8 *) fbi->fix.smem_start;

	buf += calc_fb_offset(mfd, fbi, bpp);

	dma2_cfg_reg = DMA_PACK_ALIGN_LSB | DMA_OUT_SEL_LCDC;

	if (mfd->fb_imgType == MDP_BGR_565)
		dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
	else if (mfd->fb_imgType == MDP_RGBA_8888)
		dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
	else
		dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;

	if (bpp == 2)
		dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB565;
	else if (bpp == 3)
		dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB888;
	else
		dma2_cfg_reg |= DMA_IBUF_FORMAT_xRGB8888_OR_ARGB8888;

	switch (mfd->panel_info.bpp) {
	case 24:
		dma2_cfg_reg |= DMA_DSTC0G_8BITS |
		    DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
		break;

	case 18:
		dma2_cfg_reg |= DMA_DSTC0G_6BITS |
		    DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
		break;

	case 16:
		dma2_cfg_reg |= DMA_DSTC0G_6BITS |
		    DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
		break;

	default:
		printk(KERN_ERR "mdp lcdc can't support format %d bpp!\n",
		       mfd->panel_info.bpp);
		return -ENODEV;
	}

	

	dma_base = DMA_P_BASE;

#ifdef CONFIG_FB_MSM_MDP40
	if (mfd->panel.type == HDMI_PANEL)
		dma_base = DMA_E_BASE;
#endif

	
	MDP_OUTP(MDP_BASE + dma_base + 0x8, (uint32) buf);
	
	MDP_OUTP(MDP_BASE + dma_base + 0x4, ((fbi->var.yres) << 16) |
						(fbi->var.xres));
	
	MDP_OUTP(MDP_BASE + dma_base + 0xc, fbi->fix.line_length);
	
	MDP_OUTP(MDP_BASE + dma_base + 0x10, 0);
	
	curr = inpdw(MDP_BASE + DMA_P_BASE);
	mask = 0x0FFFFFFF;
	dma2_cfg_reg = (dma2_cfg_reg & mask) | (curr & ~mask);
	MDP_OUTP(MDP_BASE + dma_base, dma2_cfg_reg);

	h_back_porch = var->left_margin;
	h_front_porch = var->right_margin;
	v_back_porch = var->upper_margin;
	v_front_porch = var->lower_margin;
	hsync_pulse_width = var->hsync_len;
	vsync_pulse_width = var->vsync_len;
	lcdc_border_clr = mfd->panel_info.lcdc.border_clr;
	lcdc_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
	lcdc_hsync_skew = mfd->panel_info.lcdc.hsync_skew;

	lcdc_width = mfd->panel_info.xres;
	lcdc_height = mfd->panel_info.yres;
	lcdc_bpp = mfd->panel_info.bpp;

	hsync_period =
	    hsync_pulse_width + h_back_porch + lcdc_width + h_front_porch;
	hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
	hsync_start_x = hsync_pulse_width + h_back_porch;
	hsync_end_x = hsync_period - h_front_porch - 1;
	display_hctl = (hsync_end_x << 16) | hsync_start_x;

	vsync_period =
	    (vsync_pulse_width + v_back_porch + lcdc_height +
	     v_front_porch) * hsync_period;
	display_v_start =
	    (vsync_pulse_width + v_back_porch) * hsync_period + lcdc_hsync_skew;
	display_v_end =
	    vsync_period - (v_front_porch * hsync_period) + lcdc_hsync_skew - 1;

	if (lcdc_width != var->xres) {
		active_h_start = hsync_start_x + first_pixel_start_x;
		active_h_end = active_h_start + var->xres - 1;
		active_hctl =
		    ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start;
	} else {
		active_hctl = 0;
	}

	if (lcdc_height != var->yres) {
		active_v_start =
		    display_v_start + first_pixel_start_y * hsync_period;
		active_v_end = active_v_start + (var->yres) * hsync_period - 1;
		active_v_start |= ACTIVE_START_Y_EN;
	} else {
		active_v_start = 0;
		active_v_end = 0;
	}


#ifdef CONFIG_FB_MSM_MDP40
	if (mfd->panel.type == HDMI_PANEL) {
		block = MDP_DMA_E_BLOCK;
		timer_base = DTV_BASE;
		hsync_polarity = 0;
		vsync_polarity = 0;
	} else {
		hsync_polarity = 1;
		vsync_polarity = 1;
	}

	lcdc_underflow_clr |= 0x80000000;	
#else
	hsync_polarity = 0;
	vsync_polarity = 0;
#endif
	data_en_polarity = 0;

	ctrl_polarity =
	    (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);

	if (!(mfd->cont_splash_done)) {
		mdp_pipe_ctrl(MDP_CMD_BLOCK,
			MDP_BLOCK_POWER_OFF, FALSE);
		MDP_OUTP(MDP_BASE + timer_base, 0);
	}

	MDP_OUTP(MDP_BASE + timer_base + 0x4, hsync_ctrl);
	MDP_OUTP(MDP_BASE + timer_base + 0x8, vsync_period);
	MDP_OUTP(MDP_BASE + timer_base + 0xc, vsync_pulse_width * hsync_period);
	if (timer_base == LCDC_BASE) {
		MDP_OUTP(MDP_BASE + timer_base + 0x10, display_hctl);
		MDP_OUTP(MDP_BASE + timer_base + 0x14, display_v_start);
		MDP_OUTP(MDP_BASE + timer_base + 0x18, display_v_end);
		MDP_OUTP(MDP_BASE + timer_base + 0x28, lcdc_border_clr);
		MDP_OUTP(MDP_BASE + timer_base + 0x2c, lcdc_underflow_clr);
		MDP_OUTP(MDP_BASE + timer_base + 0x30, lcdc_hsync_skew);
		MDP_OUTP(MDP_BASE + timer_base + 0x38, ctrl_polarity);
		MDP_OUTP(MDP_BASE + timer_base + 0x1c, active_hctl);
		MDP_OUTP(MDP_BASE + timer_base + 0x20, active_v_start);
		MDP_OUTP(MDP_BASE + timer_base + 0x24, active_v_end);
	} else {
		MDP_OUTP(MDP_BASE + timer_base + 0x18, display_hctl);
		MDP_OUTP(MDP_BASE + timer_base + 0x1c, display_v_start);
		MDP_OUTP(MDP_BASE + timer_base + 0x20, display_v_end);
		MDP_OUTP(MDP_BASE + timer_base + 0x40, lcdc_border_clr);
		MDP_OUTP(MDP_BASE + timer_base + 0x44, lcdc_underflow_clr);
		MDP_OUTP(MDP_BASE + timer_base + 0x48, lcdc_hsync_skew);
		MDP_OUTP(MDP_BASE + timer_base + 0x50, ctrl_polarity);
		MDP_OUTP(MDP_BASE + timer_base + 0x2c, active_hctl);
		MDP_OUTP(MDP_BASE + timer_base + 0x30, active_v_start);
		MDP_OUTP(MDP_BASE + timer_base + 0x38, active_v_end);
	}

	ret = panel_next_on(pdev);
	if (ret == 0) {
		
		MDP_OUTP(MDP_BASE + timer_base, 1);
		mdp_pipe_ctrl(block, MDP_BLOCK_POWER_ON, FALSE);
	}
	
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);

	if (!vsync_cntrl.sysfs_created) {
		ret = sysfs_create_group(&vsync_cntrl.dev->kobj,
			&vsync_fs_attr_group);
		if (ret) {
			pr_err("%s: sysfs creation failed, ret=%d\n",
				__func__, ret);
			return ret;
		}

		kobject_uevent(&vsync_cntrl.dev->kobj, KOBJ_ADD);
		pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
		vsync_cntrl.sysfs_created = 1;
	}
	mdp_histogram_ctrl_all(TRUE);

	return ret;
}
Example #16
0
int mdp_dsi_video_on(struct platform_device *pdev)
{
    int dsi_width;
    int dsi_height;
    int dsi_bpp;
    int dsi_border_clr;
    int dsi_underflow_clr;
    int dsi_hsync_skew;

    int hsync_period;
    int hsync_ctrl;
    int vsync_period;
    int display_hctl;
    int display_v_start;
    int display_v_end;
    int active_hctl;
    int active_h_start;
    int active_h_end;
    int active_v_start;
    int active_v_end;
    int ctrl_polarity;
    int h_back_porch;
    int h_front_porch;
    int v_back_porch;
    int v_front_porch;
    int hsync_pulse_width;
    int vsync_pulse_width;
    int hsync_polarity;
    int vsync_polarity;
    int data_en_polarity;
    int hsync_start_x;
    int hsync_end_x;
    uint8 *buf;
    uint32 dma2_cfg_reg;

    int bpp;
    struct fb_info *fbi;
    struct fb_var_screeninfo *var;
    struct msm_fb_data_type *mfd;
    int ret;
    uint32_t mask, curr;

    /* LGE_CHANGE_S : LCD ESD Protection
     * 2012-01-30, yoonsoo@lge.com
     * LCD ESD Protection
     */
#ifdef CONFIG_LGE_LCD_ESD_DETECTION
    if( (!esd_reset_pdev) && (pdev))
    {
        esd_reset_pdev = pdev;
    }
#endif
    /* LGE_CHANGE_E : LCD ESD Protection*/

    mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);

    if (!mfd)
        return -ENODEV;

    if (mfd->key != MFD_KEY)
        return -EINVAL;

    fbi = mfd->fbi;
    var = &fbi->var;

    vsync_cntrl.dev = mfd->fbi->dev;
    atomic_set(&vsync_cntrl.suspend, 0);
    bpp = fbi->var.bits_per_pixel / 8;
    buf = (uint8 *) fbi->fix.smem_start;

    buf += calc_fb_offset(mfd, fbi, bpp);

    dma2_cfg_reg = DMA_PACK_ALIGN_LSB | DMA_OUT_SEL_DSI_VIDEO;

    if (mfd->fb_imgType == MDP_BGR_565)
        dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
    else if (mfd->fb_imgType == MDP_RGBA_8888)
        dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
    else
        dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;

    if (bpp == 2)
        dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB565;
    else if (bpp == 3)
        dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB888;
    else
        dma2_cfg_reg |= DMA_IBUF_FORMAT_xRGB8888_OR_ARGB8888;

    switch (mfd->panel_info.bpp) {
    case 24:
        dma2_cfg_reg |= DMA_DSTC0G_8BITS |
                        DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
        break;
    case 18:
        dma2_cfg_reg |= DMA_DSTC0G_6BITS |
                        DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
        break;
    case 16:
        dma2_cfg_reg |= DMA_DSTC0G_6BITS |
                        DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
        break;
    default:
        printk(KERN_ERR "mdp lcdc can't support format %d bpp!\n",
               mfd->panel_info.bpp);
        return -ENODEV;
    }
    /* MDP cmd block enable */
    mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);


    /* starting address */
    MDP_OUTP(MDP_BASE + DMA_P_BASE + 0x8, (uint32) buf);

    /* active window width and height */
    MDP_OUTP(MDP_BASE + DMA_P_BASE + 0x4, ((fbi->var.yres) << 16) |
             (fbi->var.xres));

    /* buffer ystride */
    MDP_OUTP(MDP_BASE + DMA_P_BASE + 0xc, fbi->fix.line_length);

    /* x/y coordinate = always 0 for lcdc */
    MDP_OUTP(MDP_BASE + DMA_P_BASE + 0x10, 0);

    /* dma config */
    curr = inpdw(MDP_BASE + DMA_P_BASE);
    mask = 0x0FFFFFFF;
    dma2_cfg_reg = (dma2_cfg_reg & mask) | (curr & ~mask);
    MDP_OUTP(MDP_BASE + DMA_P_BASE, dma2_cfg_reg);

    /*
     * DSI timing setting
     */
    h_back_porch = var->left_margin;
    h_front_porch = var->right_margin;
    v_back_porch = var->upper_margin;
    v_front_porch = var->lower_margin;
    hsync_pulse_width = var->hsync_len;
    vsync_pulse_width = var->vsync_len;
    dsi_border_clr = mfd->panel_info.lcdc.border_clr;
    dsi_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
    dsi_hsync_skew = mfd->panel_info.lcdc.hsync_skew;
    dsi_width = mfd->panel_info.xres;
    dsi_height = mfd->panel_info.yres;
    dsi_bpp = mfd->panel_info.bpp;
    hsync_period = h_back_porch + dsi_width + h_front_porch + 1;
    hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
    hsync_start_x = h_back_porch;
    hsync_end_x = dsi_width + h_back_porch - 1;
    display_hctl = (hsync_end_x << 16) | hsync_start_x;

    vsync_period =
        (v_back_porch + dsi_height + v_front_porch + 1) * hsync_period;
    display_v_start = v_back_porch * hsync_period + dsi_hsync_skew;
    display_v_end = (dsi_height + v_back_porch) * hsync_period;

    active_h_start = hsync_start_x + first_pixel_start_x;
    active_h_end = active_h_start + var->xres - 1;
    active_hctl = ACTIVE_START_X_EN |
                  (active_h_end << 16) | active_h_start;

    active_v_start = display_v_start +
                     first_pixel_start_y * hsync_period;
    active_v_end = active_v_start +	(var->yres) * hsync_period - 1;
    active_v_start |= ACTIVE_START_Y_EN;

    dsi_underflow_clr |= 0x80000000;	/* enable recovery */
    hsync_polarity = 0;
    vsync_polarity = 0;
    data_en_polarity = 0;

    ctrl_polarity =	(data_en_polarity << 2) |
                    (vsync_polarity << 1) | (hsync_polarity);

    /*LGE_CHANGE_S : seven.kim@lge.com to migrate pre-CS kernel*/
#ifndef CONFIG_FB_MSM_EBI2

    /*[LGSI_SP4_BSP_BEGIN] [kiran.jainapure@lge.com] - Multiple power off registers. Sometimes display is not wakeup*/
#ifndef CONFIG_FB_MSM_MIPI_DSI_LG4573B
    if (!(mfd->cont_splash_done))
    {

        mdp_pipe_ctrl(MDP_CMD_BLOCK,
                      MDP_BLOCK_POWER_OFF, FALSE);
        MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
        mipi_dsi_controller_cfg(0);
    }
#else /* below code is required for smooth boot logo display*/
    /*LGE_CHANGE_S, youngbae.choi@lge.com, 12-12-28, for V7 sometimes booting animation is no display*/
#if !defined(CONFIG_MACH_MSM8X25_V7)
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
    mipi_dsi_controller_cfg(0);
#endif
    /*LGE_CHANGE_E, youngbae.choi@lge.com, 12-12-28, for V7 sometimes booting animation is no display*/
#endif /* below code is required for smooth boot logo display*/
    /*[LGSI_SP4_BSP_END] [kiran.jainapure@lge.com] */

#endif /*CONFIG_FB_MSM_EBI2*/
    /*LGE_CHANGE_E : seven.kim@lge.com to migrate pre-CS kernel*/

    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x4, hsync_ctrl);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x8, vsync_period);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0xc, vsync_pulse_width);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x10, display_hctl);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x14, display_v_start);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x18, display_v_end);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x1c, active_hctl);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x20, active_v_start);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x24, active_v_end);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x28, dsi_border_clr);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x2c, dsi_underflow_clr);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x30, dsi_hsync_skew);
    MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x38, ctrl_polarity);

    ret = panel_next_on(pdev);
    if (ret == 0) {
        /* enable DSI block */
        MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
        /*Turning on DMA_P block*/
        mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
    }

    /* MDP cmd block disable */
    mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);

    if (!vsync_cntrl.sysfs_created) {
        ret = sysfs_create_group(&vsync_cntrl.dev->kobj,
                                 &vsync_fs_attr_group);
        if (ret) {
            pr_err("%s: sysfs creation failed, ret=%d\n",
                   __func__, ret);
            return ret;
        }

        kobject_uevent(&vsync_cntrl.dev->kobj, KOBJ_ADD);
        pr_debug("%s: kobject_uevent(KOBJ_ADD)\n", __func__);
        vsync_cntrl.sysfs_created = 1;
    }

    return ret;
}
static ssize_t dbg_reg_read(
	struct file *file,
	char __user *buff,
	size_t count,
	loff_t *ppos)
{
	int len = 0;
	uint32 data;
	int i, j, off, dlen, num;
	char *bp, *cp;
	int tot = 0;


	if (*ppos)
		return 0;	/* the end */

	if (dbg_base == 0)
		return 0;	/* nothing to read */

	j = 0;
	num = 0;
	bp = debug_buf;
	cp = (char *)(dbg_base + dbg_offset);
	dlen = sizeof(debug_buf);
	while (j++ < 16) {
		len = snprintf(bp, dlen, "0x%08x: ", (int)cp);
		tot += len;
		bp += len;
		dlen -= len;
		off = 0;
		i = 0;
		while (i++ < 4) {
			data = inpdw(cp + off);
			rmb();
			len = snprintf(bp, dlen, "%08x ", data);
			tot += len;
			bp += len;
			dlen -= len;
			off += 4;
			num++;
			if (num >= dbg_count)
				break;
		}
		data = inpdw((u32)cp + off);
		rmb();
		*bp++ = '\n';
		--dlen;
		tot++;
		cp += off;
		if (num >= dbg_count)
			break;
	}
	*bp = 0;
	tot++;

	if (copy_to_user(buff, debug_buf, tot))
		return -EFAULT;

	*ppos += tot;	/* increase offset */

	return tot;
}
/*
 * mdp4_dsi_cmd_dma_busy_wait: check dsi link activity
 * dsi link is a shared resource and it can only be used
 * while it is in idle state.
 * ov_mutex need to be acquired before call this function.
 */
void mdp4_dsi_cmd_dma_busy_wait(struct msm_fb_data_type *mfd)
{
	unsigned long flag;
	int need_wait = 0;
#if 1 /* HTC_CSP_START */
	int retry_count = 0;
	long timeout;
#endif /* HTC_CSP_END */

	if (dsi_clock_timer.function) {
		if (time_after(jiffies, tout_expired)) {
			tout_expired = jiffies + TOUT_PERIOD;
			mod_timer(&dsi_clock_timer, tout_expired);
			tout_expired -= MS_100;
		}
	}

	pr_debug("%s: start pid=%d dsi_clk_on=%d\n",
			__func__, current->pid, mipi_dsi_clk_on);

	/* satrt dsi clock if necessary */
	if (mipi_dsi_clk_on == 0) {
		local_bh_disable();
		mipi_dsi_turn_on_clks();
		local_bh_enable();
	}

	spin_lock_irqsave(&mdp_spin_lock, flag);
	if (mfd->dma->busy == TRUE) {
		if (busy_wait_cnt == 0)
			INIT_COMPLETION(mfd->dma->comp);
		busy_wait_cnt++;
		need_wait++;
	}
	spin_unlock_irqrestore(&mdp_spin_lock, flag);

	if (need_wait) {
		/* wait until DMA finishes the current job */
		pr_debug("%s: pending pid=%d dsi_clk_on=%d\n",
				__func__, current->pid, mipi_dsi_clk_on);
#if 1 /* HTC_CSP_START */
		timeout = wait_for_completion_timeout(&mfd->dma->comp, HZ/5);

		while (!timeout && retry_count++ < 15) {
			rmb();
			if (mfd->dma->busy == FALSE) {
				PR_DISP_INFO("%s(%d)timeout but dma not busy now, cnt:%d\n", __func__, __LINE__, busy_wait_cnt);
				break;
			} else {
				PR_DISP_INFO("%s(%d)timeout but dma still busy\n", __func__, __LINE__);
				PR_DISP_INFO("###busy_wait_cnt:%d need_wait:%d pending pid=%d dsi_clk_on=%d\n", busy_wait_cnt, need_wait, current->pid, mipi_dsi_clk_on);
				PR_DISP_INFO("MDP_DISPLAY_STATUS:%x\n", inpdw(msm_mdp_base + 0x18));
				PR_DISP_INFO("MDP_INTR_STATUS:%x\n", inpdw(MDP_INTR_STATUS));
				PR_DISP_INFO("MDP_INTR_ENABLE:%x\n", inpdw(MDP_INTR_ENABLE));
				PR_DISP_INFO("MDP_PRIM_INT_CNT_VAL:%x\n", inpdw(msm_mdp_base + 0x0140));
				PR_DISP_INFO("MDP_LAYERMIXER_IN_CFG:%x\n", inpdw(msm_mdp_base + 0x10100));
				PR_DISP_INFO("MDP_OVERLAY_STATUS:%x\n", inpdw(msm_mdp_base + 0x10000));
				PR_DISP_INFO("MDP_OVERLAYPROC0_CFG:%x\n", inpdw(msm_mdp_base + 0x10004));
				PR_DISP_INFO("MDP_OVERLAYPROC1_CFG:%x\n", inpdw(msm_mdp_base + 0x18004));
				PR_DISP_INFO("RGB1(1):%x %x %x %x\n", inpdw(msm_mdp_base + 0x40000), inpdw(msm_mdp_base + 0x40004), inpdw(msm_mdp_base + 0x40008), inpdw(msm_mdp_base + 0x4000C));
				PR_DISP_INFO("RGB1(2):%x %x %x %x\n", inpdw(msm_mdp_base + 0x40010), inpdw(msm_mdp_base + 0x40014), inpdw(msm_mdp_base + 0x40018), inpdw(msm_mdp_base + 0x40040));
				PR_DISP_INFO("RGB1(3):%x %x %x %x\n", inpdw(msm_mdp_base + 0x40050), inpdw(msm_mdp_base + 0x40054), inpdw(msm_mdp_base + 0x40058), inpdw(msm_mdp_base + 0x4005C));
				PR_DISP_INFO("RGB1(4):%x %x %x %x\n", inpdw(msm_mdp_base + 0x40060), inpdw(msm_mdp_base + 0x41000), inpdw(msm_mdp_base + 0x41004), inpdw(msm_mdp_base + 0x41008));
				PR_DISP_INFO("RGB2(1):%x %x %x %x\n", inpdw(msm_mdp_base + 0x50000), inpdw(msm_mdp_base + 0x50004), inpdw(msm_mdp_base + 0x50008), inpdw(msm_mdp_base + 0x5000C));
				PR_DISP_INFO("RGB2(2):%x %x %x %x\n", inpdw(msm_mdp_base + 0x50010), inpdw(msm_mdp_base + 0x50014), inpdw(msm_mdp_base + 0x50018), inpdw(msm_mdp_base + 0x50040));
				PR_DISP_INFO("RGB2(3):%x %x %x %x\n", inpdw(msm_mdp_base + 0x50050), inpdw(msm_mdp_base + 0x50054), inpdw(msm_mdp_base + 0x50058), inpdw(msm_mdp_base + 0x5005C));
				PR_DISP_INFO("RGB2(4):%x %x %x %x\n", inpdw(msm_mdp_base + 0x50060), inpdw(msm_mdp_base + 0x51000), inpdw(msm_mdp_base + 0x51004), inpdw(msm_mdp_base + 0x51008));
				PR_DISP_INFO("VG1 (1):%x %x %x %x\n", inpdw(msm_mdp_base + 0x20000), inpdw(msm_mdp_base + 0x20004), inpdw(msm_mdp_base + 0x20008), inpdw(msm_mdp_base + 0x2000C));
				PR_DISP_INFO("VG1 (2):%x %x %x %x\n", inpdw(msm_mdp_base + 0x20010), inpdw(msm_mdp_base + 0x20014), inpdw(msm_mdp_base + 0x20018), inpdw(msm_mdp_base + 0x20040));
				PR_DISP_INFO("VG1 (3):%x %x %x %x\n", inpdw(msm_mdp_base + 0x20050), inpdw(msm_mdp_base + 0x20054), inpdw(msm_mdp_base + 0x20058), inpdw(msm_mdp_base + 0x2005C));
				PR_DISP_INFO("VG1 (4):%x %x %x %x\n", inpdw(msm_mdp_base + 0x20060), inpdw(msm_mdp_base + 0x21000), inpdw(msm_mdp_base + 0x21004), inpdw(msm_mdp_base + 0x21008));
				PR_DISP_INFO("VG2 (1):%x %x %x %x\n", inpdw(msm_mdp_base + 0x30000), inpdw(msm_mdp_base + 0x30004), inpdw(msm_mdp_base + 0x30008), inpdw(msm_mdp_base + 0x3000C));
				PR_DISP_INFO("VG2 (2):%x %x %x %x\n", inpdw(msm_mdp_base + 0x30010), inpdw(msm_mdp_base + 0x30014), inpdw(msm_mdp_base + 0x30018), inpdw(msm_mdp_base + 0x30040));
				PR_DISP_INFO("VG2 (3):%x %x %x %x\n", inpdw(msm_mdp_base + 0x30050), inpdw(msm_mdp_base + 0x30054), inpdw(msm_mdp_base + 0x30058), inpdw(msm_mdp_base + 0x3005C));
				PR_DISP_INFO("VG2 (4):%x %x %x %x\n", inpdw(msm_mdp_base + 0x30060), inpdw(msm_mdp_base + 0x31000), inpdw(msm_mdp_base + 0x31004), inpdw(msm_mdp_base + 0x31008));

				timeout = wait_for_completion_timeout(&mfd->dma->comp, HZ/5);
			}
		}

		if (retry_count >= 15) {
			PR_DISP_INFO("###mdp busy wait retry timed out, mfd->dma->busy:%d busy_wait_cnt:%d\n",  mfd->dma->busy, busy_wait_cnt);
			spin_lock_irqsave(&mdp_spin_lock, flag);
			if(busy_wait_cnt > 0)
				--busy_wait_cnt;
			mfd->dma->busy = FALSE;
			spin_unlock_irqrestore(&mdp_spin_lock, flag);
		}
#else /* HTC_CSP_END */
		wait_for_completion(&mfd->dma->comp);
#endif
	}
	pr_debug("%s: done pid=%d dsi_clk_on=%d\n",
			 __func__, current->pid, mipi_dsi_clk_on);
}
void mdp4_overlay_update_lcd(struct msm_fb_data_type *mfd)
{
	MDPIBUF *iBuf = &mfd->ibuf;
	uint8 *src;
	int ptype;
	uint32 mddi_ld_param;
	uint16 mddi_vdo_packet_reg;
	struct mdp4_overlay_pipe *pipe;
	int ret;

	if (mfd->key != MFD_KEY)
		return;

	mddi_mfd = mfd;		/* keep it */

	/* MDP cmd block enable */
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);

	if (mddi_pipe == NULL) {
		ptype = mdp4_overlay_format2type(mfd->fb_imgType);
		if (ptype < 0)
			printk(KERN_INFO "%s: format2type failed\n", __func__);
		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0, 0);
		if (pipe == NULL)
			printk(KERN_INFO "%s: pipe_alloc failed\n", __func__);
		pipe->pipe_used++;
		pipe->mixer_num  = MDP4_MIXER0;
		pipe->src_format = mfd->fb_imgType;
		mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_MDDI);
		ret = mdp4_overlay_format2pipe(pipe);
		if (ret < 0)
			printk(KERN_INFO "%s: format2type failed\n", __func__);

		mddi_pipe = pipe; /* keep it */
		mddi_pipe->blt_end = 1;	/* mark as end */
		mddi_ld_param = 0;
		mddi_vdo_packet_reg = mfd->panel_info.mddi.vdopkt;

		if (mdp_hw_revision == MDP4_REVISION_V2_1) {
			uint32	data;

			data = inpdw(MDP_BASE + 0x0028);
			data &= ~0x0300;	/* bit 8, 9, MASTER4 */
			if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
				data |= 0x0200;
			else
				data |= 0x0100;

			MDP_OUTP(MDP_BASE + 0x00028, data);
		}

		if (mfd->panel_info.type == MDDI_PANEL) {
			if (mfd->panel_info.pdest == DISPLAY_1)
				mddi_ld_param = 0;
			else
				mddi_ld_param = 1;
		} else {
			mddi_ld_param = 2;
		}

		MDP_OUTP(MDP_BASE + 0x00090, mddi_ld_param);

		if (mfd->panel_info.bpp == 24)
			MDP_OUTP(MDP_BASE + 0x00094,
			 (MDDI_VDO_PACKET_DESC_24 << 16) | mddi_vdo_packet_reg);
		else if (mfd->panel_info.bpp == 16)
			MDP_OUTP(MDP_BASE + 0x00094,
			 (MDDI_VDO_PACKET_DESC_16 << 16) | mddi_vdo_packet_reg);
		else
			MDP_OUTP(MDP_BASE + 0x00094,
			 (MDDI_VDO_PACKET_DESC << 16) | mddi_vdo_packet_reg);

		MDP_OUTP(MDP_BASE + 0x00098, 0x01);
	} else {
		pipe = mddi_pipe;
	}

	/* 0 for dma_p, client_id = 0 */
	MDP_OUTP(MDP_BASE + 0x00090, 0);


	src = (uint8 *) iBuf->buf;

#ifdef WHOLESCREEN

	{
		struct fb_info *fbi;

		fbi = mfd->fbi;
		pipe->src_height = fbi->var.yres;
		pipe->src_width = fbi->var.xres;
		pipe->src_h = fbi->var.yres;
		pipe->src_w = fbi->var.xres;
		pipe->src_y = 0;
		pipe->src_x = 0;
		pipe->dst_h = fbi->var.yres;
		pipe->dst_w = fbi->var.xres;
		pipe->dst_y = 0;
		pipe->dst_x = 0;
		pipe->srcp0_addr = (uint32)src;
		pipe->srcp0_ystride = fbi->fix.line_length;
	}

#else
	if (mdp4_overlay_active(MDP4_MIXER0)) {
		struct fb_info *fbi;

		fbi = mfd->fbi;
		pipe->src_height = fbi->var.yres;
		pipe->src_width = fbi->var.xres;
		pipe->src_h = fbi->var.yres;
		pipe->src_w = fbi->var.xres;
		pipe->src_y = 0;
		pipe->src_x = 0;
		pipe->dst_h = fbi->var.yres;
		pipe->dst_w = fbi->var.xres;
		pipe->dst_y = 0;
		pipe->dst_x = 0;
		pipe->srcp0_addr = (uint32) src;
		pipe->srcp0_ystride = fbi->fix.line_length;
	} else {
		/* starting input address */
		src += (iBuf->dma_x + iBuf->dma_y * iBuf->ibuf_width)
					* iBuf->bpp;

		pipe->src_height = iBuf->dma_h;
		pipe->src_width = iBuf->dma_w;
		pipe->src_h = iBuf->dma_h;
		pipe->src_w = iBuf->dma_w;
		pipe->src_y = 0;
		pipe->src_x = 0;
		pipe->dst_h = iBuf->dma_h;
		pipe->dst_w = iBuf->dma_w;
		pipe->dst_y = iBuf->dma_y;
		pipe->dst_x = iBuf->dma_x;
		pipe->srcp0_addr = (uint32) src;
		pipe->srcp0_ystride = iBuf->ibuf_width * iBuf->bpp;
	}
#endif

	pipe->mixer_stage  = MDP4_MIXER_STAGE_BASE;

	mdp4_overlay_rgb_setup(pipe);

	mdp4_mixer_stage_up(pipe);

	mdp4_overlayproc_cfg(pipe);

	mdp4_overlay_dmap_xy(pipe);

	mdp4_overlay_dmap_cfg(mfd, 0);

	mdp4_mddi_vsync_enable(mfd, pipe, 0);

	/* MDP cmd block disable */
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);

}
Example #20
0
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
    unsigned long flag;
    int cndx = 0;
    struct vsycn_ctrl *vctrl;
    struct mdp4_overlay_pipe *pipe;


    vctrl = &vsync_ctrl_db[cndx];
    pipe = vctrl->base_pipe;

    mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

    if (mfd->ov0_wb_buf->write_addr == 0) {
        pr_info("%s: no blt_base assigned\n", __func__);
        return;
    }
#ifdef BLT_MODE_CHANGE_ISSUE
    wake_lock(&blt_mode_perf_up);
#endif
    spin_lock_irqsave(&vctrl->spin_lock, flag);
    if (enable && pipe->ov_blt_addr == 0) {
        pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
        pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
        pipe->ov_cnt = 0;
        pipe->dmap_cnt = 0;
        vctrl->ov_koff = 0;
        vctrl->ov_done = 0;
        vctrl->blt_free = 0;
        mdp4_stat.blt_dsi_video++;
        vctrl->blt_change++;
    } else if (enable == 0 && pipe->ov_blt_addr) {
        pipe->ov_blt_addr = 0;
        pipe->dma_blt_addr =  0;
        vctrl->blt_free = 4;	/* 4 commits to free wb buf */
        vctrl->blt_change++;
    }

    __DLOG__( vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

    pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__,
            vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

    if (!vctrl->blt_change) {
        spin_unlock_irqrestore(&vctrl->spin_lock, flag);
#ifdef BLT_MODE_CHANGE_ISSUE
        wake_unlock(&blt_mode_perf_up);
#endif
        return;
    }
    spin_unlock_irqrestore(&vctrl->spin_lock, flag);

    if (vctrl->blt_ctrl == BLT_SWITCH_TG_OFF) {
        int tg_enabled;

        vctrl->blt_change = 0;
        tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
        if (tg_enabled) {
            mdp4_dsi_video_wait4vsync(cndx);
            MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
            mdp4_dsi_video_wait4dmap_done(0);
        }
        mdp4_overlayproc_cfg(pipe);
        mdp4_overlay_dmap_xy(pipe);
        if (tg_enabled) {
            /*
            * need wait for more than 1 ms to
            * make sure dsi lanes' fifo is empty and
            * lanes in stop state befroe reset
            * controller
            */
            usleep(2000);
            mipi_dsi_sw_reset();
            MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
        }
    }
}
Example #21
0
static void mdp4_dtv_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int data;
	int cndx = 0;
	struct vsycn_ctrl *vctrl;
	struct mdp4_overlay_pipe *pipe;

	vctrl = &vsync_ctrl_db[cndx];
	pipe = vctrl->base_pipe;

	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER1);

	if (!mfd->ov1_wb_buf->write_addr) {
		pr_info("%s: ctrl=%d blt_base NOT assigned\n", __func__, cndx);
		return;
	}

	spin_lock_irqsave(&vctrl->spin_lock, flag);
	if (enable && pipe->ov_blt_addr == 0) {
		pipe->ov_blt_addr = mfd->ov1_wb_buf->write_addr;
		pipe->dma_blt_addr = mfd->ov1_wb_buf->read_addr;
		pipe->blt_cnt = 0;
		pipe->ov_cnt = 0;
		pipe->blt_dmap_done = 0;
		pipe->blt_ov_koff = 0;
		pipe->blt_ov_done = 0;
		mdp4_stat.blt_dtv++;
		vctrl->blt_change++;
	} else if (enable == 0 && pipe->ov_blt_addr) {
		pipe->ov_blt_addr = 0;
		pipe->dma_blt_addr = 0;
		vctrl->blt_change++;
	}

	pr_info("%s: enable=%d change=%d blt_addr=%x\n", __func__,
		enable, vctrl->blt_change, (int)pipe->ov_blt_addr);

	if (!vctrl->blt_change) {
		spin_unlock_irqrestore(&vctrl->spin_lock, flag);
		return;
	}

	atomic_set(&vctrl->suspend, 1);
	spin_unlock_irqrestore(&vctrl->spin_lock, flag);

	data = inpdw(MDP_BASE + DTV_BASE);
	data &= 0x01;
	if (data)       /* timing generator enabled */
		mdp4_dtv_wait4dmae(0);

	if (pipe->ov_blt_addr == 0) {
		MDP_OUTP(MDP_BASE + DTV_BASE, 0);       /* stop dtv */
		msleep(20);
		mdp4_overlayproc_cfg(pipe);
		mdp4_overlay_dmae_xy(pipe);
		MDP_OUTP(MDP_BASE + DTV_BASE, 1);       /* start dtv */
	}

	atomic_set(&vctrl->suspend, 0);
}
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int cndx = 0;
	struct vsycn_ctrl *vctrl;
	struct mdp4_overlay_pipe *pipe;

	vctrl = &vsync_ctrl_db[cndx];
	pipe = vctrl->base_pipe;

	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

	if (mfd->ov0_wb_buf->write_addr == 0) {
		pr_info("%s: no blt_base assigned\n", __func__);
		return;
	}

	spin_lock_irqsave(&vctrl->spin_lock, flag);
	if (enable && pipe->ov_blt_addr == 0) {
		pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
		pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
		pipe->ov_cnt = 0;
		pipe->dmap_cnt = 0;
		vctrl->ov_koff = 0;
		vctrl->ov_done = 0;
		vctrl->blt_free = 0;
		mdp4_stat.blt_dsi_video++;
		vctrl->blt_change++;
	} else if (enable == 0 && pipe->ov_blt_addr) {
		pipe->ov_blt_addr = 0;
		pipe->dma_blt_addr =  0;
		vctrl->blt_free = 4;	/* 4 commits to free wb buf */
		vctrl->blt_change++;
	}

	pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__,
		vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

	if (!vctrl->blt_change) {
		spin_unlock_irqrestore(&vctrl->spin_lock, flag);
		return;
	}

	spin_unlock_irqrestore(&vctrl->spin_lock, flag);

	if (mdp_ov0_blt_ctl == MDP4_BLT_SWITCH_TG_OFF) {
		int tg_enabled;
		long long  vtime;
		tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
		if (tg_enabled) {
			mdp4_dsi_video_wait4vsync(0, &vtime);
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
			mdp4_dsi_video_wait4dmap_done(0);
		}
		mdp4_overlayproc_cfg(pipe);
		mdp4_overlay_dmap_xy(pipe);
		vctrl->blt_change = 0;
		if (tg_enabled) {
			mipi_dsi_sw_reset();
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		}
	}
}
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
	unsigned long flag;
	int cndx = 0;
	struct vsycn_ctrl *vctrl;
	struct mdp4_overlay_pipe *pipe;

	vctrl = &vsync_ctrl_db[cndx];
	pipe = vctrl->base_pipe;

	mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

	if (mfd->ov0_wb_buf->write_addr == 0) {
		pr_info("%s: no blt_base assigned\n", __func__);
		return;
	}

	spin_lock_irqsave(&vctrl->spin_lock, flag);
	if (enable && pipe->ov_blt_addr == 0) {
		pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
		pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
		pipe->ov_cnt = 0;
		pipe->dmap_cnt = 0;
		vctrl->ov_koff = 0;
		vctrl->ov_done = 0;
		vctrl->blt_free = 0;
		mdp4_stat.blt_dsi_video++;
		vctrl->blt_change++;
	} else if (enable == 0 && pipe->ov_blt_addr) {
		pipe->ov_blt_addr = 0;
		pipe->dma_blt_addr =  0;
		vctrl->blt_free = 4;	/* 4 commits to free wb buf */
		vctrl->blt_change++;
	}

	pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__,
		vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

	if (!vctrl->blt_change) {
		spin_unlock_irqrestore(&vctrl->spin_lock, flag);
		return;
	}
	spin_unlock_irqrestore(&vctrl->spin_lock, flag);

	if (vctrl->blt_ctrl == OVERLAY_BLT_SWITCH_TG_OFF) {
		int tg_enabled;

		pr_info("%s: blt enabled by switching TG off\n", __func__);
		vctrl->blt_change = 0;
		tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
		if (tg_enabled) {
			mdp4_dsi_video_wait4vsync(cndx);
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
			mdp4_dsi_video_wait4dmap_done(0);
		}
		mdp4_overlayproc_cfg(pipe);
		mdp4_overlay_dmap_xy(pipe);
		if (pipe->ov_blt_addr) {
			mdp4_dsi_video_blt_ov_update(pipe);
			pipe->ov_cnt++;
			/* Prefill one frame */
			vsync_irq_enable(INTR_OVERLAY0_DONE,
						MDP_OVERLAY0_TERM);
			/* kickoff overlay0 engine */
			mdp4_stat.kickoff_ov0++;
			vctrl->ov_koff++;	/* make up for prefill */
			outpdw(MDP_BASE + 0x0004, 0);
		}
		if (tg_enabled) {
			/*
			 * need wait for more than 1 ms to
			 * make sure lanes' fifo is empty and
			 * lanes in stop state befroe reset
			 * controller
			 */
			usleep(2000);
			mipi_dsi_sw_reset();
			MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		}
	}
}
int mdp_lcdc_on(struct platform_device *pdev)
{
	int lcdc_width;
	int lcdc_height;
	int lcdc_bpp;
	int lcdc_border_clr;
	int lcdc_underflow_clr;
	int lcdc_hsync_skew;

	int hsync_period;
	int hsync_ctrl;
	int vsync_period;
	int display_hctl;
	int display_v_start;
	int display_v_end;
	int active_hctl;
	int active_h_start;
	int active_h_end;
	int active_v_start;
	int active_v_end;
	int ctrl_polarity;
	int h_back_porch;
	int h_front_porch;
	int v_back_porch;
	int v_front_porch;
	int hsync_pulse_width;
	int vsync_pulse_width;
	int hsync_polarity;
	int vsync_polarity;
	int data_en_polarity;
	int hsync_start_x;
	int hsync_end_x;
	uint8 *buf;
	int bpp;
	uint32 dma2_cfg_reg;
	struct fb_info *fbi;
	struct fb_var_screeninfo *var;
	struct msm_fb_data_type *mfd;
	uint32 dma_base;
	uint32 timer_base = LCDC_BASE;
	uint32 block = MDP_DMA2_BLOCK;
	int ret;
	uint32_t mask, curr;

	mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);

	if (!mfd)
		return -ENODEV;

	if (mfd->key != MFD_KEY)
		return -EINVAL;

	fbi = mfd->fbi;
	var = &fbi->var;
	vsync_cntrl.dev = mfd->fbi->dev;

	/* MDP cmd block enable */
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);

	bpp = fbi->var.bits_per_pixel / 8;
	buf = (uint8 *) fbi->fix.smem_start;

	buf += calc_fb_offset(mfd, fbi, bpp);

	dma2_cfg_reg = DMA_PACK_ALIGN_LSB | DMA_OUT_SEL_LCDC;

	if (mfd->fb_imgType == MDP_BGR_565)
		dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
	else if (mfd->fb_imgType == MDP_RGBA_8888)
		dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
	else
		dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;

	if (bpp == 2)
		dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB565;
	else if (bpp == 3)
		dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB888;
	else
		dma2_cfg_reg |= DMA_IBUF_FORMAT_xRGB8888_OR_ARGB8888;

	switch (mfd->panel_info.bpp) {
	case 24:
		dma2_cfg_reg |= DMA_DSTC0G_8BITS |
		    DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
		break;

	case 18:
		dma2_cfg_reg |= DMA_DSTC0G_6BITS |
		    DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
		break;

	case 16:
		dma2_cfg_reg |= DMA_DSTC0G_6BITS |
		    DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
		break;

	default:
		printk(KERN_ERR "mdp lcdc can't support format %d bpp!\n",
		       mfd->panel_info.bpp);
		return -ENODEV;
	}

	/* DMA register config */

	dma_base = DMA_P_BASE;

#ifdef CONFIG_FB_MSM_MDP40
	if (mfd->panel.type == HDMI_PANEL)
		dma_base = DMA_E_BASE;
#endif

	/* starting address */
	MDP_OUTP(MDP_BASE + dma_base + 0x8, (uint32) buf);
	/* active window width and height */
	MDP_OUTP(MDP_BASE + dma_base + 0x4, ((fbi->var.yres) << 16) |
						(fbi->var.xres));
	/* buffer ystride */
	MDP_OUTP(MDP_BASE + dma_base + 0xc, fbi->fix.line_length);
	/* x/y coordinate = always 0 for lcdc */
	MDP_OUTP(MDP_BASE + dma_base + 0x10, 0);
	/* dma config */
	curr = inpdw(MDP_BASE + DMA_P_BASE);
	mask = 0x0FFFFFFF;
	dma2_cfg_reg = (dma2_cfg_reg & mask) | (curr & ~mask);
	MDP_OUTP(MDP_BASE + dma_base, dma2_cfg_reg);

	/*
	 * LCDC timing setting
	 */
	h_back_porch = var->left_margin;
	h_front_porch = var->right_margin;
	v_back_porch = var->upper_margin;
	v_front_porch = var->lower_margin;
	hsync_pulse_width = var->hsync_len;
	vsync_pulse_width = var->vsync_len;
	lcdc_border_clr = mfd->panel_info.lcdc.border_clr;
	lcdc_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
	lcdc_hsync_skew = mfd->panel_info.lcdc.hsync_skew;

	lcdc_width = mfd->panel_info.xres;
	lcdc_height = mfd->panel_info.yres;
	lcdc_bpp = mfd->panel_info.bpp;

	hsync_period =
	    hsync_pulse_width + h_back_porch + lcdc_width + h_front_porch;
	hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
	hsync_start_x = hsync_pulse_width + h_back_porch;
	hsync_end_x = hsync_period - h_front_porch - 1;
	display_hctl = (hsync_end_x << 16) | hsync_start_x;

	vsync_period =
	    (vsync_pulse_width + v_back_porch + lcdc_height +
	     v_front_porch) * hsync_period;
	display_v_start =
	    (vsync_pulse_width + v_back_porch) * hsync_period + lcdc_hsync_skew;
	display_v_end =
	    vsync_period - (v_front_porch * hsync_period) + lcdc_hsync_skew - 1;

	if (lcdc_width != var->xres) {
		active_h_start = hsync_start_x + first_pixel_start_x;
		active_h_end = active_h_start + var->xres - 1;
		active_hctl =
		    ACTIVE_START_X_EN | (active_h_end << 16) | active_h_start;
	} else {
		active_hctl = 0;
	}

	if (lcdc_height != var->yres) {
		active_v_start =
		    display_v_start + first_pixel_start_y * hsync_period;
		active_v_end = active_v_start + (var->yres) * hsync_period - 1;
		active_v_start |= ACTIVE_START_Y_EN;
	} else {
		active_v_start = 0;
		active_v_end = 0;
	}


#ifdef CONFIG_FB_MSM_MDP40
	if (mfd->panel.type == HDMI_PANEL) {
		block = MDP_DMA_E_BLOCK;
		timer_base = DTV_BASE;
		hsync_polarity = 0;
		vsync_polarity = 0;
	} else {
		hsync_polarity = 1;
		vsync_polarity = 1;
	}

	lcdc_underflow_clr |= 0x80000000;	/* enable recovery */
#else
	hsync_polarity = 0;
	vsync_polarity = 0;
#endif
	data_en_polarity = 0;

	ctrl_polarity =
	    (data_en_polarity << 2) | (vsync_polarity << 1) | (hsync_polarity);

	MDP_OUTP(MDP_BASE + timer_base + 0x4, hsync_ctrl);
	MDP_OUTP(MDP_BASE + timer_base + 0x8, vsync_period);
	MDP_OUTP(MDP_BASE + timer_base + 0xc, vsync_pulse_width * hsync_period);
	if (timer_base == LCDC_BASE) {
		MDP_OUTP(MDP_BASE + timer_base + 0x10, display_hctl);
		MDP_OUTP(MDP_BASE + timer_base + 0x14, display_v_start);
		MDP_OUTP(MDP_BASE + timer_base + 0x18, display_v_end);
		MDP_OUTP(MDP_BASE + timer_base + 0x28, lcdc_border_clr);
		MDP_OUTP(MDP_BASE + timer_base + 0x2c, lcdc_underflow_clr);
		MDP_OUTP(MDP_BASE + timer_base + 0x30, lcdc_hsync_skew);
		MDP_OUTP(MDP_BASE + timer_base + 0x38, ctrl_polarity);
		MDP_OUTP(MDP_BASE + timer_base + 0x1c, active_hctl);
		MDP_OUTP(MDP_BASE + timer_base + 0x20, active_v_start);
		MDP_OUTP(MDP_BASE + timer_base + 0x24, active_v_end);
	} else {
		MDP_OUTP(MDP_BASE + timer_base + 0x18, display_hctl);
		MDP_OUTP(MDP_BASE + timer_base + 0x1c, display_v_start);
		MDP_OUTP(MDP_BASE + timer_base + 0x20, display_v_end);
		MDP_OUTP(MDP_BASE + timer_base + 0x40, lcdc_border_clr);
		MDP_OUTP(MDP_BASE + timer_base + 0x44, lcdc_underflow_clr);
		MDP_OUTP(MDP_BASE + timer_base + 0x48, lcdc_hsync_skew);
		MDP_OUTP(MDP_BASE + timer_base + 0x50, ctrl_polarity);
		MDP_OUTP(MDP_BASE + timer_base + 0x2c, active_hctl);
		MDP_OUTP(MDP_BASE + timer_base + 0x30, active_v_start);
		MDP_OUTP(MDP_BASE + timer_base + 0x38, active_v_end);
	}

	ret = panel_next_on(pdev);
	if (ret == 0) {
		/* enable LCDC block */
		MDP_OUTP(MDP_BASE + timer_base, 1);
		mdp_pipe_ctrl(block, MDP_BLOCK_POWER_ON, FALSE);
	}
	/* MDP cmd block disable */
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);

	return ret;
}
/*
 * make sure the MIPI_DSI_WRITEBACK_SIZE defined at boardfile
 * has enough space h * w * 3 * 2
 */
static void mdp4_dsi_video_do_blt(struct msm_fb_data_type *mfd, int enable)
{
    unsigned long flag;
    int cndx = 0;
    struct vsycn_ctrl *vctrl;
    struct mdp4_overlay_pipe *pipe;
    long long vtime;

    vctrl = &vsync_ctrl_db[cndx];
    pipe = vctrl->base_pipe;

    mdp4_allocate_writeback_buf(mfd, MDP4_MIXER0);

    if (mfd->ov0_wb_buf->write_addr == 0) {
        pr_info("%s: no blt_base assigned\n", __func__);
        return;
    }

    spin_lock_irqsave(&vctrl->spin_lock, flag);
    if (enable && pipe->ov_blt_addr == 0) {
        pipe->ov_blt_addr = mfd->ov0_wb_buf->write_addr;
        pipe->dma_blt_addr = mfd->ov0_wb_buf->read_addr;
        pipe->ov_cnt = 0;
        pipe->dmap_cnt = 0;
        vctrl->ov_koff = 0;
        vctrl->ov_done = 0;
        vctrl->blt_free = 0;
        mdp4_stat.blt_dsi_video++;
        vctrl->blt_change++;
    } else if (enable == 0 && pipe->ov_blt_addr) {
        pipe->ov_blt_addr = 0;
        pipe->dma_blt_addr =  0;
        vctrl->blt_free = 4;	/* 4 commits to free wb buf */
        vctrl->blt_change++;
    }

    pr_info("%s: changed=%d enable=%d ov_blt_addr=%x\n", __func__,
            vctrl->blt_change, enable, (int)pipe->ov_blt_addr);

    if (!vctrl->blt_change) {
        spin_unlock_irqrestore(&vctrl->spin_lock, flag);
        return;
    }

    if (vctrl->blt_ctrl == BLT_SWITCH_TG_OFF) // QC_1204
        vctrl->blt_change = 0; // QC_1204

    spin_unlock_irqrestore(&vctrl->spin_lock, flag);

    // QC_1206 - start
    if (enable && pipe->ov_blt_addr) {
        size_t blt_vm_size;
        char *blt_vm_addr;
        unsigned long ionflag = 0;
        int rc = -1;

        blt_vm_size = roundup(mfd->panel_info.xres * \
                              mfd->panel_info.yres * 3 * 2, SZ_4K);

        if (!IS_ERR_OR_NULL(mfd->iclient)) {
            rc = ion_handle_get_flags(mfd->iclient,
                                      mfd->ov0_wb_buf->ihdl,
                                      &ionflag);
            pr_err("*** %s: rc=%x\n", __func__, rc); // QC_1207

            if (!rc) {
                blt_vm_addr = (char *) ion_map_kernel(
                                  mfd->iclient,
                                  mfd->ov0_wb_buf->ihdl,
                                  ionflag);
                pr_err("*** %s: blt_vm_addr=%x\n", __func__, (unsigned int)blt_vm_addr); // QC_1207
                if (blt_vm_addr) {
                    pr_err("*** %s: Calling memset() with blt_vm_size=%d\n", __func__, blt_vm_size); // QC_1207
                    memset(blt_vm_addr, 0, blt_vm_size);
                    ion_unmap_kernel(mfd->iclient,
                                     mfd->ov0_wb_buf->ihdl);
                }
            }
        }
    }
    // QC_1206 - end

    if (vctrl->blt_ctrl == BLT_SWITCH_TG_OFF) {
        int tg_enabled;

        vctrl->blt_change = 0;
        tg_enabled = inpdw(MDP_BASE + DSI_VIDEO_BASE) & 0x01;
        if (tg_enabled) {
            vsync_irq_enable(INTR_PRIMARY_VSYNC, MDP_PRIM_VSYNC_TERM);
            mdp4_dsi_video_wait4vsync(0, &vtime);
            MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
            mdp4_dsi_video_wait4dmap_done(0);
        }
        mdp4_overlayproc_cfg(pipe);
        mdp4_overlay_dmap_xy(pipe);
        if (tg_enabled) {
            /*
            * need wait for more than 1 ms to
            * make sure dsi lanes' fifo is empty and
            * lanes in stop state befroe reset
            * controller
            */
            usleep(2000);
            mipi_dsi_sw_reset();
            MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
        }
    }
}
Example #26
0
int mdp4_overlay_writeback_on(struct platform_device *pdev)
{
	struct msm_fb_data_type *mfd;
	struct fb_info *fbi;
	uint8 *buf;
	struct mdp4_overlay_pipe *pipe;
	int bpp;
	int ret;
	uint32 data;

	mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);

	if (!mfd)
		return -ENODEV;

	if (mfd->key != MFD_KEY)
		return -EINVAL;

	writeback_mfd = mfd;		  /* keep it */

	fbi = mfd->fbi;

	bpp = fbi->var.bits_per_pixel / 8;
	buf = (uint8 *) fbi->fix.smem_start;
	buf += fbi->var.xoffset * bpp +
		fbi->var.yoffset * fbi->fix.line_length;

	/* MDP cmd block enable */
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);

	if (writeback_pipe == NULL) {
		pipe = mdp4_overlay_pipe_alloc(OVERLAY_TYPE_BF, MDP4_MIXER2);
		if (pipe == NULL)
			pr_info("%s: pipe_alloc failed\n", __func__);
		pipe->pipe_used++;
		pipe->mixer_stage  = MDP4_MIXER_STAGE_BASE;
		pipe->mixer_num  = MDP4_MIXER2;
		pipe->src_format = MDP_ARGB_8888;
		mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_WRITEBACK);
		ret = mdp4_overlay_format2pipe(pipe);
		if (ret < 0)
			pr_info("%s: format2type failed\n", __func__);

		writeback_pipe = pipe; /* keep it */

	} else {
		pipe = writeback_pipe;
	}
	ret = panel_next_on(pdev);
	/* MDP_LAYERMIXER_WB_MUX_SEL to use mixer1 axi for mixer2 writeback */
	data = inpdw(MDP_BASE + 0x100F4);
	data &= ~0x02; /* clear the mixer1 mux bit */
	data |= 0x02;
	outpdw(MDP_BASE + 0x100F4, data);
	MDP_OUTP(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x5004,
		((0x0 & 0xFFF) << 16) | /* 12-bit B */
			(0x0 & 0xFFF));         /* 12-bit G */
	/* MSP_BORDER_COLOR */
	MDP_OUTP(MDP_BASE + MDP4_OVERLAYPROC1_BASE + 0x5008,
		(0x0 & 0xFFF));         /* 12-bit R */

	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
	return ret;
}
int mdp4_dsi_video_pipe_commit(int cndx, int wait)
{
    static uint32 frameDropCnt = 0; // QC_1206
    int lmCfg; // QC_1204
    int  i, undx;
    int mixer = 0;
    struct vsycn_ctrl *vctrl;
    struct vsync_update *vp;
    struct mdp4_overlay_pipe *pipe;
    struct mdp4_overlay_pipe *real_pipe;
    unsigned long flags;
    int cnt = 0;

    vctrl = &vsync_ctrl_db[cndx];

    mutex_lock(&vctrl->update_lock);
    undx =  vctrl->update_ndx;
    vp = &vctrl->vlist[undx];
    pipe = vctrl->base_pipe;
    mixer = pipe->mixer_num;

    if (vp->update_cnt == 0) {
        mutex_unlock(&vctrl->update_lock);
        return cnt;
    }

    vctrl->update_ndx++;
    vctrl->update_ndx &= 0x01;
    vp->update_cnt = 0;     /* reset */
    if (vctrl->blt_free) {
        vctrl->blt_free--;
//		if (vctrl->blt_free == 0)
//			mdp4_free_writeback_buf(vctrl->mfd, mixer);
    }
    mutex_unlock(&vctrl->update_lock);

    /* free previous committed iommu back to pool */
    mdp4_overlay_iommu_unmap_freelist(mixer);

    spin_lock_irqsave(&vctrl->spin_lock, flags);


    if (vctrl->ov_koff != vctrl->ov_done) {
        frameDropCnt++; // QC_1206
        spin_unlock_irqrestore(&vctrl->spin_lock, flags);
        pr_err("%s: Error, frame dropped %d %d\n", __func__,
               vctrl->ov_koff, vctrl->ov_done);


        if (frameDropCnt >= 2) { // QC_1206
            mdp4_dump_regs(); // QC_1205
            lmCfg = inpdw(MDP_BASE + 0x10100); // QC_1204
            pr_err("*** %s: lmCfg=%x, frameDropCnt=%d\n", __func__, lmCfg, frameDropCnt); // QC_1204

            // retry ov0
            pr_err("*** %s: Retrying OV0\n", __func__); // QC_1204
            INIT_COMPLETION(vctrl->ov_comp); // QC_1204
            vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM); // QC_1204
            mb(); // QC_1204
            outpdw(MDP_BASE + 0x0004, 0); // QC_1204
        }
        return 0;
    } else {
        frameDropCnt = 0; // QC_1206
    }

    spin_unlock_irqrestore(&vctrl->spin_lock, flags);

    mdp4_overlay_mdp_perf_upd(vctrl->mfd, 1);

    if (vctrl->blt_change) {
        pipe = vctrl->base_pipe;
        spin_lock_irqsave(&vctrl->spin_lock, flags);
        INIT_COMPLETION(vctrl->dmap_comp);
        INIT_COMPLETION(vctrl->ov_comp);
        vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
        spin_unlock_irqrestore(&vctrl->spin_lock, flags);
        mdp4_dsi_video_wait4dmap(0);
        if (pipe->ov_blt_addr)
            mdp4_dsi_video_wait4ov(0);
    }

    pipe = vp->plist;

    for (i = 0; i < OVERLAY_PIPE_MAX; i++, pipe++) {
        if (pipe->pipe_used) {
            cnt++;
            real_pipe = mdp4_overlay_ndx2pipe(pipe->pipe_ndx);
            if (real_pipe && real_pipe->pipe_used) {
                /* pipe not unset */
                mdp4_overlay_vsync_commit(pipe);
            }
            /* free previous iommu to freelist
            * which will be freed at next
            * pipe_commit
            */
            mdp4_overlay_iommu_pipe_free(pipe->pipe_ndx, 0);
            pipe->pipe_used = 0; /* clear */
        }
    }

    mdp4_mixer_stage_commit(mixer);

    /* start timing generator & mmu if they are not started yet */
    mdp4_overlay_dsi_video_start();

    pipe = vctrl->base_pipe;
    spin_lock_irqsave(&vctrl->spin_lock, flags);
    if (pipe->ov_blt_addr) {
        mdp4_dsi_video_blt_ov_update(pipe);
        pipe->ov_cnt++;
        INIT_COMPLETION(vctrl->ov_comp);
        vsync_irq_enable(INTR_OVERLAY0_DONE, MDP_OVERLAY0_TERM);
        mb();
        vctrl->ov_koff++;

        pr_err("*** %s: vctrl->ov_koff++=%d\n", __func__, vctrl->ov_koff); // QC_1204

        lmCfg = inpdw(MDP_BASE + 0x10100); // QC_1204
        pr_err("*** %s: lmCfg=%x\n", __func__, lmCfg); // QC_1204


        /* kickoff overlay engine */
        mdp4_stat.kickoff_ov0++;
        outpdw(MDP_BASE + 0x0004, 0);
    } else {
        /* schedule second phase update  at dmap */
        INIT_COMPLETION(vctrl->dmap_comp);
        vsync_irq_enable(INTR_DMA_P_DONE, MDP_DMAP_TERM);
    }
    spin_unlock_irqrestore(&vctrl->spin_lock, flags);

    mdp4_stat.overlay_commit[pipe->mixer_num]++;

    if (wait) {
        if (pipe->ov_blt_addr)
            mdp4_dsi_video_wait4ov(0);
        else
            mdp4_dsi_video_wait4dmap(0);
    }

    return cnt;
}
Example #28
0
void lut_tune(int num, unsigned int *pLutTable)
{
	__u16 *r, *g, *b, i;
	int j;
	struct fb_info *info;
	struct fb_cmap test_cmap;
	struct fb_cmap *cmap;
	struct msm_fb_data_type *mfd;
	uint32_t out;

	/*for final assignment*/
	u16 r_1, g_1, b_1;

	info = registered_fb[0];

	cmap = &test_cmap;
	/*=====================================
	* cmap allocation
	=====================================*/
	cmap->red = 0;
	cmap->green = 0;
	cmap->blue = 0;
	cmap->transp = 0;
	cmap->start = 0;
	cmap->len = num;	/*MAX_LUT_SIZE;//LUT has 256 entries*/
	cmap->red = kmalloc(cmap->len * sizeof(__u16), GFP_KERNEL);
	if (!cmap->red) {
		printk(KERN_ERR "can't malloc cmap!");
		goto fail_rest;
	}

	cmap->green = kmalloc(cmap->len * sizeof(__u16), GFP_KERNEL);
	if (!cmap->green) {
		printk(KERN_ERR "can't malloc cmap!");
		goto fail_rest;
	}

	cmap->blue = kmalloc(cmap->len * sizeof(__u16), GFP_KERNEL);
	if (!cmap->blue) {
		printk(KERN_ERR "can't malloc cmap!");
		goto fail_rest;
	}
	r = cmap->red;
	g = cmap->green;
	b = cmap->blue;

	j = 0;
	DPRINT("cmap->len %d\n", cmap->len);
	/* Assigning the cmap */
	for (i = 0; i < cmap->len; i++) {
		*r++ = pLutTable[j++];
		*g++ = pLutTable[j++];
		*b++ = pLutTable[j++];
	}

	/*instead of an ioctl */
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
#if defined(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_WVGA_PT) \
	|| defined(CONFIG_FB_MSM_MIPI_NOVATEK_BOE_CMD_WVGA_PT) \
	|| defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_CMD_QHD_PT)
	mdp_clk_ctrl(1);
#endif
	j = 0;
	for (i = 0; i < cmap->len; i++) {
		r_1 = pLutTable[j++];
		g_1 = pLutTable[j++];
		b_1 = pLutTable[j++];

#ifdef CONFIG_FB_MSM_MDP40
		MDP_OUTP(MDP_BASE + 0x94800 +
#else
		MDP_OUTP(MDP_BASE + 0x93800 +
#endif
			(0x400 * mdp_lut_i) + cmap->start * 4 + i * 4,
			((g_1 & 0xff) |
			((b_1 & 0xff) << 8) | ((r_1 & 0xff) << 16)));
	}

	mfd = (struct msm_fb_data_type *) registered_fb[0]->par;
	if (mfd->panel.type == MIPI_CMD_PANEL) {
#if defined(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_WVGA_PT) \
			|| defined(CONFIG_FB_MSM_MIPI_NOVATEK_BOE_CMD_WVGA_PT) \
			|| defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_CMD_QHD_PT)
		mdp_clk_ctrl(0);
#endif
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
		mutex_lock(&mdp_lut_push_sem);
		mdp_lut_push = 1;
		mdp_lut_push_i = mdp_lut_i;
		mutex_unlock(&mdp_lut_push_sem);
	} else {
		/*mask off non LUT select bits*/
		out = inpdw(MDP_BASE + 0x90070) & ~((0x1 << 10) | 0x7);
		MDP_OUTP(MDP_BASE + 0x90070, (mdp_lut_i << 10) | 0x7 | out);
#if defined(CONFIG_FB_MSM_MIPI_NOVATEK_CMD_WVGA_PT) \
					|| defined(CONFIG_FB_MSM_MIPI_NOVATEK_BOE_CMD_WVGA_PT) \
					|| defined(CONFIG_FB_MSM_MIPI_SAMSUNG_OLED_CMD_QHD_PT)
		mdp_clk_ctrl(0);
#endif
		mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);
	}

	mdp_lut_i = (mdp_lut_i + 1)%2;
fail_rest:
	free_cmap(cmap);
	/*close(fb);*/
}
int mdp_dsi_video_on(struct platform_device *pdev)
{
	int dsi_width;
	int dsi_height;
	int dsi_bpp;
	int dsi_border_clr;
	int dsi_underflow_clr;
	int dsi_hsync_skew;

	int hsync_period;
	int hsync_ctrl;
	int vsync_period;
	int display_hctl;
	int display_v_start;
	int display_v_end;
	int active_hctl;
	int active_h_start;
	int active_h_end;
	int active_v_start;
	int active_v_end;
	int ctrl_polarity;
	int h_back_porch;
	int h_front_porch;
	int v_back_porch;
	int v_front_porch;
	int hsync_pulse_width;
	int vsync_pulse_width;
	int hsync_polarity;
	int vsync_polarity;
	int data_en_polarity;
	int hsync_start_x;
	int hsync_end_x;
	uint8 *buf;
	uint32 dma2_cfg_reg;

	int bpp;
	struct fb_info *fbi;
	struct fb_var_screeninfo *var;
	struct msm_fb_data_type *mfd;
	int ret;
	uint32_t mask, curr;

	mfd = (struct msm_fb_data_type *)platform_get_drvdata(pdev);

	if (!mfd)
		return -ENODEV;

	if (mfd->key != MFD_KEY)
		return -EINVAL;

	fbi = mfd->fbi;
	var = &fbi->var;

	vsync_cntrl.dev = mfd->fbi->dev;
	atomic_set(&vsync_cntrl.suspend, 0);
	vsync_cntrl.vsync_irq_enabled = 0;
	bpp = fbi->var.bits_per_pixel / 8;
	buf = (uint8 *) fbi->fix.smem_start;

	buf += calc_fb_offset(mfd, fbi, bpp);

	dma2_cfg_reg = DMA_PACK_ALIGN_LSB | DMA_OUT_SEL_DSI_VIDEO;

	if (mfd->fb_imgType == MDP_BGR_565)
		dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
	else if (mfd->fb_imgType == MDP_RGBA_8888)
		dma2_cfg_reg |= DMA_PACK_PATTERN_BGR;
	else
		dma2_cfg_reg |= DMA_PACK_PATTERN_RGB;

	if (bpp == 2)
		dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB565;
	else if (bpp == 3)
		dma2_cfg_reg |= DMA_IBUF_FORMAT_RGB888;
	else
		dma2_cfg_reg |= DMA_IBUF_FORMAT_xRGB8888_OR_ARGB8888;

	switch (mfd->panel_info.bpp) {
	case 24:
		dma2_cfg_reg |= DMA_DSTC0G_8BITS |
			DMA_DSTC1B_8BITS | DMA_DSTC2R_8BITS;
		break;
	case 18:
		dma2_cfg_reg |= DMA_DSTC0G_6BITS |
			DMA_DSTC1B_6BITS | DMA_DSTC2R_6BITS;
		break;
	case 16:
		dma2_cfg_reg |= DMA_DSTC0G_6BITS |
			DMA_DSTC1B_5BITS | DMA_DSTC2R_5BITS;
		break;
	default:
		printk(KERN_ERR "mdp lcdc can't support format %d bpp!\n",
			mfd->panel_info.bpp);
		return -ENODEV;
	}
	/* MDP cmd block enable */
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_ON, FALSE);


	/* starting address */
	MDP_OUTP(MDP_BASE + DMA_P_BASE + 0x8, (uint32) buf);

	/* active window width and height */
	MDP_OUTP(MDP_BASE + DMA_P_BASE + 0x4, ((fbi->var.yres) << 16) |
		(fbi->var.xres));

	/* buffer ystride */
	MDP_OUTP(MDP_BASE + DMA_P_BASE + 0xc, fbi->fix.line_length);

	/* x/y coordinate = always 0 for lcdc */
	MDP_OUTP(MDP_BASE + DMA_P_BASE + 0x10, 0);

	/* dma config */
	curr = inpdw(MDP_BASE + DMA_P_BASE);
	mask = 0x0FFFFFFF;
	dma2_cfg_reg = (dma2_cfg_reg & mask) | (curr & ~mask);
	MDP_OUTP(MDP_BASE + DMA_P_BASE, dma2_cfg_reg);

	/*
	 * DSI timing setting
	 */
	h_back_porch = var->left_margin;
	h_front_porch = var->right_margin;
	v_back_porch = var->upper_margin;
	v_front_porch = var->lower_margin;
	hsync_pulse_width = var->hsync_len;
	vsync_pulse_width = var->vsync_len;
	dsi_border_clr = mfd->panel_info.lcdc.border_clr;
	dsi_underflow_clr = mfd->panel_info.lcdc.underflow_clr;
	dsi_hsync_skew = mfd->panel_info.lcdc.hsync_skew;
	dsi_width = mfd->panel_info.xres;
	dsi_height = mfd->panel_info.yres;
	dsi_bpp = mfd->panel_info.bpp;
	hsync_period = h_back_porch + dsi_width + h_front_porch + 1;
	hsync_ctrl = (hsync_period << 16) | hsync_pulse_width;
	hsync_start_x = h_back_porch;
	hsync_end_x = dsi_width + h_back_porch - 1;
	display_hctl = (hsync_end_x << 16) | hsync_start_x;

	vsync_period =
		(v_back_porch + dsi_height + v_front_porch + 1) * hsync_period;
	display_v_start = v_back_porch * hsync_period + dsi_hsync_skew;
	display_v_end = (dsi_height + v_back_porch) * hsync_period;

	active_h_start = hsync_start_x + first_pixel_start_x;
	active_h_end = active_h_start + var->xres - 1;
	active_hctl = ACTIVE_START_X_EN |
			(active_h_end << 16) | active_h_start;

	active_v_start = display_v_start +
			first_pixel_start_y * hsync_period;
	active_v_end = active_v_start +	(var->yres) * hsync_period - 1;
	active_v_start |= ACTIVE_START_Y_EN;

	dsi_underflow_clr |= 0x80000000;	/* enable recovery */
	hsync_polarity = 0;
	vsync_polarity = 0;
	data_en_polarity = 0;

	ctrl_polarity =	(data_en_polarity << 2) |
		(vsync_polarity << 1) | (hsync_polarity);

	if (!(mfd->cont_splash_done)) {
		mdp_pipe_ctrl(MDP_CMD_BLOCK,
			MDP_BLOCK_POWER_OFF, FALSE);
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 0);
		mipi_dsi_controller_cfg(0);
	}

	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x4, hsync_ctrl);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x8, vsync_period);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0xc, vsync_pulse_width);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x10, display_hctl);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x14, display_v_start);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x18, display_v_end);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x1c, active_hctl);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x20, active_v_start);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x24, active_v_end);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x28, dsi_border_clr);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x2c, dsi_underflow_clr);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x30, dsi_hsync_skew);
	MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE + 0x38, ctrl_polarity);

	ret = panel_next_on(pdev);
	if (ret == 0) {
		/* enable DSI block */
		MDP_OUTP(MDP_BASE + DSI_VIDEO_BASE, 1);
		/*Turning on DMA_P block*/
		mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_ON, FALSE);
	}
	mdp_histogram_ctrl_all(TRUE);
	/* MDP cmd block disable */
	mdp_pipe_ctrl(MDP_CMD_BLOCK, MDP_BLOCK_POWER_OFF, FALSE);

	return ret;
}
void mdp4_overlay_update_mddi(struct msm_fb_data_type *mfd)
{
	int ptype;
	uint32 mddi_ld_param;
	uint16 mddi_vdo_packet_reg;
	struct mdp4_overlay_pipe *pipe;
	uint32	data;
	int ret;
	int cndx = 0;
	struct vsycn_ctrl *vctrl;

	if (mfd->key != MFD_KEY)
		return;

	vctrl = &vsync_ctrl_db[cndx];

	if (vctrl->base_pipe == NULL) {
		ptype = mdp4_overlay_format2type(mfd->fb_imgType);

		if (ptype < 0)
			pr_info("%s: format2type failed\n", __func__);

		pipe = mdp4_overlay_pipe_alloc(ptype, MDP4_MIXER0);
		if (pipe == NULL) {
			pr_info("%s: pipe_alloc failed\n", __func__);
			return;
		}
		pipe->pipe_used++;
		pipe->mixer_stage  = MDP4_MIXER_STAGE_BASE;
		pipe->mixer_num  = MDP4_MIXER0;
		pipe->src_format = mfd->fb_imgType;
		mdp4_overlay_panel_mode(pipe->mixer_num, MDP4_PANEL_MDDI);
		ret = mdp4_overlay_format2pipe(pipe);
		if (ret < 0)
			pr_info("%s: format2type failed\n", __func__);

		vctrl->base_pipe = pipe; /* keep it */
		mdp4_init_writeback_buf(mfd, MDP4_MIXER0);
		pipe->ov_blt_addr = 0;
		pipe->dma_blt_addr = 0;
	} else {
		pipe = vctrl->base_pipe;
	}

	MDP_OUTP(MDP_BASE + 0x021c, 10); /* read pointer */

	mddi_ld_param = 0;
	mddi_vdo_packet_reg = mfd->panel_info.mddi.vdopkt;

	if (mdp_hw_revision == MDP4_REVISION_V2_1) {
		data = inpdw(MDP_BASE + 0x0028);
		data &= ~0x0300;	/* bit 8, 9, MASTER4 */
		if (mfd->fbi->var.xres == 540) /* qHD, 540x960 */
			data |= 0x0200;
		else
			data |= 0x0100;

			MDP_OUTP(MDP_BASE + 0x00028, data);
	}

	if (mfd->panel_info.type == MDDI_PANEL) {
		if (mfd->panel_info.pdest == DISPLAY_1)
			mddi_ld_param = 0;
		else
			mddi_ld_param = 1;
	} else {
		mddi_ld_param = 2;
	}

	MDP_OUTP(MDP_BASE + 0x00090, mddi_ld_param);

	if (mfd->panel_info.bpp == 24)
		MDP_OUTP(MDP_BASE + 0x00094,
		 (MDDI_VDO_PACKET_DESC_24 << 16) | mddi_vdo_packet_reg);
	else if (mfd->panel_info.bpp == 16)
		MDP_OUTP(MDP_BASE + 0x00094,
		 (MDDI_VDO_PACKET_DESC_16 << 16) | mddi_vdo_packet_reg);
	else
		MDP_OUTP(MDP_BASE + 0x00094,
		 (MDDI_VDO_PACKET_DESC << 16) | mddi_vdo_packet_reg);

		MDP_OUTP(MDP_BASE + 0x00098, 0x01);


	mdp4_overlay_setup_pipe_addr(mfd, pipe);

	mdp4_overlay_rgb_setup(pipe);

	mdp4_overlay_reg_flush(pipe, 1);

	mdp4_mixer_stage_up(pipe, 0);

	mdp4_overlayproc_cfg(pipe);

	mdp4_overlay_dmap_xy(pipe);

	mdp4_overlay_dmap_cfg(mfd, 0);

	mdp4_mixer_stage_commit(pipe->mixer_num);

	wmb();
}