static void opti_write_reg(struct ata_port *ap, u8 val, int reg)
{
void __iomem *regio = ap->ioaddr.cmd_addr;
/* These 3 unlock the control register access */
ioread16(regio + 1);
ioread16(regio + 1);
iowrite8(3, regio + 2);
/* Do the I/O */
iowrite8(val, regio + reg);
/* Relock */
iowrite8(0x83, regio + 2);
}
static int _qc_data_upload(struct pld_link_device *pld,
struct dpram_udl_param *param)
{
struct qc_dpram_boot_map *qbt_map = &pld->qc_bt_map;
int retval = 0;
u16 intval = 0;
int count = 0;
while (1) {
if (!gpio_get_value(pld->gpio_dpram_int)) {
intval = pld->recv_intr(pld);
if (intval == 0xDBAB) {
break;
} else {
mif_err("intr 0x%08x\n", intval);
return -1;
}
}
usleep_range(1000, 2000);
count++;
if (count > 200) {
mif_err("<%s:%d>\n", __func__, __LINE__);
return -1;
}
}
iowrite16(PLD_ADDR_MASK(&qbt_map->frame_size[0]),
pld->address_buffer);
param->size = ioread16(pld->base);
iowrite16(PLD_ADDR_MASK(&qbt_map->tag[0]),
pld->address_buffer);
param->tag = ioread16(pld->base);
iowrite16(PLD_ADDR_MASK(&qbt_map->count[0]),
pld->address_buffer);
param->count = ioread16(pld->base);
iowrite16(PLD_ADDR_MASK(&qbt_map->buff[0]),
pld->address_buffer);
memcpy(param->addr, pld->base, param->size);
pld->send_intr(pld, 0xDB12);
return retval;
}
u16 pci_read16(struct flink_device* fdev, u32 addr) {
struct flink_pci_data* pci_data = (struct flink_pci_data*)fdev->bus_data;
if(pci_data != NULL) {
return ioread16(pci_data->base_addr + addr);
}
return 0;
}
int vnic_dev_spec(struct vnic_dev *vdev, unsigned int offset, unsigned int size,
void *value)
{
#ifdef CONFIG_MIPS
u8 *v = vnic_dev_get_res(vdev, RES_TYPE_DEV, 0);
if (!v) {
pr_err("vNIC device-specific region not found.\n");
return -EINVAL;
}
switch (size) {
case 1:
*(u8 *)value = ioread8(v + offset);
break;
case 2:
*(u16 *)value = ioread16(v + offset);
break;
case 4:
*(u32 *)value = ioread32(v + offset);
break;
case 8:
*(u64 *)value = readq(v + offset);
break;
default:
BUG();
break;
}
return 0;
#else
u64 a0, a1;
int wait = 1000;
int err;
a0 = offset;
a1 = size;
err = vnic_dev_cmd(vdev, CMD_DEV_SPEC, &a0, &a1, wait);
switch (size) {
case 1:
*(u8 *)value = (u8)a0;
break;
case 2:
*(u16 *)value = (u16)a0;
break;
case 4:
*(u32 *)value = (u32)a0;
break;
case 8:
*(u64 *)value = a0;
break;
default:
BUG();
break;
}
return err;
#endif
}
int softing_bootloader_command(struct softing *card, int16_t cmd,
const char *msg)
{
int ret;
unsigned long stamp;
iowrite16(RES_NONE, &card->dpram[DPRAM_RECEIPT]);
iowrite16(cmd, &card->dpram[DPRAM_COMMAND]);
wmb();
stamp = jiffies + 3 * HZ;
do {
ret = ioread16(&card->dpram[DPRAM_RECEIPT]);
rmb();
if (ret == RES_OK)
return 0;
if (time_after(jiffies, stamp))
break;
usleep_range(500, 10000);
} while (!signal_pending(current));
ret = (ret == RES_NONE) ? -ETIMEDOUT : -ECANCELED;
dev_alert(&card->pdev->dev, "bootloader %s failed (%i)\n", msg, ret);
return ret;
}
static int _softing_fct_cmd(struct softing *card, int16_t cmd, uint16_t vector,
const char *msg)
{
int ret;
unsigned long stamp;
iowrite16(cmd, &card->dpram[DPRAM_FCT_PARAM]);
iowrite8(vector >> 8, &card->dpram[DPRAM_FCT_HOST + 1]);
iowrite8(vector, &card->dpram[DPRAM_FCT_HOST]);
wmb();
stamp = jiffies + 1 * HZ;
do {
ret = ioread8(&card->dpram[DPRAM_FCT_HOST]) +
(ioread8(&card->dpram[DPRAM_FCT_HOST + 1]) << 8);
rmb();
if (ret == RES_OK)
return ioread16(&card->dpram[DPRAM_FCT_RESULT]);
if ((ret != vector) || time_after(jiffies, stamp))
break;
usleep_range(500, 10000);
} while (1);
ret = (ret == RES_NONE) ? -ETIMEDOUT : -ECANCELED;
dev_alert(&card->pdev->dev, "firmware %s failed (%i)\n", msg, ret);
return ret;
}
static void __iomem *sdk7786_fpga_probe(void)
{
unsigned long area;
void __iomem *base;
/*
*/
for (area = PA_AREA0; area < PA_AREA7; area += SZ_64M) {
base = ioremap_nocache(area + FPGA_REGS_OFFSET, FPGA_REGS_SIZE);
if (!base) {
/* */
continue;
}
if (ioread16(base + SRSTR) == SRSTR_MAGIC)
return base; /* */
iounmap(base);
}
return NULL;
}
static inline u16 recv_intr(struct dpram_link_device *dpld)
{
if (dpld->dpctl->recv_intr)
return dpld->dpctl->recv_intr();
else
return ioread16(dpld->mbx2ap);
}
static inline size_t fifo_eim_rx_ready(struct ccat_eth_fifo *const fifo)
{
static const size_t OVERHEAD = sizeof(struct ccat_eim_frame_hdr);
const size_t len = ioread16(&fifo->eim.next->hdr.length);
return (len < OVERHEAD) ? 0 : len - OVERHEAD;
}
//return 0 means success
static int probe(struct pci_dev *dev, const struct pci_device_id *id)
{
/* Do probing type stuff here. Like calling request_region(); */
//lin: unsigned char revision_id;
unsigned long len;
void __iomem *addressio;
int bar ;
if(skel_get_revision(dev) != MEM_PCI_REVISION_ID)
return 1;
if (pci_enable_device(dev) < 0) {
return 1;
}
bar = 1;
//lin: resource_size_t start = pci_resource_start(dev, bar);
len = pci_resource_len(dev, bar);
//lin: unsigned long flags = pci_resource_flags(dev, bar);
addressio = pci_iomap(dev,bar,len);
if (addressio == NULL) {
return 1;
}
//*(byte *)addressio = 0x57;
//iowrite8(0x89,addressio + 8);
//printk("%x\n",ioread8(addressio + 8));
//printk("%x\n",*(byte *)addressio);
iowrite8(0x89,addressio + 0);
printk("%x\n",ioread8(addressio + 0));
iowrite16(0x50,addressio + 8);
printk("%x\n",ioread16(addressio + 8));
printk("len=%ld\n",len);
return 0;
}
/* The RDC interrupt handler. */
static irqreturn_t pci_eth_interrupt(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct pci_eth_private *priv = netdev_priv(dev);
void __iomem *ioaddr = priv->base;
u16 misr, status;
/* TODO: Is it our interrupt? */
/* TODO: Read status register and clear */
status = ioread16(ioaddr + MISR);
/* RX interrupt request */
if (status & RX_INTS) {
if (status & RX_NO_DESC) {
/* RX descriptor unavailable */
dev->stats.rx_dropped++;
dev->stats.rx_missed_errors++;
}
if (status & RX_FIFO_FULL)
dev->stats.rx_fifo_errors++;
if (likely(napi_schedule_prep(&priv->napi))) {
/* TODO: Mask off (disable) RX interrupt */
__napi_schedule(&priv->napi);
}
}
/* TX interrupt request */
if (status & TX_INTS)
pci_eth_tx(dev);
return IRQ_HANDLED;
}
static u16
brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
{
void __iomem *address = devinfo->tcm + mem_offset;
return (ioread16(address));
}
static u16 usdhi6_read16(struct usdhi6_host *host, u32 reg)
{
u16 data = ioread16(host->base + reg);
dev_vdbg(mmc_dev(host->mmc), "%s(0x%p + 0x%x) = 0x%x\n", __func__,
host->base, reg, data);
return data;
}
static irqreturn_t tpci200_interrupt(int irq, void *dev_id)
{
struct tpci200_board *tpci200 = (struct tpci200_board *) dev_id;
struct slot_irq *slot_irq;
irqreturn_t ret;
u16 status_reg;
int i;
/* Read status register */
status_reg = ioread16(&tpci200->info->interface_regs->status);
/* Did we cause the interrupt? */
if (!(status_reg & TPCI200_SLOT_INT_MASK))
return IRQ_NONE;
/* callback to the IRQ handler for the corresponding slot */
rcu_read_lock();
for (i = 0; i < TPCI200_NB_SLOT; i++) {
if (!(status_reg & ((TPCI200_A_INT0 | TPCI200_A_INT1) << (2 * i))))
continue;
slot_irq = rcu_dereference(tpci200->slots[i].irq);
ret = tpci200_slot_irq(slot_irq);
if (ret == -ENODEV) {
dev_info(&tpci200->info->pdev->dev,
"No registered ISR for slot [%d:%d]!. IRQ will be disabled.\n",
tpci200->number, i);
tpci200_disable_irq(tpci200, i);
}
}
rcu_read_unlock();
return IRQ_HANDLED;
}
static inline unsigned int if_cs_read16(struct if_cs_card *card, uint reg)
{
unsigned int val = ioread16(card->iobase + reg);
if (debug_output)
printk(KERN_INFO "inw %08x<%04x\n", reg, val);
return val;
}
static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct scoop_dev *sdev = container_of(chip, struct scoop_dev, gpio);
/* XXX: I'm usure, but it seems so */
return ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1));
}
static int ec_bhf_setup_offsets(struct ec_bhf_priv *priv)
{
struct device *dev = PRIV_TO_DEV(priv);
unsigned block_count, i;
void __iomem *ec_info;
block_count = ioread8(priv->io + INFO_BLOCK_BLK_CNT);
for (i = 0; i < block_count; i++) {
u16 type = ioread16(priv->io + i * INFO_BLOCK_SIZE +
INFO_BLOCK_TYPE);
if (type == ETHERCAT_MASTER_ID)
break;
}
if (i == block_count) {
dev_err(dev, "EtherCAT master with DMA block not found\n");
return -ENODEV;
}
ec_info = priv->io + i * INFO_BLOCK_SIZE;
priv->tx_dma_chan = ioread8(ec_info + INFO_BLOCK_TX_CHAN);
priv->rx_dma_chan = ioread8(ec_info + INFO_BLOCK_RX_CHAN);
priv->ec_io = priv->io + ioread32(ec_info + INFO_BLOCK_OFFSET);
priv->mii_io = priv->ec_io + ioread32(priv->ec_io + EC_MII_OFFSET);
priv->fifo_io = priv->ec_io + ioread32(priv->ec_io + EC_FIFO_OFFSET);
priv->mac_io = priv->ec_io + ioread32(priv->ec_io + EC_MAC_OFFSET);
return 0;
}
static int scoop_gpio_get(struct gpio_chip *chip, unsigned offset)
{
struct scoop_dev *sdev = gpiochip_get_data(chip);
/* XXX: I'm unsure, but it seems so */
return !!(ioread16(sdev->base + SCOOP_GPRR) & (1 << (offset + 1)));
}
static u16 edma_readw(struct fsl_edma_engine *edma, void __iomem *addr)
{
if (edma->big_endian)
return ioread16be(addr);
else
return ioread16(addr);
}
int softing_bootloader_command(struct softing *card, int16_t cmd,
const char *msg)
{
int ret;
unsigned long stamp;
iowrite16(RES_NONE, &card->dpram[DPRAM_RECEIPT]);
iowrite16(cmd, &card->dpram[DPRAM_COMMAND]);
/* be sure to flush this to the card */
wmb();
stamp = jiffies + 3 * HZ;
/* wait for card */
do {
ret = ioread16(&card->dpram[DPRAM_RECEIPT]);
/* don't have any cached variables */
rmb();
if (ret == RES_OK)
return 0;
if (time_after(jiffies, stamp))
break;
/* process context => relax */
usleep_range(500, 10000);
} while (!signal_pending(current));
ret = (ret == RES_NONE) ? -ETIMEDOUT : -ECANCELED;
dev_alert(&card->pdev->dev, "bootloader %s failed (%i)\n", msg, ret);
return ret;
}
/*
* low level DPRAM command.
* Make sure that card->dpram[DPRAM_FCT_HOST] is preset
*/
static int _softing_fct_cmd(struct softing *card, int16_t cmd, uint16_t vector,
const char *msg)
{
int ret;
unsigned long stamp;
iowrite16(cmd, &card->dpram[DPRAM_FCT_PARAM]);
iowrite8(vector >> 8, &card->dpram[DPRAM_FCT_HOST + 1]);
iowrite8(vector, &card->dpram[DPRAM_FCT_HOST]);
/* be sure to flush this to the card */
wmb();
stamp = jiffies + 1 * HZ;
/* wait for card */
do {
/* DPRAM_FCT_HOST is _not_ aligned */
ret = ioread8(&card->dpram[DPRAM_FCT_HOST]) +
(ioread8(&card->dpram[DPRAM_FCT_HOST + 1]) << 8);
/* don't have any cached variables */
rmb();
if (ret == RES_OK)
/* read return-value now */
return ioread16(&card->dpram[DPRAM_FCT_RESULT]);
if ((ret != vector) || time_after(jiffies, stamp))
break;
/* process context => relax */
usleep_range(500, 10000);
} while (1);
ret = (ret == RES_NONE) ? -ETIMEDOUT : -ECANCELED;
dev_alert(&card->pdev->dev, "firmware %s failed (%i)\n", msg, ret);
return ret;
}
//----------------------------------------------------------------------------------------------//
// //
// Function Name : RestorePreviousGpioMode //
// //
// Description : Function which restore the gpio previous mode (which settting all //
// the gpio registers in their previous mode). //
// //
// Return : A negative number if an error occured, 0 otherwise. //
// //
//----------------------------------------------------------------------------------------------//
static int RestorePreviousGpioMode (unsigned int uiGpioNumber)
{
// Variables initialization
static int iCpt;
static u16 uiToRestoreMode;
static void * addr;
// For each gpio register
for (iCpt = 0; iCpt < m_pGpioAttributesTab[uiGpioNumber].uiNbMuxed; iCpt++) {
// Register access request
addr = ioremap(m_pGpioAttributesTab[uiGpioNumber].uiRegisterAdress[iCpt], 2);
// If an error occured during the request
if (!addr) {
printk (KERN_WARNING "%s%s : IOREMAP error on adresse 0x%x for GPIO %d", DRV_NAME, __func__, m_pGpioAttributesTab[uiGpioNumber].uiRegisterAdress[iCpt], uiGpioNumber);
return -ERR_GPIO_RESTOREPREVIOUSGPIOMODE_MUX_REQUEST;
}
else {
// Save the mode to restore
uiToRestoreMode = m_pGpioAttributesTab[uiGpioNumber].uiPreviousMode[iCpt];
// Save the current mode
m_pGpioAttributesTab[uiGpioNumber].uiPreviousMode[iCpt] = ioread16(addr);
// If the mode to restore and the current mode are not the same
if (m_pGpioAttributesTab[uiGpioNumber].uiPreviousMode[iCpt] != uiToRestoreMode)
iowrite16(uiToRestoreMode, addr); // Restore previous mode
// Unmap the register access
iounmap(addr);
}
}
return 0;
}
//----------------------------------------------------------------------------------------------//
// //
// Function Name : SaveDefaultMode //
// //
// Description : Function which check every gpio register value to save them all //
// into an array //
// //
// Return : A negative number if an error occured, 0 otherwise. //
// //
//----------------------------------------------------------------------------------------------//
static int SaveDefaultMode (void)
{
// Variables initialization
static int iCpt1, iCpt2;
static void * addr;
// For each gpio
for (iCpt1 = 0; iCpt1 < DRIVER_DEV_REGISTER_NB; iCpt1++) {
// For each gpio register
for (iCpt2 = 0; iCpt2 < m_pGpioAttributesTab[iCpt1].uiNbMuxed ; iCpt2++) {
if (m_bDebugPrints)
printk(KERN_DEBUG "%s%s : Gpio %d, Register number %d, adress 0x%x\n", DRV_NAME, __func__, iCpt1, iCpt2, m_pGpioAttributesTab[iCpt1].uiRegisterAdress[iCpt2]);
// Register access request
addr = ioremap(m_pGpioAttributesTab[iCpt1].uiRegisterAdress[iCpt2], 2);
// If an error occured during the request
if (!addr) {
printk (KERN_ERR "%s%s : IOREMAP error on adresse 0x%x for GPIO %d", DRV_NAME, __func__, m_pGpioAttributesTab[iCpt1].uiRegisterAdress[iCpt2], iCpt1);
return -ERR_GPIO_SAVEDEFAULTMODE_MUX_REQUEST;
}
else {
// Save the current mode
m_pGpioAttributesTab[iCpt1].uiDefaultMode[iCpt2] = ioread16(addr);
// Unmap the register access
iounmap(addr);
}
}
}
return 0;
}
/**
* memcpy16_from_io
* @to: pointer to "real" memory
* @from: pointer to IO memory
* @count: data length in bytes to be copied
*
* Copies data from IO memory space to "real" memory space.
*/
void memcpy16_from_io(const void *to, const void __iomem *from, u32 count)
{
u16 *d = (u16 *)to;
u16 *s = (u16 *)from;
u32 words = count >> 1;
while (words--)
*d++ = ioread16(s++);
}
static void check_scoop_reg(struct scoop_dev *sdev)
{
unsigned short mcr;
mcr = ioread16(sdev->base + SCOOP_MCR);
if ((mcr & 0x100) == 0)
iowrite16(0x0101, sdev->base + SCOOP_MCR);
}
/**
* Handle a 16 bit I/O request.
*
* @dev: Device to access
* @buffer: Data buffer
* @buflen: Length of the buffer.
* @rw: True to write.
*/
static unsigned int octeon_cf_data_xfer16(struct ata_device *dev,
unsigned char *buffer,
unsigned int buflen,
int rw)
{
struct ata_port *ap = dev->link->ap;
void __iomem *data_addr = ap->ioaddr.data_addr;
unsigned long words;
int count;
words = buflen / 2;
if (rw) {
count = 16;
while (words--) {
iowrite16(*(uint16_t *)buffer, data_addr);
buffer += sizeof(uint16_t);
/*
* Every 16 writes do a read so the bootbus
* FIFO doesn't fill up.
*/
if (--count == 0) {
ioread8(ap->ioaddr.altstatus_addr);
count = 16;
}
}
} else {
while (words--) {
*(uint16_t *)buffer = ioread16(data_addr);
buffer += sizeof(uint16_t);
}
}
/* Transfer trailing 1 byte, if any. */
if (unlikely(buflen & 0x01)) {
__le16 align_buf[1] = { 0 };
if (rw == READ) {
align_buf[0] = cpu_to_le16(ioread16(data_addr));
memcpy(buffer, align_buf, 1);
} else {
memcpy(align_buf, buffer, 1);
iowrite16(le16_to_cpu(align_buf[0]), data_addr);
}
words++;
}
return buflen;
}
halReturn_t HalEnableI2C(int bEnable )
{
#define PADCONF_I2C2_SCL_OFFSET 0x18e
#define PADCONF_I2C2_SDA_OFFSET 0x190
unsigned short x,old;
void * base = NULL;
base = ioremap(IO_PHY_ADDRESS,
0x10000);
if (base == NULL)
{
SII_DEBUG_PRINT(MSG_ERR,"IO Mapping failed\n");
return HAL_RET_FAILURE;
}
old = ioread16(base + PAD_CONF_OFFSET + PADCONF_I2C2_SCL_OFFSET);
if(bEnable)
{
x = (IEN | PTU | EN | M0 );
}
else
{
x = (EN | PTD | M4 | IDIS);
}
iowrite16(x,base + PAD_CONF_OFFSET + PADCONF_I2C2_SCL_OFFSET);
// SII_DEBUG_PRINT(SII_OSAL_DEBUG_TRACE,"GPIO%d {0x%x}:0x%x => 0x%x ;\n",168,pinconf,old,x);
old = ioread16(base + PAD_CONF_OFFSET + PADCONF_I2C2_SDA_OFFSET);
if(bEnable)
{
x = (IEN | M0 );
}
else
{
x = (EN | PTD | M4 | IDIS);
}
iowrite16(x,base + PAD_CONF_OFFSET + PADCONF_I2C2_SDA_OFFSET);
// SII_DEBUG_PRINT(SII_OSAL_DEBUG_TRACE,"GPIO%d {0x%x}:0x%x => 0x%x ;\n",183,pinconf,old,x);
iounmap(base);
return HAL_RET_SUCCESS;
}
/* The RDC interrupt handler. */
static irqreturn_t r6040_interrupt(int irq, void *dev_id)
{
struct net_device *dev = dev_id;
struct r6040_private *lp = netdev_priv(dev);
void __iomem *ioaddr = lp->base;
u16 misr, status;
/* Save MIER */
misr = ioread16(ioaddr + MIER);
/* Mask off RDC MAC interrupt */
iowrite16(MSK_INT, ioaddr + MIER);
/* Read MISR status and clear */
status = ioread16(ioaddr + MISR);
if (status == 0x0000 || status == 0xffff) {
/* Restore RDC MAC interrupt */
iowrite16(misr, ioaddr + MIER);
return IRQ_NONE;
}
/* RX interrupt request */
if (status & RX_INTS) {
if (status & RX_NO_DESC) {
/* RX descriptor unavailable */
dev->stats.rx_dropped++;
dev->stats.rx_missed_errors++;
}
if (status & RX_FIFO_FULL)
dev->stats.rx_fifo_errors++;
if (likely(napi_schedule_prep(&lp->napi))) {
/* Mask off RX interrupt */
misr &= ~RX_INTS;
__napi_schedule(&lp->napi);
}
}
/* TX interrupt request */
if (status & TX_INTS)
r6040_tx(dev);
/* Restore RDC MAC interrupt */
iowrite16(misr, ioaddr + MIER);
return IRQ_HANDLED;
}
static void tpci200_set_mask(struct tpci200_board *tpci200,
__le16 __iomem *addr, u16 mask)
{
unsigned long flags;
spin_lock_irqsave(&tpci200->regs_lock, flags);
iowrite16(ioread16(addr) | mask, addr);
spin_unlock_irqrestore(&tpci200->regs_lock, flags);
}
static u16 vp_config_vector(struct virtio_pci_device *vp_dev, u16 vector)
{
/* Setup the vector used for configuration events */
iowrite16(vector, vp_dev->ioaddr + VIRTIO_MSI_CONFIG_VECTOR);
/* Verify we had enough resources to assign the vector */
/* Will also flush the write out to device */
return ioread16(vp_dev->ioaddr + VIRTIO_MSI_CONFIG_VECTOR);
}
