unsigned int cpm_pic_init(void)
{
struct device_node *np = NULL;
struct resource res;
unsigned int sirq = NO_IRQ, hwirq, eirq;
int ret;
pr_debug("cpm_pic_init\n");
np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
if (np == NULL)
np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
if (np == NULL) {
printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
return sirq;
}
ret = of_address_to_resource(np, 0, &res);
if (ret)
goto end;
cpic_reg = ioremap(res.start, resource_size(&res));
if (cpic_reg == NULL)
goto end;
sirq = irq_of_parse_and_map(np, 0);
if (sirq == NO_IRQ)
goto end;
/* Initialize the CPM interrupt controller. */
hwirq = (unsigned int)virq_to_hw(sirq);
out_be32(&cpic_reg->cpic_cicr,
(CICR_SCD_SCC4 | CICR_SCC_SCC3 | CICR_SCB_SCC2 | CICR_SCA_SCC1) |
((hwirq/2) << 13) | CICR_HP_MASK);
out_be32(&cpic_reg->cpic_cimr, 0);
cpm_pic_host = irq_domain_add_linear(np, 64, &cpm_pic_host_ops, NULL);
if (cpm_pic_host == NULL) {
printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
sirq = NO_IRQ;
goto end;
}
/* Install our own error handler. */
np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
if (np == NULL)
np = of_find_node_by_type(NULL, "cpm");
if (np == NULL) {
printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
goto end;
}
eirq = irq_of_parse_and_map(np, 0);
if (eirq == NO_IRQ)
goto end;
if (setup_irq(eirq, &cpm_error_irqaction))
printk(KERN_ERR "Could not allocate CPM error IRQ!");
setbits32(&cpic_reg->cpic_cicr, CICR_IEN);
end:
of_node_put(np);
return sirq;
}
static int spi_st_probe(struct platform_device *pdev)
{
struct device_node *np = pdev->dev.of_node;
struct spi_master *master;
struct resource *res;
struct spi_st *spi_st;
int irq, ret = 0;
u32 var;
master = spi_alloc_master(&pdev->dev, sizeof(*spi_st));
if (!master)
return -ENOMEM;
master->dev.of_node = np;
master->mode_bits = MODEBITS;
master->setup = spi_st_setup;
master->cleanup = spi_st_cleanup;
master->transfer_one = spi_st_transfer_one;
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16);
master->auto_runtime_pm = true;
master->bus_num = pdev->id;
spi_st = spi_master_get_devdata(master);
spi_st->clk = devm_clk_get(&pdev->dev, "ssc");
if (IS_ERR(spi_st->clk)) {
dev_err(&pdev->dev, "Unable to request clock\n");
ret = PTR_ERR(spi_st->clk);
goto put_master;
}
ret = clk_prepare_enable(spi_st->clk);
if (ret)
goto put_master;
init_completion(&spi_st->done);
/* Get resources */
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
spi_st->base = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(spi_st->base)) {
ret = PTR_ERR(spi_st->base);
goto clk_disable;
}
/* Disable I2C and Reset SSC */
writel_relaxed(0x0, spi_st->base + SSC_I2C);
var = readw_relaxed(spi_st->base + SSC_CTL);
var |= SSC_CTL_SR;
writel_relaxed(var, spi_st->base + SSC_CTL);
udelay(1);
var = readl_relaxed(spi_st->base + SSC_CTL);
var &= ~SSC_CTL_SR;
writel_relaxed(var, spi_st->base + SSC_CTL);
/* Set SSC into slave mode before reconfiguring PIO pins */
var = readl_relaxed(spi_st->base + SSC_CTL);
var &= ~SSC_CTL_MS;
writel_relaxed(var, spi_st->base + SSC_CTL);
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
dev_err(&pdev->dev, "IRQ missing or invalid\n");
ret = -EINVAL;
goto clk_disable;
}
ret = devm_request_irq(&pdev->dev, irq, spi_st_irq, 0,
pdev->name, spi_st);
if (ret) {
dev_err(&pdev->dev, "Failed to request irq %d\n", irq);
goto clk_disable;
}
/* by default the device is on */
pm_runtime_set_active(&pdev->dev);
pm_runtime_enable(&pdev->dev);
platform_set_drvdata(pdev, master);
ret = devm_spi_register_master(&pdev->dev, master);
if (ret) {
dev_err(&pdev->dev, "Failed to register master\n");
goto clk_disable;
}
return 0;
clk_disable:
clk_disable_unprepare(spi_st->clk);
put_master:
spi_master_put(master);
return ret;
}
static int __devinit tdm_fsl_starlite_probe(struct of_device *ofdev,
const struct of_device_id *match)
{
int ret = 0;
struct tdm_priv *priv;
struct resource res;
priv = kmalloc(sizeof(struct tdm_priv), GFP_KERNEL);
if (!priv) {
ret = -ENOMEM;
goto err_alloc;
}
dev_set_drvdata(&ofdev->dev, priv);
priv->device = &ofdev->dev;
ret = of_address_to_resource(ofdev->node, 0, &res);
if (ret) {
ret = -EINVAL;
goto err_resource;
}
priv->ptdm_base = res.start;
priv->tdm_regs = of_iomap(ofdev->node, 0);
if (!priv->tdm_regs) {
ret = -ENOMEM;
goto err_tdmregs;
}
priv->dmac_regs = of_iomap(ofdev->node, 1);
if (!priv->dmac_regs) {
ret = -ENOMEM;
goto err_dmacreg;
}
/* tdmrd tmdtd at immrbar+0x16100 */
priv->data_regs =
(struct tdm_data *)(TDM_DATAREG_OFFSET + (u8 *)priv->tdm_regs);
/* TDMCLK_DIV_VAL_RX/TX at TDMBASE+0x180 */
priv->clk_regs =
(struct tdm_clock *)(TDM_CLKREG_OFFSET + (u8 *)priv->tdm_regs);
/* irqs mapping for tdm err/dmac err, dmac done */
priv->tdm_err_intr = irq_of_parse_and_map(ofdev->node, 0);
if (priv->tdm_err_intr == NO_IRQ) {
ret = -EINVAL;
goto err_tdmerr_irqmap;
}
priv->dmac_done_intr = irq_of_parse_and_map(ofdev->node, 1);
if (priv->dmac_done_intr == NO_IRQ) {
ret = -EINVAL;
goto err_dmacdone_irqmap;
}
ret =
request_irq(priv->tdm_err_intr, tdm_err_isr, 0, "tdm_err_isr",
priv);
if (ret)
goto err_tdmerrisr;
ret =
request_irq(priv->dmac_done_intr, dmac_done_isr, 0, "dmac_done_isr",
priv);
if (ret)
goto err_dmacdoneisr;
priv->cfg.loopback = e_TDM_PROCESS_NORMAL;
priv->cfg.num_ch = TDM_ACTIVE_CHANNELS;
priv->cfg.ch_type = TDM_CHANNEL_TYPE;
priv->cfg.ch_width = TDM_SLOT_WIDTH;
priv->cfg.num_frames = NUM_OF_FRAMES;
priv->adap = &tdm_fsl_starlite_ops;
/* Wait q initilization */
priv->adap->tdm_rx_flag = 0;
/* todo - these should be configured by dts or init time */
priv->adap->adap_mode = e_TDM_ADAPTER_MODE_NONE;
priv->adap->tdm_mode = priv->cfg.loopback;
priv->adap->max_num_ports = priv->cfg.num_ch;
tdm_set_adapdata(priv->adap, priv);
priv->adap->parent = &ofdev->dev;
ret = 0;
ret = tdm_add_adapter(priv->adap);
if (ret < 0) {
dev_err(priv->device, "failed to add adapter\n");
goto fail_adapter;
}
ret = init_tdm(priv);
if (ret)
goto err_tdminit;
ret = tdm_fsl_starlite_reg_init(priv);
if (ret)
goto err_tdminit;
spin_lock_init(&priv->tdmlock);
spin_lock(&priv->tdmlock);
priv->tdm_active = 0;
spin_unlock(&priv->tdmlock);
if (tdmen) {
ret = tdm_fsl_starlite_enable(priv->adap);
if (!ret)
goto err_tdminit;
}
return 0;
err_tdminit:
fail_adapter:
free_irq(priv->dmac_done_intr, priv);
err_dmacdoneisr:
free_irq(priv->tdm_err_intr, priv);
err_tdmerrisr:
irq_dispose_mapping(priv->dmac_done_intr);
err_dmacdone_irqmap:
irq_dispose_mapping(priv->tdm_err_intr);
err_tdmerr_irqmap:
iounmap(priv->dmac_regs);
err_dmacreg:
iounmap(priv->tdm_regs);
err_tdmregs:
err_resource:
dev_set_drvdata(&ofdev->dev, NULL);
kfree(priv);
err_alloc:
return ret;
}
/* The decrementer counts at the system (internal) clock frequency divided by
* sixteen, or external oscillator divided by four. We force the processor
* to use system clock divided by sixteen.
*/
void __init mpc8xx_calibrate_decr(void)
{
struct device_node *cpu;
cark8xx_t __iomem *clk_r1;
car8xx_t __iomem *clk_r2;
sitk8xx_t __iomem *sys_tmr1;
sit8xx_t __iomem *sys_tmr2;
int irq, virq;
clk_r1 = immr_map(im_clkrstk);
/* Unlock the SCCR. */
out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
out_be32(&clk_r1->cark_sccrk, KAPWR_KEY);
immr_unmap(clk_r1);
/* Force all 8xx processors to use divide by 16 processor clock. */
clk_r2 = immr_map(im_clkrst);
setbits32(&clk_r2->car_sccr, 0x02000000);
immr_unmap(clk_r2);
/* Processor frequency is MHz.
*/
ppc_proc_freq = 50000000;
if (!get_freq("clock-frequency", &ppc_proc_freq))
printk(KERN_ERR "WARNING: Estimating processor frequency "
"(not found)\n");
ppc_tb_freq = ppc_proc_freq / 16;
printk("Decrementer Frequency = 0x%lx\n", ppc_tb_freq);
/* Perform some more timer/timebase initialization. This used
* to be done elsewhere, but other changes caused it to get
* called more than once....that is a bad thing.
*
* First, unlock all of the registers we are going to modify.
* To protect them from corruption during power down, registers
* that are maintained by keep alive power are "locked". To
* modify these registers we have to write the key value to
* the key location associated with the register.
* Some boards power up with these unlocked, while others
* are locked. Writing anything (including the unlock code?)
* to the unlocked registers will lock them again. So, here
* we guarantee the registers are locked, then we unlock them
* for our use.
*/
sys_tmr1 = immr_map(im_sitk);
out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
out_be32(&sys_tmr1->sitk_tbscrk, KAPWR_KEY);
out_be32(&sys_tmr1->sitk_rtcsck, KAPWR_KEY);
out_be32(&sys_tmr1->sitk_tbk, KAPWR_KEY);
immr_unmap(sys_tmr1);
init_internal_rtc();
/* Enabling the decrementer also enables the timebase interrupts
* (or from the other point of view, to get decrementer interrupts
* we have to enable the timebase). The decrementer interrupt
* is wired into the vector table, nothing to do here for that.
*/
cpu = of_find_node_by_type(NULL, "cpu");
virq= irq_of_parse_and_map(cpu, 0);
irq = virq_to_hw(virq);
sys_tmr2 = immr_map(im_sit);
out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
(TBSCR_TBF | TBSCR_TBE));
immr_unmap(sys_tmr2);
if (setup_irq(virq, &tbint_irqaction))
panic("Could not allocate timer IRQ!");
}
static int __devinit
ohci_hcd_ppc_of_probe(struct of_device *op, const struct of_device_id *match)
{
struct device_node *dn = op->dev.of_node;
struct usb_hcd *hcd;
struct ohci_hcd *ohci;
struct resource res;
int irq;
int rv;
int is_bigendian;
struct device_node *np;
if (usb_disabled())
return -ENODEV;
is_bigendian =
of_device_is_compatible(dn, "ohci-bigendian") ||
of_device_is_compatible(dn, "ohci-be");
dev_dbg(&op->dev, "initializing PPC-OF USB Controller\n");
rv = of_address_to_resource(dn, 0, &res);
if (rv)
return rv;
hcd = usb_create_hcd(&ohci_ppc_of_hc_driver, &op->dev, "PPC-OF USB");
if (!hcd)
return -ENOMEM;
hcd->rsrc_start = res.start;
hcd->rsrc_len = res.end - res.start + 1;
if (!request_mem_region(hcd->rsrc_start, hcd->rsrc_len, hcd_name)) {
printk(KERN_ERR "%s: request_mem_region failed\n", __FILE__);
rv = -EBUSY;
goto err_rmr;
}
irq = irq_of_parse_and_map(dn, 0);
if (irq == NO_IRQ) {
printk(KERN_ERR "%s: irq_of_parse_and_map failed\n", __FILE__);
rv = -EBUSY;
goto err_irq;
}
hcd->regs = ioremap(hcd->rsrc_start, hcd->rsrc_len);
if (!hcd->regs) {
printk(KERN_ERR "%s: ioremap failed\n", __FILE__);
rv = -ENOMEM;
goto err_ioremap;
}
ohci = hcd_to_ohci(hcd);
if (is_bigendian) {
ohci->flags |= OHCI_QUIRK_BE_MMIO | OHCI_QUIRK_BE_DESC;
if (of_device_is_compatible(dn, "fsl,mpc5200-ohci"))
ohci->flags |= OHCI_QUIRK_FRAME_NO;
if (of_device_is_compatible(dn, "mpc5200-ohci"))
ohci->flags |= OHCI_QUIRK_FRAME_NO;
}
ohci_hcd_init(ohci);
rv = usb_add_hcd(hcd, irq, IRQF_DISABLED);
if (rv == 0)
return 0;
/* by now, 440epx is known to show usb_23 erratum */
np = of_find_compatible_node(NULL, NULL, "ibm,usb-ehci-440epx");
/* Work around - At this point ohci_run has executed, the
* controller is running, everything, the root ports, etc., is
* set up. If the ehci driver is loaded, put the ohci core in
* the suspended state. The ehci driver will bring it out of
* suspended state when / if a non-high speed USB device is
* attached to the USB Host port. If the ehci driver is not
* loaded, do nothing. request_mem_region is used to test if
* the ehci driver is loaded.
*/
if (np != NULL) {
if (!of_address_to_resource(np, 0, &res)) {
if (!request_mem_region(res.start, 0x4, hcd_name)) {
writel_be((readl_be(&ohci->regs->control) |
OHCI_USB_SUSPEND), &ohci->regs->control);
(void) readl_be(&ohci->regs->control);
} else
release_mem_region(res.start, 0x4);
} else
pr_debug("%s: cannot get ehci offset from fdt\n", __FILE__);
}
iounmap(hcd->regs);
err_ioremap:
irq_dispose_mapping(irq);
err_irq:
release_mem_region(hcd->rsrc_start, hcd->rsrc_len);
err_rmr:
usb_put_hcd(hcd);
return rv;
}
static int talitos_probe(struct platform_device *pdev)
#endif
{
struct talitos_softc *sc = NULL;
struct resource *r;
#ifdef CONFIG_PPC_MERGE
struct device *device = &ofdev->dev;
struct device_node *np = ofdev->node;
const unsigned int *prop;
int err;
struct resource res;
#endif
static int num_chips = 0;
int rc;
int i;
DPRINTF("%s()\n", __FUNCTION__);
sc = (struct talitos_softc *) kmalloc(sizeof(*sc), GFP_KERNEL);
if (!sc)
return -ENOMEM;
memset(sc, 0, sizeof(*sc));
softc_device_init(sc, DRV_NAME, num_chips, talitos_methods);
sc->sc_irq = -1;
sc->sc_cid = -1;
#ifndef CONFIG_PPC_MERGE
sc->sc_dev = pdev;
#endif
sc->sc_num = num_chips++;
#ifdef CONFIG_PPC_MERGE
dev_set_drvdata(device, sc);
#else
platform_set_drvdata(sc->sc_dev, sc);
#endif
/* get the irq line */
#ifdef CONFIG_PPC_MERGE
err = of_address_to_resource(np, 0, &res);
if (err)
return -EINVAL;
r = &res;
sc->sc_irq = irq_of_parse_and_map(np, 0);
#else
/* get a pointer to the register memory */
r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
sc->sc_irq = platform_get_irq(pdev, 0);
#endif
rc = request_irq(sc->sc_irq, talitos_intr, 0,
device_get_nameunit(sc->sc_cdev), sc);
if (rc) {
printk(KERN_ERR "%s: failed to hook irq %d\n",
device_get_nameunit(sc->sc_cdev), sc->sc_irq);
sc->sc_irq = -1;
goto out;
}
sc->sc_base_addr = (ocf_iomem_t) ioremap(r->start, (r->end - r->start));
if (!sc->sc_base_addr) {
printk(KERN_ERR "%s: failed to ioremap\n",
device_get_nameunit(sc->sc_cdev));
goto out;
}
/* figure out our SEC's properties and capabilities */
sc->sc_chiprev = (u64)talitos_read(sc->sc_base_addr + TALITOS_ID) << 32
| talitos_read(sc->sc_base_addr + TALITOS_ID_HI);
DPRINTF("sec id 0x%llx\n", sc->sc_chiprev);
#ifdef CONFIG_PPC_MERGE
/* get SEC properties from device tree, defaulting to SEC 2.0 */
prop = of_get_property(np, "num-channels", NULL);
sc->sc_num_channels = prop ? *prop : TALITOS_NCHANNELS_SEC_2_0;
prop = of_get_property(np, "channel-fifo-len", NULL);
sc->sc_chfifo_len = prop ? *prop : TALITOS_CHFIFOLEN_SEC_2_0;
prop = of_get_property(np, "exec-units-mask", NULL);
sc->sc_exec_units = prop ? *prop : TALITOS_HAS_EUS_SEC_2_0;
prop = of_get_property(np, "descriptor-types-mask", NULL);
sc->sc_desc_types = prop ? *prop : TALITOS_HAS_DESCTYPES_SEC_2_0;
#else
/* bulk should go away with openfirmware flat device tree support */
if (sc->sc_chiprev & TALITOS_ID_SEC_2_0) {
sc->sc_num_channels = TALITOS_NCHANNELS_SEC_2_0;
sc->sc_chfifo_len = TALITOS_CHFIFOLEN_SEC_2_0;
sc->sc_exec_units = TALITOS_HAS_EUS_SEC_2_0;
sc->sc_desc_types = TALITOS_HAS_DESCTYPES_SEC_2_0;
} else {
printk(KERN_ERR "%s: failed to id device\n",
device_get_nameunit(sc->sc_cdev));
goto out;
}
#endif
/* + 1 is for the meta-channel lock used by the channel scheduler */
sc->sc_chnfifolock = (spinlock_t *) kmalloc(
(sc->sc_num_channels + 1) * sizeof(spinlock_t), GFP_KERNEL);
if (!sc->sc_chnfifolock)
goto out;
for (i = 0; i < sc->sc_num_channels + 1; i++) {
spin_lock_init(&sc->sc_chnfifolock[i]);
}
sc->sc_chnlastalg = (int *) kmalloc(
sc->sc_num_channels * sizeof(int), GFP_KERNEL);
if (!sc->sc_chnlastalg)
goto out;
memset(sc->sc_chnlastalg, 0, sc->sc_num_channels * sizeof(int));
sc->sc_chnfifo = (struct desc_cryptop_pair **) kmalloc(
sc->sc_num_channels * sizeof(struct desc_cryptop_pair *),
GFP_KERNEL);
if (!sc->sc_chnfifo)
goto out;
for (i = 0; i < sc->sc_num_channels; i++) {
sc->sc_chnfifo[i] = (struct desc_cryptop_pair *) kmalloc(
sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair),
GFP_KERNEL);
if (!sc->sc_chnfifo[i])
goto out;
memset(sc->sc_chnfifo[i], 0,
sc->sc_chfifo_len * sizeof(struct desc_cryptop_pair));
}
/* reset and initialize the SEC h/w device */
talitos_reset_device(sc);
talitos_init_device(sc);
sc->sc_cid = crypto_get_driverid(softc_get_device(sc),CRYPTOCAP_F_HARDWARE);
if (sc->sc_cid < 0) {
printk(KERN_ERR "%s: could not get crypto driver id\n",
device_get_nameunit(sc->sc_cdev));
goto out;
}
/* register algorithms with the framework */
printk("%s:", device_get_nameunit(sc->sc_cdev));
if (sc->sc_exec_units & TALITOS_HAS_EU_RNG) {
printk(" rng");
#ifdef CONFIG_OCF_RANDOMHARVEST
talitos_rng_init(sc);
crypto_rregister(sc->sc_cid, talitos_read_random, sc);
#endif
}
if (sc->sc_exec_units & TALITOS_HAS_EU_DEU) {
printk(" des/3des");
crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0);
crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0);
}
if (sc->sc_exec_units & TALITOS_HAS_EU_AESU) {
printk(" aes");
crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0);
}
if (sc->sc_exec_units & TALITOS_HAS_EU_MDEU) {
printk(" md5");
crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0);
/* HMAC support only with IPsec for now */
crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0);
printk(" sha1");
crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0);
/* HMAC support only with IPsec for now */
crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0);
}
printk("\n");
return 0;
out:
#ifndef CONFIG_PPC_MERGE
talitos_remove(pdev);
#endif
return -ENOMEM;
}
/*
* Setup one port structure after probing, HW is down at this point,
* Unlike sunzilog, we don't need to pre-init the spinlock as we don't
* register our console before uart_add_one_port() is called
*/
static int __init pmz_init_port(struct uart_pmac_port *uap)
{
struct device_node *np = uap->node;
const char *conn;
const struct slot_names_prop {
int count;
char name[1];
} *slots;
int len;
struct resource r_ports, r_rxdma, r_txdma;
/*
* Request & map chip registers
*/
if (of_address_to_resource(np, 0, &r_ports))
return -ENODEV;
uap->port.mapbase = r_ports.start;
uap->port.membase = ioremap(uap->port.mapbase, 0x1000);
uap->control_reg = uap->port.membase;
uap->data_reg = uap->control_reg + 0x10;
/*
* Request & map DBDMA registers
*/
#ifdef HAS_DBDMA
if (of_address_to_resource(np, 1, &r_txdma) == 0 &&
of_address_to_resource(np, 2, &r_rxdma) == 0)
uap->flags |= PMACZILOG_FLAG_HAS_DMA;
#else
memset(&r_txdma, 0, sizeof(struct resource));
memset(&r_rxdma, 0, sizeof(struct resource));
#endif
if (ZS_HAS_DMA(uap)) {
uap->tx_dma_regs = ioremap(r_txdma.start, 0x100);
if (uap->tx_dma_regs == NULL) {
uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
goto no_dma;
}
uap->rx_dma_regs = ioremap(r_rxdma.start, 0x100);
if (uap->rx_dma_regs == NULL) {
iounmap(uap->tx_dma_regs);
uap->tx_dma_regs = NULL;
uap->flags &= ~PMACZILOG_FLAG_HAS_DMA;
goto no_dma;
}
uap->tx_dma_irq = irq_of_parse_and_map(np, 1);
uap->rx_dma_irq = irq_of_parse_and_map(np, 2);
}
no_dma:
/*
* Detect port type
*/
if (of_device_is_compatible(np, "cobalt"))
uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
conn = of_get_property(np, "AAPL,connector", &len);
if (conn && (strcmp(conn, "infrared") == 0))
uap->flags |= PMACZILOG_FLAG_IS_IRDA;
uap->port_type = PMAC_SCC_ASYNC;
/* 1999 Powerbook G3 has slot-names property instead */
slots = of_get_property(np, "slot-names", &len);
if (slots && slots->count > 0) {
if (strcmp(slots->name, "IrDA") == 0)
uap->flags |= PMACZILOG_FLAG_IS_IRDA;
else if (strcmp(slots->name, "Modem") == 0)
uap->flags |= PMACZILOG_FLAG_IS_INTMODEM;
}
if (ZS_IS_IRDA(uap))
uap->port_type = PMAC_SCC_IRDA;
if (ZS_IS_INTMODEM(uap)) {
struct device_node* i2c_modem =
of_find_node_by_name(NULL, "i2c-modem");
if (i2c_modem) {
const char* mid =
of_get_property(i2c_modem, "modem-id", NULL);
if (mid) switch(*mid) {
case 0x04 :
case 0x05 :
case 0x07 :
case 0x08 :
case 0x0b :
case 0x0c :
uap->port_type = PMAC_SCC_I2S1;
}
printk(KERN_INFO "pmac_zilog: i2c-modem detected, id: %d\n",
mid ? (*mid) : 0);
of_node_put(i2c_modem);
} else {
printk(KERN_INFO "pmac_zilog: serial modem detected\n");
}
}
/*
* Init remaining bits of "port" structure
*/
uap->port.iotype = UPIO_MEM;
uap->port.irq = irq_of_parse_and_map(np, 0);
uap->port.uartclk = ZS_CLOCK;
uap->port.fifosize = 1;
uap->port.ops = &pmz_pops;
uap->port.type = PORT_PMAC_ZILOG;
uap->port.flags = 0;
/* Setup some valid baud rate information in the register
* shadows so we don't write crap there before baud rate is
* first initialized.
*/
pmz_convert_to_zs(uap, CS8, 0, 9600);
return 0;
}
static int __init omap_dm_timer_init_one(struct omap_dm_timer *timer,
int gptimer_id,
const char *fck_source,
const char *property,
int posted)
{
char name[10]; /* 10 = sizeof("gptXX_Xck0") */
const char *oh_name;
struct device_node *np;
struct omap_hwmod *oh;
struct resource irq, mem;
int r = 0;
if (of_have_populated_dt()) {
np = omap_get_timer_dt(omap_timer_match, property);
if (!np)
return -ENODEV;
of_property_read_string_index(np, "ti,hwmods", 0, &oh_name);
if (!oh_name)
return -ENODEV;
timer->irq = irq_of_parse_and_map(np, 0);
if (!timer->irq)
return -ENXIO;
timer->io_base = of_iomap(np, 0);
of_node_put(np);
} else {
if (omap_dm_timer_reserve_systimer(gptimer_id))
return -ENODEV;
sprintf(name, "timer%d", gptimer_id);
oh_name = name;
}
oh = omap_hwmod_lookup(oh_name);
if (!oh)
return -ENODEV;
if (!of_have_populated_dt()) {
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_IRQ, NULL,
&irq);
if (r)
return -ENXIO;
timer->irq = irq.start;
r = omap_hwmod_get_resource_byname(oh, IORESOURCE_MEM, NULL,
&mem);
if (r)
return -ENXIO;
/* Static mapping, never released */
timer->io_base = ioremap(mem.start, mem.end - mem.start);
}
if (!timer->io_base)
return -ENXIO;
/* After the dmtimer is using hwmod these clocks won't be needed */
timer->fclk = clk_get(NULL, omap_hwmod_get_main_clk(oh));
if (IS_ERR(timer->fclk))
return -ENODEV;
/* FIXME: Need to remove hard-coded test on timer ID */
if (gptimer_id != 12) {
struct clk *src;
src = clk_get(NULL, fck_source);
if (IS_ERR(src)) {
r = -EINVAL;
} else {
r = clk_set_parent(timer->fclk, src);
if (IS_ERR_VALUE(r))
pr_warn("%s: %s cannot set source\n",
__func__, oh->name);
clk_put(src);
}
}
omap_hwmod_setup_one(oh_name);
omap_hwmod_enable(oh);
__omap_dm_timer_init_regs(timer);
if (posted)
__omap_dm_timer_enable_posted(timer);
/* Check that the intended posted configuration matches the actual */
if (posted != timer->posted)
return -EINVAL;
timer->rate = clk_get_rate(timer->fclk);
timer->reserved = 1;
return r;
}
static int __init xen_guest_init(void)
{
struct xen_add_to_physmap xatp;
static struct shared_info *shared_info_page = 0;
struct device_node *node;
int len;
const char *s = NULL;
const char *version = NULL;
const char *xen_prefix = "xen,xen-";
struct resource res;
node = of_find_compatible_node(NULL, NULL, "xen,xen");
if (!node) {
pr_debug("No Xen support\n");
return 0;
}
s = of_get_property(node, "compatible", &len);
if (strlen(xen_prefix) + 3 < len &&
!strncmp(xen_prefix, s, strlen(xen_prefix)))
version = s + strlen(xen_prefix);
if (version == NULL) {
pr_debug("Xen version not found\n");
return 0;
}
if (of_address_to_resource(node, GRANT_TABLE_PHYSADDR, &res))
return 0;
xen_hvm_resume_frames = res.start >> PAGE_SHIFT;
xen_events_irq = irq_of_parse_and_map(node, 0);
pr_info("Xen %s support found, events_irq=%d gnttab_frame_pfn=%lx\n",
version, xen_events_irq, xen_hvm_resume_frames);
xen_domain_type = XEN_HVM_DOMAIN;
xen_setup_features();
if (xen_feature(XENFEAT_dom0))
xen_start_info->flags |= SIF_INITDOMAIN|SIF_PRIVILEGED;
else
xen_start_info->flags &= ~(SIF_INITDOMAIN|SIF_PRIVILEGED);
if (!shared_info_page)
shared_info_page = (struct shared_info *)
get_zeroed_page(GFP_KERNEL);
if (!shared_info_page) {
pr_err("not enough memory\n");
return -ENOMEM;
}
xatp.domid = DOMID_SELF;
xatp.idx = 0;
xatp.space = XENMAPSPACE_shared_info;
xatp.gpfn = __pa(shared_info_page) >> PAGE_SHIFT;
if (HYPERVISOR_memory_op(XENMEM_add_to_physmap, &xatp))
BUG();
HYPERVISOR_shared_info = (struct shared_info *)shared_info_page;
/* xen_vcpu is a pointer to the vcpu_info struct in the shared_info
* page, we use it in the event channel upcall and in some pvclock
* related functions.
* The shared info contains exactly 1 CPU (the boot CPU). The guest
* is required to use VCPUOP_register_vcpu_info to place vcpu info
* for secondary CPUs as they are brought up.
* For uniformity we use VCPUOP_register_vcpu_info even on cpu0.
*/
xen_vcpu_info = __alloc_percpu(sizeof(struct vcpu_info),
sizeof(struct vcpu_info));
if (xen_vcpu_info == NULL)
return -ENOMEM;
gnttab_init();
if (!xen_initial_domain())
xenbus_probe(NULL);
return 0;
}
static int __devinit electra_cf_probe(struct of_device *ofdev,
const struct of_device_id *match)
{
struct device *device = &ofdev->dev;
struct device_node *np = ofdev->node;
struct electra_cf_socket *cf;
struct resource mem, io;
int status;
const unsigned int *prop;
int err;
struct vm_struct *area;
err = of_address_to_resource(np, 0, &mem);
if (err)
return -EINVAL;
err = of_address_to_resource(np, 1, &io);
if (err)
return -EINVAL;
cf = kzalloc(sizeof *cf, GFP_KERNEL);
if (!cf)
return -ENOMEM;
setup_timer(&cf->timer, electra_cf_timer, (unsigned long)cf);
cf->irq = NO_IRQ;
cf->ofdev = ofdev;
cf->mem_phys = mem.start;
cf->mem_size = PAGE_ALIGN(mem.end - mem.start);
cf->mem_base = ioremap(cf->mem_phys, cf->mem_size);
cf->io_size = PAGE_ALIGN(io.end - io.start);
area = __get_vm_area(cf->io_size, 0, PHB_IO_BASE, PHB_IO_END);
if (area == NULL)
return -ENOMEM;
cf->io_virt = (void __iomem *)(area->addr);
cf->gpio_base = ioremap(0xfc103000, 0x1000);
dev_set_drvdata(device, cf);
if (!cf->mem_base || !cf->io_virt || !cf->gpio_base ||
(__ioremap_at(io.start, cf->io_virt, cf->io_size,
_PAGE_NO_CACHE | _PAGE_GUARDED) == NULL)) {
dev_err(device, "can't ioremap ranges\n");
status = -ENOMEM;
goto fail1;
}
cf->io_base = (unsigned long)cf->io_virt - VMALLOC_END;
cf->iomem.start = (unsigned long)cf->mem_base;
cf->iomem.end = (unsigned long)cf->mem_base + (mem.end - mem.start);
cf->iomem.flags = IORESOURCE_MEM;
cf->irq = irq_of_parse_and_map(np, 0);
status = request_irq(cf->irq, electra_cf_irq, IRQF_SHARED,
driver_name, cf);
if (status < 0) {
dev_err(device, "request_irq failed\n");
goto fail1;
}
cf->socket.pci_irq = cf->irq;
prop = of_get_property(np, "card-detect-gpio", NULL);
if (!prop)
goto fail1;
cf->gpio_detect = *prop;
prop = of_get_property(np, "card-vsense-gpio", NULL);
if (!prop)
goto fail1;
cf->gpio_vsense = *prop;
prop = of_get_property(np, "card-3v-gpio", NULL);
if (!prop)
goto fail1;
cf->gpio_3v = *prop;
prop = of_get_property(np, "card-5v-gpio", NULL);
if (!prop)
goto fail1;
cf->gpio_5v = *prop;
cf->socket.io_offset = cf->io_base;
/* reserve chip-select regions */
if (!request_mem_region(cf->mem_phys, cf->mem_size, driver_name)) {
status = -ENXIO;
dev_err(device, "Can't claim memory region\n");
goto fail1;
}
if (!request_region(cf->io_base, cf->io_size, driver_name)) {
status = -ENXIO;
dev_err(device, "Can't claim I/O region\n");
goto fail2;
}
cf->socket.owner = THIS_MODULE;
cf->socket.dev.parent = &ofdev->dev;
cf->socket.ops = &electra_cf_ops;
cf->socket.resource_ops = &pccard_static_ops;
cf->socket.features = SS_CAP_PCCARD | SS_CAP_STATIC_MAP |
SS_CAP_MEM_ALIGN;
cf->socket.map_size = 0x800;
status = pcmcia_register_socket(&cf->socket);
if (status < 0) {
dev_err(device, "pcmcia_register_socket failed\n");
goto fail3;
}
dev_info(device, "at mem 0x%lx io 0x%llx irq %d\n",
cf->mem_phys, io.start, cf->irq);
cf->active = 1;
electra_cf_timer((unsigned long)cf);
return 0;
fail3:
release_region(cf->io_base, cf->io_size);
fail2:
release_mem_region(cf->mem_phys, cf->mem_size);
fail1:
if (cf->irq != NO_IRQ)
free_irq(cf->irq, cf);
if (cf->io_virt)
__iounmap_at(cf->io_virt, cf->io_size);
if (cf->mem_base)
iounmap(cf->mem_base);
if (cf->gpio_base)
iounmap(cf->gpio_base);
device_init_wakeup(&ofdev->dev, 0);
kfree(cf);
return status;
}
/*
* Fill a struct uart_port for a given device node
*/
static int __devinit of_platform_serial_setup(struct platform_device *ofdev,
int type, struct uart_port *port)
{
struct resource resource;
struct device_node *np = ofdev->dev.of_node;
u32 clk, spd, prop;
int ret;
memset(port, 0, sizeof *port);
if (of_property_read_u32(np, "clock-frequency", &clk)) {
dev_warn(&ofdev->dev, "no clock-frequency property set\n");
return -ENODEV;
}
/* If current-speed was set, then try not to change it. */
if (of_property_read_u32(np, "current-speed", &spd) == 0)
port->custom_divisor = clk / (16 * spd);
ret = of_address_to_resource(np, 0, &resource);
if (ret) {
dev_warn(&ofdev->dev, "invalid address\n");
return ret;
}
spin_lock_init(&port->lock);
port->mapbase = resource.start;
/* Check for shifted address mapping */
if (of_property_read_u32(np, "reg-offset", &prop) == 0)
port->mapbase += prop;
/* Check for registers offset within the devices address range */
if (of_property_read_u32(np, "reg-shift", &prop) == 0)
port->regshift = prop;
port->irq = irq_of_parse_and_map(np, 0);
port->iotype = UPIO_MEM;
if (of_property_read_u32(np, "reg-io-width", &prop) == 0) {
switch (prop) {
case 1:
port->iotype = UPIO_MEM;
break;
case 4:
port->iotype = UPIO_MEM32;
break;
default:
dev_warn(&ofdev->dev, "unsupported reg-io-width (%d)\n",
prop);
return -EINVAL;
}
}
port->type = type;
port->uartclk = clk;
port->flags = UPF_SHARE_IRQ | UPF_BOOT_AUTOCONF | UPF_IOREMAP
| UPF_FIXED_PORT | UPF_FIXED_TYPE;
port->dev = &ofdev->dev;
if (type == PORT_TEGRA)
port->handle_break = tegra_serial_handle_break;
return 0;
}
static int __init tegra_init_timer(struct device_node *np, bool tegra20)
{
struct timer_of *to;
int cpu, ret;
to = this_cpu_ptr(&tegra_to);
ret = timer_of_init(np, to);
if (ret)
goto out;
timer_reg_base = timer_of_base(to);
/*
* Configure microsecond timers to have 1MHz clock
* Config register is 0xqqww, where qq is "dividend", ww is "divisor"
* Uses n+1 scheme
*/
switch (timer_of_rate(to)) {
case 12000000:
usec_config = 0x000b; /* (11+1)/(0+1) */
break;
case 12800000:
usec_config = 0x043f; /* (63+1)/(4+1) */
break;
case 13000000:
usec_config = 0x000c; /* (12+1)/(0+1) */
break;
case 16800000:
usec_config = 0x0453; /* (83+1)/(4+1) */
break;
case 19200000:
usec_config = 0x045f; /* (95+1)/(4+1) */
break;
case 26000000:
usec_config = 0x0019; /* (25+1)/(0+1) */
break;
case 38400000:
usec_config = 0x04bf; /* (191+1)/(4+1) */
break;
case 48000000:
usec_config = 0x002f; /* (47+1)/(0+1) */
break;
default:
ret = -EINVAL;
goto out;
}
writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG);
for_each_possible_cpu(cpu) {
struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu);
unsigned int base = tegra_base_for_cpu(cpu, tegra20);
unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20);
/*
* TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the
* parent clock.
*/
if (tegra20)
cpu_to->of_clk.rate = 1000000;
cpu_to = per_cpu_ptr(&tegra_to, cpu);
cpu_to->of_base.base = timer_reg_base + base;
cpu_to->clkevt.cpumask = cpumask_of(cpu);
cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx);
if (!cpu_to->clkevt.irq) {
pr_err("failed to map irq for cpu%d\n", cpu);
ret = -EINVAL;
goto out_irq;
}
irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN);
ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr,
IRQF_TIMER | IRQF_NOBALANCING,
cpu_to->clkevt.name, &cpu_to->clkevt);
if (ret) {
pr_err("failed to set up irq for cpu%d: %d\n",
cpu, ret);
irq_dispose_mapping(cpu_to->clkevt.irq);
cpu_to->clkevt.irq = 0;
goto out_irq;
}
}
sched_clock_register(tegra_read_sched_clock, 32, 1000000);
ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
"timer_us", 1000000,
300, 32, clocksource_mmio_readl_up);
if (ret)
pr_err("failed to register clocksource: %d\n", ret);
#ifdef CONFIG_ARM
register_current_timer_delay(&tegra_delay_timer);
#endif
ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING,
"AP_TEGRA_TIMER_STARTING", tegra_timer_setup,
tegra_timer_stop);
if (ret)
pr_err("failed to set up cpu hp state: %d\n", ret);
return ret;
out_irq:
for_each_possible_cpu(cpu) {
struct timer_of *cpu_to;
cpu_to = per_cpu_ptr(&tegra_to, cpu);
if (cpu_to->clkevt.irq) {
free_irq(cpu_to->clkevt.irq, &cpu_to->clkevt);
irq_dispose_mapping(cpu_to->clkevt.irq);
}
}
out:
timer_of_cleanup(to);
return ret;
}
void __init armada_370_xp_timer_init(void)
{
u32 u;
struct device_node *np;
int res;
np = of_find_compatible_node(NULL, NULL, "marvell,armada-370-xp-timer");
timer_base = of_iomap(np, 0);
WARN_ON(!timer_base);
local_base = of_iomap(np, 1);
if (of_find_property(np, "marvell,timer-25Mhz", NULL)) {
/* The fixed 25MHz timer is available so let's use it */
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u | TIMER0_25MHZ,
timer_base + TIMER_CTRL_OFF);
timer_clk = 25000000;
} else {
unsigned long rate = 0;
struct clk *clk = of_clk_get(np, 0);
WARN_ON(IS_ERR(clk));
rate = clk_get_rate(clk);
u = readl(timer_base + TIMER_CTRL_OFF);
writel(u & ~(TIMER0_25MHZ),
timer_base + TIMER_CTRL_OFF);
timer_clk = rate / TIMER_DIVIDER;
timer25Mhz = false;
}
/*
* We use timer 0 as clocksource, and private(local) timer 0
* for clockevents
*/
armada_370_xp_clkevt_irq = irq_of_parse_and_map(np, 4);
ticks_per_jiffy = (timer_clk + HZ / 2) / HZ;
/*
* Set scale and timer for sched_clock.
*/
setup_sched_clock(armada_370_xp_read_sched_clock, 32, timer_clk);
/*
* Setup free-running clocksource timer (interrupts
* disabled).
*/
writel(0xffffffff, timer_base + TIMER0_VAL_OFF);
writel(0xffffffff, timer_base + TIMER0_RELOAD_OFF);
u = readl(timer_base + TIMER_CTRL_OFF);
writel((u | TIMER0_EN | TIMER0_RELOAD_EN |
TIMER0_DIV(TIMER_DIVIDER_SHIFT)), timer_base + TIMER_CTRL_OFF);
clocksource_mmio_init(timer_base + TIMER0_VAL_OFF,
"armada_370_xp_clocksource",
timer_clk, 300, 32, clocksource_mmio_readl_down);
register_cpu_notifier(&armada_370_xp_timer_cpu_nb);
armada_370_xp_evt = alloc_percpu(struct clock_event_device);
/*
* Setup clockevent timer (interrupt-driven).
*/
res = request_percpu_irq(armada_370_xp_clkevt_irq,
armada_370_xp_timer_interrupt,
"armada_370_xp_per_cpu_tick",
armada_370_xp_evt);
/* Immediately configure the timer on the boot CPU */
if (!res)
armada_370_xp_timer_setup(this_cpu_ptr(armada_370_xp_evt));
}
static int __devinit fsl_i2c_probe(struct of_device *op, const struct of_device_id *match)
{
int result = 0;
struct mpc_i2c *i2c;
i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
if (!i2c)
return -ENOMEM;
if (of_get_property(op->node, "dfsrr", NULL))
i2c->flags |= FSL_I2C_DEV_SEPARATE_DFSRR;
if (of_device_is_compatible(op->node, "fsl,mpc5200-i2c") ||
of_device_is_compatible(op->node, "mpc5200-i2c"))
i2c->flags |= FSL_I2C_DEV_CLOCK_5200;
init_waitqueue_head(&i2c->queue);
i2c->base = of_iomap(op->node, 0);
if (!i2c->base) {
printk(KERN_ERR "i2c-mpc - failed to map controller\n");
result = -ENOMEM;
goto fail_map;
}
i2c->irq = irq_of_parse_and_map(op->node, 0);
if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */
result = request_irq(i2c->irq, mpc_i2c_isr,
IRQF_SHARED, "i2c-mpc", i2c);
if (result < 0) {
printk(KERN_ERR "i2c-mpc - failed to attach interrupt\n");
goto fail_request;
}
}
mpc_i2c_setclock(i2c);
dev_set_drvdata(&op->dev, i2c);
i2c->adap = mpc_ops;
i2c_set_adapdata(&i2c->adap, i2c);
i2c->adap.dev.parent = &op->dev;
result = i2c_add_adapter(&i2c->adap);
if (result < 0) {
printk(KERN_ERR "i2c-mpc - failed to add adapter\n");
goto fail_add;
}
of_register_i2c_devices(&i2c->adap, op->node);
return result;
fail_add:
dev_set_drvdata(&op->dev, NULL);
free_irq(i2c->irq, i2c);
fail_request:
irq_dispose_mapping(i2c->irq);
iounmap(i2c->base);
fail_map:
kfree(i2c);
return result;
};
static int of_isp1760_probe(struct platform_device *dev)
{
struct isp1760 *drvdata;
struct device_node *dp = dev->dev.of_node;
struct resource *res;
struct resource memory;
int virq;
resource_size_t res_len;
int ret;
unsigned int devflags = 0;
enum of_gpio_flags gpio_flags;
u32 bus_width = 0;
drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
ret = of_address_to_resource(dp, 0, &memory);
if (ret) {
ret = -ENXIO;
goto free_data;
}
res_len = resource_size(&memory);
res = request_mem_region(memory.start, res_len, dev_name(&dev->dev));
if (!res) {
ret = -EBUSY;
goto free_data;
}
virq = irq_of_parse_and_map(dp, 0);
if (!virq) {
ret = -ENODEV;
goto release_reg;
}
if (of_device_is_compatible(dp, "nxp,usb-isp1761"))
devflags |= ISP1760_FLAG_ISP1761;
/* Some systems wire up only 16 of the 32 data lines */
of_property_read_u32(dp, "bus-width", &bus_width);
if (bus_width == 16)
devflags |= ISP1760_FLAG_BUS_WIDTH_16;
if (of_get_property(dp, "port1-otg", NULL) != NULL)
devflags |= ISP1760_FLAG_OTG_EN;
if (of_get_property(dp, "analog-oc", NULL) != NULL)
devflags |= ISP1760_FLAG_ANALOG_OC;
if (of_get_property(dp, "dack-polarity", NULL) != NULL)
devflags |= ISP1760_FLAG_DACK_POL_HIGH;
if (of_get_property(dp, "dreq-polarity", NULL) != NULL)
devflags |= ISP1760_FLAG_DREQ_POL_HIGH;
drvdata->rst_gpio = of_get_gpio_flags(dp, 0, &gpio_flags);
if (gpio_is_valid(drvdata->rst_gpio)) {
ret = gpio_request(drvdata->rst_gpio, dev_name(&dev->dev));
if (!ret) {
if (!(gpio_flags & OF_GPIO_ACTIVE_LOW)) {
devflags |= ISP1760_FLAG_RESET_ACTIVE_HIGH;
gpio_direction_output(drvdata->rst_gpio, 0);
} else {
gpio_direction_output(drvdata->rst_gpio, 1);
}
} else {
drvdata->rst_gpio = ret;
}
}
drvdata->hcd = isp1760_register(memory.start, res_len, virq,
IRQF_SHARED, drvdata->rst_gpio,
&dev->dev, dev_name(&dev->dev),
devflags);
if (IS_ERR(drvdata->hcd)) {
ret = PTR_ERR(drvdata->hcd);
goto free_gpio;
}
dev_set_drvdata(&dev->dev, drvdata);
return ret;
free_gpio:
if (gpio_is_valid(drvdata->rst_gpio))
gpio_free(drvdata->rst_gpio);
release_reg:
release_mem_region(memory.start, res_len);
free_data:
kfree(drvdata);
return ret;
}
static int ehci_hcd_grlib_probe(struct platform_device *op)
{
struct device_node *dn = op->dev.of_node;
struct usb_hcd *hcd;
struct ehci_hcd *ehci = NULL;
struct resource res;
u32 hc_capbase;
int irq;
int rv;
if (usb_disabled())
return -ENODEV;
dev_dbg(&op->dev, "initializing GRUSBHC EHCI USB Controller\n");
rv = of_address_to_resource(dn, 0, &res);
if (rv)
return rv;
/* usb_create_hcd requires dma_mask != NULL */
op->dev.dma_mask = &op->dev.coherent_dma_mask;
hcd = usb_create_hcd(&ehci_grlib_hc_driver, &op->dev,
"GRUSBHC EHCI USB");
if (!hcd)
return -ENOMEM;
hcd->rsrc_start = res.start;
hcd->rsrc_len = resource_size(&res);
irq = irq_of_parse_and_map(dn, 0);
if (irq == NO_IRQ) {
printk(KERN_ERR "%s: irq_of_parse_and_map failed\n", __FILE__);
rv = -EBUSY;
goto err_irq;
}
hcd->regs = devm_ioremap_resource(&op->dev, &res);
if (IS_ERR(hcd->regs)) {
rv = PTR_ERR(hcd->regs);
goto err_ioremap;
}
ehci = hcd_to_ehci(hcd);
ehci->caps = hcd->regs;
/* determine endianness of this implementation */
hc_capbase = ehci_readl(ehci, &ehci->caps->hc_capbase);
if (HC_VERSION(ehci, hc_capbase) != GRUSBHC_HCIVERSION) {
ehci->big_endian_mmio = 1;
ehci->big_endian_desc = 1;
ehci->big_endian_capbase = 1;
}
rv = usb_add_hcd(hcd, irq, 0);
if (rv)
goto err_ioremap;
return 0;
err_ioremap:
irq_dispose_mapping(irq);
err_irq:
usb_put_hcd(hcd);
return rv;
}
static int kpd_pdrv_probe(struct platform_device *pdev)
{
int i, r;
int err = 0;
struct clk *kpd_clk = NULL;
kpd_info("Keypad probe start!!!\n");
/*kpd-clk should be control by kpd driver, not depend on default clock state*/
kpd_clk = devm_clk_get(&pdev->dev, "kpd-clk");
if (!IS_ERR(kpd_clk)) {
clk_prepare(kpd_clk);
clk_enable(kpd_clk);
} else {
kpd_print("get kpd-clk fail, but not return, maybe kpd-clk is set by ccf.\n");
}
kp_base = of_iomap(pdev->dev.of_node, 0);
if (!kp_base) {
kpd_info("KP iomap failed\n");
return -ENODEV;
};
kp_irqnr = irq_of_parse_and_map(pdev->dev.of_node, 0);
if (!kp_irqnr) {
kpd_info("KP get irqnr failed\n");
return -ENODEV;
}
kpd_info("kp base: 0x%p, addr:0x%p, kp irq: %d\n", kp_base, &kp_base, kp_irqnr);
/* initialize and register input device (/dev/input/eventX) */
kpd_input_dev = input_allocate_device();
if (!kpd_input_dev) {
kpd_print("input allocate device fail.\n");
return -ENOMEM;
}
kpd_input_dev->name = KPD_NAME;
kpd_input_dev->id.bustype = BUS_HOST;
kpd_input_dev->id.vendor = 0x2454;
kpd_input_dev->id.product = 0x6500;
kpd_input_dev->id.version = 0x0010;
kpd_input_dev->open = kpd_open;
kpd_get_dts_info(pdev->dev.of_node);
#ifdef CONFIG_ARCH_MT8173
wake_lock_init(&pwrkey_lock, WAKE_LOCK_SUSPEND, "PWRKEY");
#endif
/* fulfill custom settings */
kpd_memory_setting();
__set_bit(EV_KEY, kpd_input_dev->evbit);
#if defined(CONFIG_KPD_PWRKEY_USE_EINT) || defined(CONFIG_KPD_PWRKEY_USE_PMIC)
__set_bit(kpd_dts_data.kpd_sw_pwrkey, kpd_input_dev->keybit);
kpd_keymap[8] = 0;
#endif
if (!kpd_dts_data.kpd_use_extend_type) {
for (i = 17; i < KPD_NUM_KEYS; i += 9) /* only [8] works for Power key */
kpd_keymap[i] = 0;
}
for (i = 0; i < KPD_NUM_KEYS; i++) {
if (kpd_keymap[i] != 0)
__set_bit(kpd_keymap[i], kpd_input_dev->keybit);
}
#if KPD_AUTOTEST
for (i = 0; i < ARRAY_SIZE(kpd_auto_keymap); i++)
__set_bit(kpd_auto_keymap[i], kpd_input_dev->keybit);
#endif
#if KPD_HAS_SLIDE_QWERTY
__set_bit(EV_SW, kpd_input_dev->evbit);
__set_bit(SW_LID, kpd_input_dev->swbit);
#endif
if (kpd_dts_data.kpd_sw_rstkey)
__set_bit(kpd_dts_data.kpd_sw_rstkey, kpd_input_dev->keybit);
#ifdef KPD_KEY_MAP
__set_bit(KPD_KEY_MAP, kpd_input_dev->keybit);
#endif
#ifdef CONFIG_MTK_MRDUMP_KEY
__set_bit(KEY_RESTART, kpd_input_dev->keybit);
#endif
kpd_input_dev->dev.parent = &pdev->dev;
r = input_register_device(kpd_input_dev);
if (r) {
kpd_info("register input device failed (%d)\n", r);
input_free_device(kpd_input_dev);
return r;
}
/* register device (/dev/mt6575-kpd) */
kpd_dev.parent = &pdev->dev;
r = misc_register(&kpd_dev);
if (r) {
kpd_info("register device failed (%d)\n", r);
input_unregister_device(kpd_input_dev);
return r;
}
wake_lock_init(&kpd_suspend_lock, WAKE_LOCK_SUSPEND, "kpd wakelock");
/* register IRQ and EINT */
kpd_set_debounce(kpd_dts_data.kpd_key_debounce);
r = request_irq(kp_irqnr, kpd_irq_handler, IRQF_TRIGGER_NONE, KPD_NAME, NULL);
if (r) {
kpd_info("register IRQ failed (%d)\n", r);
misc_deregister(&kpd_dev);
input_unregister_device(kpd_input_dev);
return r;
}
mt_eint_register();
#ifndef KPD_EARLY_PORTING /*add for avoid early porting build err the macro is defined in custom file */
long_press_reboot_function_setting(); /* /API 4 for kpd long press reboot function setting */
#endif
hrtimer_init(&aee_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
aee_timer.function = aee_timer_func;
#if AEE_ENABLE_5_15
hrtimer_init(&aee_timer_5s, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
aee_timer_5s.function = aee_timer_5s_func;
#endif
err = kpd_create_attr(&kpd_pdrv.driver);
if (err) {
kpd_info("create attr file fail\n");
kpd_delete_attr(&kpd_pdrv.driver);
return err;
}
kpd_info("%s Done\n", __func__);
return 0;
}
static int serial_omap_probe(struct platform_device *pdev)
{
struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
struct uart_omap_port *up;
struct resource *mem;
void __iomem *base;
int uartirq = 0;
int wakeirq = 0;
int ret;
/* The optional wakeirq may be specified in the board dts file */
if (pdev->dev.of_node) {
uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
if (!uartirq)
return -EPROBE_DEFER;
wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
omap_up_info = of_get_uart_port_info(&pdev->dev);
pdev->dev.platform_data = omap_up_info;
} else {
uartirq = platform_get_irq(pdev, 0);
if (uartirq < 0)
return -EPROBE_DEFER;
}
up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
if (!up)
return -ENOMEM;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(base))
return PTR_ERR(base);
up->dev = &pdev->dev;
up->port.dev = &pdev->dev;
up->port.type = PORT_OMAP;
up->port.iotype = UPIO_MEM;
up->port.irq = uartirq;
up->port.regshift = 2;
up->port.fifosize = 64;
up->port.ops = &serial_omap_pops;
if (pdev->dev.of_node)
ret = of_alias_get_id(pdev->dev.of_node, "serial");
else
ret = pdev->id;
if (ret < 0) {
dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
ret);
goto err_port_line;
}
up->port.line = ret;
if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
dev_err(&pdev->dev, "uart ID %d > MAX %d.\n", up->port.line,
OMAP_MAX_HSUART_PORTS);
ret = -ENXIO;
goto err_port_line;
}
up->wakeirq = wakeirq;
if (!up->wakeirq)
dev_info(up->port.dev, "no wakeirq for uart%d\n",
up->port.line);
ret = serial_omap_probe_rs485(up, pdev->dev.of_node);
if (ret < 0)
goto err_rs485;
sprintf(up->name, "OMAP UART%d", up->port.line);
up->port.mapbase = mem->start;
up->port.membase = base;
up->port.flags = omap_up_info->flags;
up->port.uartclk = omap_up_info->uartclk;
up->port.rs485_config = serial_omap_config_rs485;
if (!up->port.uartclk) {
up->port.uartclk = DEFAULT_CLK_SPEED;
dev_warn(&pdev->dev,
"No clock speed specified: using default: %d\n",
DEFAULT_CLK_SPEED);
}
up->latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
up->calc_latency = PM_QOS_CPU_DMA_LAT_DEFAULT_VALUE;
pm_qos_add_request(&up->pm_qos_request,
PM_QOS_CPU_DMA_LATENCY, up->latency);
INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
platform_set_drvdata(pdev, up);
if (omap_up_info->autosuspend_timeout == 0)
omap_up_info->autosuspend_timeout = -1;
device_init_wakeup(up->dev, true);
pm_runtime_use_autosuspend(&pdev->dev);
pm_runtime_set_autosuspend_delay(&pdev->dev,
omap_up_info->autosuspend_timeout);
pm_runtime_irq_safe(&pdev->dev);
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
omap_serial_fill_features_erratas(up);
ui[up->port.line] = up;
serial_omap_add_console_port(up);
ret = uart_add_one_port(&serial_omap_reg, &up->port);
if (ret != 0)
goto err_add_port;
pm_runtime_mark_last_busy(up->dev);
pm_runtime_put_autosuspend(up->dev);
return 0;
err_add_port:
pm_runtime_put(&pdev->dev);
pm_runtime_disable(&pdev->dev);
pm_qos_remove_request(&up->pm_qos_request);
device_init_wakeup(up->dev, false);
err_rs485:
err_port_line:
return ret;
}
int of_mdiobus_register(struct mii_bus *mdio, struct device_node *np)
{
struct phy_device *phy;
struct device_node *child;
int rc, i;
mdio->phy_mask = ~0;
if (mdio->irq)
for (i=0; i<PHY_MAX_ADDR; i++)
mdio->irq[i] = PHY_POLL;
rc = mdiobus_register(mdio);
if (rc)
return rc;
for_each_child_of_node(np, child) {
const __be32 *paddr;
u32 addr;
int len;
paddr = of_get_property(child, "reg", &len);
if (!paddr || len < sizeof(*paddr)) {
dev_err(&mdio->dev, "%s has invalid PHY address\n",
child->full_name);
continue;
}
addr = be32_to_cpup(paddr);
if (addr >= 32) {
dev_err(&mdio->dev, "%s PHY address %i is too large\n",
child->full_name, addr);
continue;
}
if (mdio->irq) {
mdio->irq[addr] = irq_of_parse_and_map(child, 0);
if (!mdio->irq[addr])
mdio->irq[addr] = PHY_POLL;
}
phy = get_phy_device(mdio, addr);
if (!phy || IS_ERR(phy)) {
dev_err(&mdio->dev, "error probing PHY at address %i\n",
addr);
continue;
}
of_node_get(child);
phy->dev.of_node = child;
rc = phy_device_register(phy);
if (rc) {
phy_device_free(phy);
of_node_put(child);
continue;
}
dev_dbg(&mdio->dev, "registered phy %s at address %i\n",
child->name, addr);
}
return 0;
}
/*
* Interrupt setup and service. Interrupts on the holly come
* from the four external INT pins, PCI interrupts are routed via
* PCI interrupt control registers, it generates internal IRQ23
*
* Interrupt routing on the Holly Board:
* TSI108:PB_INT[0] -> CPU0:INT#
* TSI108:PB_INT[1] -> CPU0:MCP#
* TSI108:PB_INT[2] -> N/C
* TSI108:PB_INT[3] -> N/C
*/
static void __init holly_init_IRQ(void)
{
struct mpic *mpic;
phys_addr_t mpic_paddr = 0;
struct device_node *tsi_pic;
#ifdef CONFIG_PCI
unsigned int cascade_pci_irq;
struct device_node *tsi_pci;
struct device_node *cascade_node = NULL;
#endif
tsi_pic = of_find_node_by_type(NULL, "open-pic");
if (tsi_pic) {
unsigned int size;
const void *prop = of_get_property(tsi_pic, "reg", &size);
mpic_paddr = of_translate_address(tsi_pic, prop);
}
if (mpic_paddr == 0) {
printk(KERN_ERR "%s: No tsi108 PIC found !\n", __func__);
return;
}
pr_debug("%s: tsi108 pic phys_addr = 0x%x\n", __func__, (u32) mpic_paddr);
mpic = mpic_alloc(tsi_pic, mpic_paddr,
MPIC_PRIMARY | MPIC_BIG_ENDIAN | MPIC_WANTS_RESET |
MPIC_SPV_EOI | MPIC_NO_PTHROU_DIS | MPIC_REGSET_TSI108,
24,
NR_IRQS-4, /* num_sources used */
"Tsi108_PIC");
BUG_ON(mpic == NULL);
mpic_assign_isu(mpic, 0, mpic_paddr + 0x100);
mpic_init(mpic);
#ifdef CONFIG_PCI
tsi_pci = of_find_node_by_type(NULL, "pci");
if (tsi_pci == NULL) {
printk(KERN_ERR "%s: No tsi108 pci node found !\n", __func__);
return;
}
cascade_node = of_find_node_by_type(NULL, "pic-router");
if (cascade_node == NULL) {
printk(KERN_ERR "%s: No tsi108 pci cascade node found !\n", __func__);
return;
}
cascade_pci_irq = irq_of_parse_and_map(tsi_pci, 0);
pr_debug("%s: tsi108 cascade_pci_irq = 0x%x\n", __func__, (u32) cascade_pci_irq);
tsi108_pci_int_init(cascade_node);
set_irq_data(cascade_pci_irq, mpic);
set_irq_chained_handler(cascade_pci_irq, tsi108_irq_cascade);
#endif
/* Configure MPIC outputs to CPU0 */
tsi108_write_reg(TSI108_MPIC_OFFSET + 0x30c, 0);
of_node_put(tsi_pic);
}
static int mpc52xx_fec_mdio_probe(struct of_device *of,
const struct of_device_id *match)
{
struct device *dev = &of->dev;
struct device_node *np = of->node;
struct device_node *child = NULL;
struct mii_bus *bus;
struct mpc52xx_fec_mdio_priv *priv;
struct resource res = {};
int err;
int i;
bus = mdiobus_alloc();
if (bus == NULL)
return -ENOMEM;
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (priv == NULL) {
err = -ENOMEM;
goto out_free;
}
bus->name = "mpc52xx MII bus";
bus->read = mpc52xx_fec_mdio_read;
bus->write = mpc52xx_fec_mdio_write;
/* setup irqs */
bus->irq = kmalloc(sizeof(bus->irq[0]) * PHY_MAX_ADDR, GFP_KERNEL);
if (bus->irq == NULL) {
err = -ENOMEM;
goto out_free;
}
for (i=0; i<PHY_MAX_ADDR; i++)
bus->irq[i] = PHY_POLL;
while ((child = of_get_next_child(np, child)) != NULL) {
int irq = irq_of_parse_and_map(child, 0);
if (irq != NO_IRQ) {
const u32 *id = of_get_property(child, "reg", NULL);
if (id)
bus->irq[*id] = irq;
}
}
/* setup registers */
err = of_address_to_resource(np, 0, &res);
if (err)
goto out_free;
priv->regs = ioremap(res.start, res.end - res.start + 1);
if (priv->regs == NULL) {
err = -ENOMEM;
goto out_free;
}
snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
bus->priv = priv;
bus->parent = dev;
dev_set_drvdata(dev, bus);
/* set MII speed */
out_be32(&priv->regs->mii_speed,
((mpc52xx_find_ipb_freq(of->node) >> 20) / 5) << 1);
err = mdiobus_register(bus);
if (err)
goto out_unmap;
return 0;
out_unmap:
iounmap(priv->regs);
out_free:
for (i=0; i<PHY_MAX_ADDR; i++)
if (bus->irq[i] != PHY_POLL)
irq_dispose_mapping(bus->irq[i]);
kfree(bus->irq);
kfree(priv);
mdiobus_free(bus);
return err;
}
static int nokia_modem_probe(struct device *dev)
{
struct device_node *np;
struct nokia_modem_device *modem;
struct hsi_client *cl = to_hsi_client(dev);
struct hsi_port *port = hsi_get_port(cl);
int irq, pflags, err;
struct hsi_board_info ssip;
struct hsi_board_info cmtspeech;
np = dev->of_node;
if (!np) {
dev_err(dev, "device tree node not found\n");
return -ENXIO;
}
modem = devm_kzalloc(dev, sizeof(*modem), GFP_KERNEL);
if (!modem) {
dev_err(dev, "Could not allocate memory for nokia_modem_device\n");
return -ENOMEM;
}
dev_set_drvdata(dev, modem);
modem->device = dev;
irq = irq_of_parse_and_map(np, 0);
if (!irq) {
dev_err(dev, "Invalid rst_ind interrupt (%d)\n", irq);
return -EINVAL;
}
modem->nokia_modem_rst_ind_irq = irq;
pflags = irq_get_trigger_type(irq);
tasklet_init(&modem->nokia_modem_rst_ind_tasklet,
do_nokia_modem_rst_ind_tasklet, (unsigned long)modem);
err = devm_request_irq(dev, irq, nokia_modem_rst_ind_isr,
pflags, "modem_rst_ind", modem);
if (err < 0) {
dev_err(dev, "Request rst_ind irq(%d) failed (flags %d)\n",
irq, pflags);
return err;
}
enable_irq_wake(irq);
if(pm) {
err = nokia_modem_gpio_probe(dev);
if (err < 0) {
dev_err(dev, "Could not probe GPIOs\n");
goto error1;
}
}
ssip.name = "ssi-protocol";
ssip.tx_cfg = cl->tx_cfg;
ssip.rx_cfg = cl->rx_cfg;
ssip.platform_data = NULL;
ssip.archdata = NULL;
modem->ssi_protocol = hsi_new_client(port, &ssip);
if (!modem->ssi_protocol) {
dev_err(dev, "Could not register ssi-protocol device\n");
err = -ENOMEM;
goto error2;
}
err = device_attach(&modem->ssi_protocol->device);
if (err == 0) {
dev_dbg(dev, "Missing ssi-protocol driver\n");
err = -EPROBE_DEFER;
goto error3;
} else if (err < 0) {
dev_err(dev, "Could not load ssi-protocol driver (%d)\n", err);
goto error3;
}
cmtspeech.name = "cmt-speech";
cmtspeech.tx_cfg = cl->tx_cfg;
cmtspeech.rx_cfg = cl->rx_cfg;
cmtspeech.platform_data = NULL;
cmtspeech.archdata = NULL;
modem->cmt_speech = hsi_new_client(port, &cmtspeech);
if (!modem->cmt_speech) {
dev_err(dev, "Could not register cmt-speech device\n");
err = -ENOMEM;
goto error3;
}
err = device_attach(&modem->cmt_speech->device);
if (err == 0) {
dev_dbg(dev, "Missing cmt-speech driver\n");
err = -EPROBE_DEFER;
goto error4;
} else if (err < 0) {
dev_err(dev, "Could not load cmt-speech driver (%d)\n", err);
goto error4;
}
dev_info(dev, "Registered Nokia HSI modem\n");
return 0;
error4:
hsi_remove_client(&modem->cmt_speech->device, NULL);
error3:
hsi_remove_client(&modem->ssi_protocol->device, NULL);
error2:
nokia_modem_gpio_unexport(dev);
error1:
disable_irq_wake(modem->nokia_modem_rst_ind_irq);
tasklet_kill(&modem->nokia_modem_rst_ind_tasklet);
return err;
}
static int pmc_probe(struct platform_device *ofdev)
{
const struct of_device_id *match;
struct device_node *np = ofdev->dev.of_node;
struct resource res;
const struct pmc_type *type;
int ret = 0;
match = of_match_device(pmc_match, &ofdev->dev);
if (!match)
return -EINVAL;
type = match->data;
if (!of_device_is_available(np))
return -ENODEV;
has_deep_sleep = type->has_deep_sleep;
immrbase = get_immrbase();
pmc_dev = ofdev;
is_pci_agent = mpc83xx_is_pci_agent();
if (is_pci_agent < 0)
return is_pci_agent;
ret = of_address_to_resource(np, 0, &res);
if (ret)
return -ENODEV;
pmc_irq = irq_of_parse_and_map(np, 0);
if (pmc_irq != NO_IRQ) {
ret = request_irq(pmc_irq, pmc_irq_handler, IRQF_SHARED,
"pmc", ofdev);
if (ret)
return -EBUSY;
}
pmc_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
if (!pmc_regs) {
ret = -ENOMEM;
goto out;
}
ret = of_address_to_resource(np, 1, &res);
if (ret) {
ret = -ENODEV;
goto out_pmc;
}
clock_regs = ioremap(res.start, sizeof(struct mpc83xx_pmc));
if (!clock_regs) {
ret = -ENOMEM;
goto out_pmc;
}
if (has_deep_sleep) {
syscr_regs = ioremap(immrbase + IMMR_SYSCR_OFFSET,
sizeof(*syscr_regs));
if (!syscr_regs) {
ret = -ENOMEM;
goto out_syscr;
}
}
if (is_pci_agent)
mpc83xx_set_agent();
suspend_set_ops(&mpc83xx_suspend_ops);
return 0;
out_syscr:
iounmap(clock_regs);
out_pmc:
iounmap(pmc_regs);
out:
if (pmc_irq != NO_IRQ)
free_irq(pmc_irq, ofdev);
return ret;
}
void __init tegra_init_timer(struct device_node *np)
{
struct clk *clk;
int ret;
unsigned long rate;
struct resource res;
if (of_address_to_resource(np, 0, &res)) {
pr_err("%s:No memory resources found\n", __func__);
return;
}
timer_reg_base = ioremap(res.start, resource_size(&res));
if (!timer_reg_base) {
pr_err("%s:Can't map timer registers\n", __func__);
BUG();
}
timer_reg_base_pa = res.start;
tegra_timer_irq.irq = irq_of_parse_and_map(np, 0);
if (tegra_timer_irq.irq <= 0) {
pr_err("%s:Failed to map timer IRQ\n", __func__);
BUG();
}
clk = of_clk_get(np, 0);
if (IS_ERR(clk))
clk = clk_get_sys("timer", NULL);
if (IS_ERR(clk)) {
pr_warn("Unable to get timer clock. Assuming 12Mhz input clock.\n");
rate = 12000000;
} else {
clk_prepare_enable(clk);
rate = clk_get_rate(clk);
}
switch (rate) {
case 12000000:
timer_writel(0x000b, TIMERUS_USEC_CFG);
break;
case 12800000:
timer_writel(0x043F, TIMERUS_USEC_CFG);
break;
case 13000000:
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
case 19200000:
timer_writel(0x045f, TIMERUS_USEC_CFG);
break;
case 26000000:
timer_writel(0x0019, TIMERUS_USEC_CFG);
break;
#ifndef CONFIG_ARCH_TEGRA_2x_SOC
case 16800000:
timer_writel(0x0453, TIMERUS_USEC_CFG);
break;
case 38400000:
timer_writel(0x04BF, TIMERUS_USEC_CFG);
break;
case 48000000:
timer_writel(0x002F, TIMERUS_USEC_CFG);
break;
#endif
default:
if (tegra_platform_is_qt()) {
timer_writel(0x000c, TIMERUS_USEC_CFG);
break;
}
WARN(1, "Unknown clock rate");
}
#ifdef CONFIG_PM_SLEEP
hotplug_cpu_register(np);
#endif
of_node_put(np);
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
tegra20_init_timer();
#else
tegra30_init_timer();
#endif
ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US,
"timer_us", 1000000, 300, 32,
clocksource_mmio_readl_up);
if (ret) {
pr_err("%s: Failed to register clocksource: %d\n",
__func__, ret);
BUG();
}
ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
if (ret) {
pr_err("%s: Failed to register timer IRQ: %d\n",
__func__, ret);
BUG();
}
clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
tegra_clockevent.max_delta_ns =
clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
tegra_clockevent.min_delta_ns =
clockevent_delta2ns(0x1, &tegra_clockevent);
tegra_clockevent.cpumask = cpu_all_mask;
tegra_clockevent.irq = tegra_timer_irq.irq;
clockevents_register_device(&tegra_clockevent);
#ifndef CONFIG_ARM64
#ifdef CONFIG_ARM_ARCH_TIMER
/* Architectural timers take precedence over broadcast timers.
Only register a broadcast clockevent device if architectural
timers do not exist or cannot be initialized. */
if (tegra_init_arch_timer())
#endif
/* Architectural timers do not exist or cannot be initialzied.
Fall back to using the broadcast timer as the sched clock. */
setup_sched_clock(tegra_read_sched_clock, 32, 1000000);
#endif
register_syscore_ops(&tegra_timer_syscore_ops);
#ifndef CONFIG_ARM64
late_time_init = tegra_init_late_timer;
#endif
//arm_delay_ops.delay = __tegra_delay;
//arm_delay_ops.const_udelay = __tegra_const_udelay;
//arm_delay_ops.udelay = __tegra_udelay;
}
static int uec_mdio_probe(struct of_device *ofdev, const struct of_device_id *match)
{
struct device *device = &ofdev->dev;
struct device_node *np = ofdev->node, *tempnp = NULL;
struct device_node *child = NULL;
struct ucc_mii_mng __iomem *regs;
struct mii_bus *new_bus;
struct resource res;
int k, err = 0;
new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL);
if (NULL == new_bus)
return -ENOMEM;
new_bus->name = "UCC Ethernet Controller MII Bus";
new_bus->read = &uec_mdio_read;
new_bus->write = &uec_mdio_write;
new_bus->reset = &uec_mdio_reset;
memset(&res, 0, sizeof(res));
err = of_address_to_resource(np, 0, &res);
if (err)
goto reg_map_fail;
new_bus->id = res.start;
new_bus->irq = kmalloc(32 * sizeof(int), GFP_KERNEL);
if (NULL == new_bus->irq) {
err = -ENOMEM;
goto reg_map_fail;
}
for (k = 0; k < 32; k++)
new_bus->irq[k] = PHY_POLL;
while ((child = of_get_next_child(np, child)) != NULL) {
int irq = irq_of_parse_and_map(child, 0);
if (irq != NO_IRQ) {
const u32 *id = of_get_property(child, "reg", NULL);
new_bus->irq[*id] = irq;
}
}
/* Set the base address */
regs = ioremap(res.start, sizeof(struct ucc_mii_mng));
if (NULL == regs) {
err = -ENOMEM;
goto ioremap_fail;
}
new_bus->priv = (void __force *)regs;
new_bus->dev = device;
dev_set_drvdata(device, new_bus);
/* Read MII management master from device tree */
while ((tempnp = of_find_compatible_node(tempnp, "network", "ucc_geth"))
!= NULL) {
struct resource tempres;
err = of_address_to_resource(tempnp, 0, &tempres);
if (err)
goto bus_register_fail;
/* if our mdio regs fall within this UCC regs range */
if ((res.start >= tempres.start) &&
(res.end <= tempres.end)) {
/* set this UCC to be the MII master */
const u32 *id = of_get_property(tempnp, "device-id", NULL);
if (id == NULL)
goto bus_register_fail;
ucc_set_qe_mux_mii_mng(*id - 1);
/* assign the TBI an address which won't
* conflict with the PHYs */
out_be32(®s->utbipar, UTBIPAR_INIT_TBIPA);
break;
}
}
err = mdiobus_register(new_bus);
if (0 != err) {
printk(KERN_ERR "%s: Cannot register as MDIO bus\n",
new_bus->name);
goto bus_register_fail;
}
return 0;
bus_register_fail:
iounmap(regs);
ioremap_fail:
kfree(new_bus->irq);
reg_map_fail:
kfree(new_bus);
return err;
}
static void __init mpc8xxx_add_controller(struct device_node *np)
{
struct mpc8xxx_gpio_chip *mpc8xxx_gc;
struct of_mm_gpio_chip *mm_gc;
struct gpio_chip *gc;
const struct of_device_id *id;
unsigned hwirq;
int ret;
mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
if (!mpc8xxx_gc) {
ret = -ENOMEM;
goto err;
}
spin_lock_init(&mpc8xxx_gc->lock);
mm_gc = &mpc8xxx_gc->mm_gc;
gc = &mm_gc->gc;
mm_gc->save_regs = mpc8xxx_gpio_save_regs;
gc->ngpio = MPC8XXX_GPIO_PINS;
gc->direction_input = mpc8xxx_gpio_dir_in;
gc->direction_output = of_device_is_compatible(np, "fsl,mpc5121-gpio") ?
mpc5121_gpio_dir_out : mpc8xxx_gpio_dir_out;
gc->get = of_device_is_compatible(np, "fsl,mpc8572-gpio") ?
mpc8572_gpio_get : mpc8xxx_gpio_get;
gc->set = mpc8xxx_gpio_set;
gc->to_irq = mpc8xxx_gpio_to_irq;
ret = of_mm_gpiochip_add(np, mm_gc);
if (ret)
goto err;
hwirq = irq_of_parse_and_map(np, 0);
if (hwirq == NO_IRQ)
goto skip_irq;
mpc8xxx_gc->irq = irq_domain_add_linear(np, MPC8XXX_GPIO_PINS,
&mpc8xxx_gpio_irq_ops, mpc8xxx_gc);
if (!mpc8xxx_gc->irq)
goto skip_irq;
id = of_match_node(mpc8xxx_gpio_ids, np);
if (id)
mpc8xxx_gc->of_dev_id_data = id->data;
/* ack and mask all irqs */
out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
out_be32(mm_gc->regs + GPIO_IMR, 0);
irq_set_handler_data(hwirq, mpc8xxx_gc);
irq_set_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
skip_irq:
return;
err:
pr_err("%s: registration failed with status %d\n",
np->full_name, ret);
kfree(mpc8xxx_gc);
return;
}
static int tdm_fsl_probe(struct platform_device *ofdev)
{
int ret = 0;
struct tdm_priv *priv;
struct resource res;
priv = kzalloc(sizeof(struct tdm_priv), GFP_KERNEL);
if (!priv) {
ret = -ENOMEM;
goto err_alloc;
}
dev_set_drvdata(&ofdev->dev, priv);
priv->device = &ofdev->dev;
ret = of_address_to_resource(ofdev->dev.of_node, 0, &res);
if (ret) {
ret = -EINVAL;
goto err_resource;
}
priv->ptdm_base = (u32)res.start;
priv->tdm_regs = of_iomap(ofdev->dev.of_node, 0);
if (!priv->tdm_regs) {
ret = -ENOMEM;
goto err_tdmregs;
}
priv->dmac_regs = of_iomap(ofdev->dev.of_node, 1);
if (!priv->dmac_regs) {
ret = -ENOMEM;
goto err_dmacreg;
}
/* tdmrd tmdtd at immrbar+0x16100 */
priv->data_regs =
(struct tdm_data *)(TDM_DATAREG_OFFSET + (u8 *)priv->tdm_regs);
/* TDMCLK_DIV_VAL_RX/TX at TDMBASE+0x180 */
priv->clk_regs =
(struct tdm_clock *)(TDM_CLKREG_OFFSET + (u8 *)priv->tdm_regs);
priv->dmac_done_intr = irq_of_parse_and_map(ofdev->dev.of_node, 0);
if (priv->dmac_done_intr == NO_IRQ) {
ret = -EINVAL;
goto err_dmacdone_irqmap;
}
ret =
request_irq(priv->dmac_done_intr, dmac_done_isr, 0, "dmac_done_isr",
priv);
if (ret)
goto err_dmacdoneisr;
priv->adap = &tdm_fsl_ops;
/* Wait q initilization */
priv->adap->tdm_rx_flag = 0;
/* todo - these should be configured by dts or init time */
tdm_set_adapdata(priv->adap, priv);
priv->adap->parent = &ofdev->dev;
ret = tdm_add_adapter(priv->adap);
if (ret < 0) {
dev_err(priv->device, "failed to add adapter\n");
goto fail_adapter;
}
ret = init_tdm(priv);
if (ret)
goto err_tdminit;
ret = tdm_fsl_reg_init(priv);
if (ret)
goto err_tdminit;
spin_lock_init(&priv->tdmlock);
spin_lock(&priv->tdmlock);
priv->tdm_active = 0;
spin_unlock(&priv->tdmlock);
if (tdmen) {
ret = tdm_fsl_enable(priv->adap);
if (!ret)
goto err_tdminit;
}
return 0;
err_tdminit:
fail_adapter:
free_irq(priv->dmac_done_intr, priv);
err_dmacdoneisr:
free_irq(priv->tdm_err_intr, priv);
err_dmacdone_irqmap:
irq_dispose_mapping(priv->dmac_done_intr);
err_dmacreg:
iounmap(priv->dmac_regs);
err_tdmregs:
err_resource:
dev_set_drvdata(&ofdev->dev, NULL);
kfree(priv);
err_alloc:
return ret;
}
static int __devinit
mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
{
unsigned int ipb_freq;
struct resource res_mem;
int ata_irq;
struct mpc52xx_ata __iomem *ata_regs;
struct mpc52xx_ata_priv *priv;
int rv;
/* Get ipb frequency */
ipb_freq = mpc52xx_find_ipb_freq(op->node);
if (!ipb_freq) {
printk(KERN_ERR DRV_NAME ": "
"Unable to find IPB Bus frequency\n" );
return -ENODEV;
}
/* Get IRQ and register */
rv = of_address_to_resource(op->node, 0, &res_mem);
if (rv) {
printk(KERN_ERR DRV_NAME ": "
"Error while parsing device node resource\n" );
return rv;
}
ata_irq = irq_of_parse_and_map(op->node, 0);
if (ata_irq == NO_IRQ) {
printk(KERN_ERR DRV_NAME ": "
"Error while mapping the irq\n");
return -EINVAL;
}
/* Request mem region */
if (!devm_request_mem_region(&op->dev, res_mem.start,
sizeof(struct mpc52xx_ata), DRV_NAME)) {
printk(KERN_ERR DRV_NAME ": "
"Error while requesting mem region\n");
rv = -EBUSY;
goto err;
}
/* Remap registers */
ata_regs = devm_ioremap(&op->dev, res_mem.start,
sizeof(struct mpc52xx_ata));
if (!ata_regs) {
printk(KERN_ERR DRV_NAME ": "
"Error while mapping register set\n");
rv = -ENOMEM;
goto err;
}
/* Prepare our private structure */
priv = devm_kzalloc(&op->dev, sizeof(struct mpc52xx_ata_priv),
GFP_ATOMIC);
if (!priv) {
printk(KERN_ERR DRV_NAME ": "
"Error while allocating private structure\n");
rv = -ENOMEM;
goto err;
}
priv->ipb_period = 1000000000 / (ipb_freq / 1000);
priv->ata_regs = ata_regs;
priv->ata_irq = ata_irq;
priv->csel = -1;
/* Init the hw */
rv = mpc52xx_ata_hw_init(priv);
if (rv) {
printk(KERN_ERR DRV_NAME ": Error during HW init\n");
goto err;
}
/* Register ourselves to libata */
rv = mpc52xx_ata_init_one(&op->dev, priv, res_mem.start);
if (rv) {
printk(KERN_ERR DRV_NAME ": "
"Error while registering to ATA layer\n");
return rv;
}
/* Done */
return 0;
/* Error path */
err:
irq_dispose_mapping(ata_irq);
return rv;
}
static int __devinit mpc52xx_lpbfifo_probe(struct platform_device *op)
{
struct resource res;
int rc = -ENOMEM;
if (lpbfifo.dev != NULL)
return -ENOSPC;
lpbfifo.irq = irq_of_parse_and_map(op->dev.of_node, 0);
if (!lpbfifo.irq)
return -ENODEV;
if (of_address_to_resource(op->dev.of_node, 0, &res))
return -ENODEV;
lpbfifo.regs_phys = res.start;
lpbfifo.regs = of_iomap(op->dev.of_node, 0);
if (!lpbfifo.regs)
return -ENOMEM;
spin_lock_init(&lpbfifo.lock);
/* */
out_be32(lpbfifo.regs + LPBFIFO_REG_ENABLE, 0x01010000);
/* */
rc = request_irq(lpbfifo.irq, mpc52xx_lpbfifo_irq, 0,
"mpc52xx-lpbfifo", &lpbfifo);
if (rc)
goto err_irq;
/* */
lpbfifo.bcom_rx_task =
bcom_gen_bd_rx_init(2, res.start + LPBFIFO_REG_FIFO_DATA,
BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC,
16*1024*1024);
if (!lpbfifo.bcom_rx_task)
goto err_bcom_rx;
rc = request_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task),
mpc52xx_lpbfifo_bcom_irq, 0,
"mpc52xx-lpbfifo-rx", &lpbfifo);
if (rc)
goto err_bcom_rx_irq;
lpbfifo.dma_irqs_enabled = 1;
/* */
lpbfifo.bcom_tx_task =
bcom_gen_bd_tx_init(2, res.start + LPBFIFO_REG_FIFO_DATA,
BCOM_INITIATOR_SCLPC, BCOM_IPR_SCLPC);
if (!lpbfifo.bcom_tx_task)
goto err_bcom_tx;
lpbfifo.dev = &op->dev;
return 0;
err_bcom_tx:
free_irq(bcom_get_task_irq(lpbfifo.bcom_rx_task), &lpbfifo);
err_bcom_rx_irq:
bcom_gen_bd_rx_release(lpbfifo.bcom_rx_task);
err_bcom_rx:
err_irq:
iounmap(lpbfifo.regs);
lpbfifo.regs = NULL;
dev_err(&op->dev, "mpc52xx_lpbfifo_probe() failed\n");
return -ENODEV;
}
static int __init xilinx_iic_probe(struct of_device *of_dev,
const struct of_device_id *match)
{
XIic_Config xiic_cfg;
struct xiic_data *dev;
char *scan_results;
struct resource mem;
struct device_node *dev_node = of_dev->node;
int error;
const u32 *did;
/* Allocate the dev and zero it out. */
dev = kzalloc(sizeof(struct xiic_data), SLAB_KERNEL);
if (!dev) {
dev_err(&of_dev->dev, "Cannot allocate struct xiic_data\n");
error = -ENOMEM;
goto out2;
}
dev_set_drvdata(&of_dev->dev, dev);
/* get resources from device tree */
dev->irq = irq_of_parse_and_map(dev_node, 0);
if (dev->irq == 0 /* NOIRQ */ ) {
error = -ENODEV;
goto out;
}
if (of_address_to_resource(dev_node, 0, &mem)) {
error = -ENODEV;
goto out;
}
/* initialize fields to satisfy i2c */
strcpy(dev->adap.name, of_dev->dev.bus_id);
did = of_get_property(dev_node, "index", NULL);
if (did == NULL) {
printk
("%s: Can not get device index from device tree, assume 0\n",
__FUNCTION__);
dev->index = 0;
} else
dev->index = *did;
init_completion(&dev->complete);
memset(&xiic_cfg, 0, sizeof(XIic_Config));
xiic_cfg.DeviceId = dev->index;
/* Change the addresses to be virtual; save the old ones to restore. */
dev->base = mem.start;
xiic_cfg.BaseAddress =
(u32) ioremap(mem.start, mem.end - mem.start + 1);
dev->remapped = 1;
down(&cfg_sem);
/* Tell the Xilinx code to bring this IIC interface up. */
if (XIic_CfgInitialize(&dev->Iic, &xiic_cfg, xiic_cfg.BaseAddress) !=
XST_SUCCESS) {
up(&cfg_sem);
dev_err(&of_dev->dev, "could not initialize device.\n");
error = -ENODEV;
goto out;
}
up(&cfg_sem);
XIic_SetRecvHandler(&dev->Iic, (void *)dev, RecvHandler);
XIic_SetSendHandler(&dev->Iic, (void *)dev, SendHandler);
XIic_SetStatusHandler(&dev->Iic, (void *)dev, StatusHandler);
/* Grab the IRQ */
error = request_irq(dev->irq, xiic_interrupt, 0, dev->adap.name, dev);
if (error) {
dev_err(&of_dev->dev, "could not allocate interrupt %d.\n",
dev->irq);
goto out;
}
dev->reqirq = 1;
if (XIic_Start(&dev->Iic) != XST_SUCCESS) {
dev_err(&of_dev->dev, "could not start device\n");
error = -ENODEV;
goto out;
}
dev->started = 1;
/* Now tell the core I2C code about our new device. */
/*
* SAATODO: Get a real ID (perhaps I2C_HW_XILINX) after
* initial release. Will need to email [email protected]
* per http://www2.lm-sensors.nu/~lm78/support.html
*/
dev->adap.id = I2C_DRIVERID_I2CDEV;
dev->adap.algo = &xiic_algo;
dev->adap.algo_data = NULL;
dev->adap.timeout = XIIC_TIMEOUT;
dev->adap.retries = XIIC_RETRY;
error = i2c_add_adapter(&dev->adap);
if (error) {
dev_err(&of_dev->dev, "could not add i2c adapter\n");
goto out;
}
dev->added = 1;
printk("%s #%d at 0x%08X mapped to 0x%08X, irq=%d\n",
dev->adap.name, dev->index,
dev->base, dev->Iic.BaseAddress, dev->irq);
if (scan) {
scan_results = xilinx_iic_do_scan(dev);
if (scan_results) {
printk(scan_results);
kfree(scan_results);
}
}
device_create_file(&of_dev->dev, &dev_attr_scan);
out:
if (error)
xilinx_iic_remove(of_dev);
out2:
return error;
}
