Example #1
0
static void tc3589x_irq_remove(struct tc3589x *tc3589x)
{
	int base = tc3589x->irq_base;
	int irq;

	for (irq = base; irq < base + TC3589x_NR_INTERNAL_IRQS; irq++) {
#ifdef CONFIG_ARM
		set_irq_flags(irq, 0);
#endif
		irq_set_chip_and_handler(irq, NULL, NULL);
		irq_set_chip_data(irq, NULL);
	}
}
Example #2
0
static int mpc8xxx_gpio_irq_map(struct irq_domain *h, unsigned int irq,
                                irq_hw_number_t hwirq)
{
    struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;

    if (mpc8xxx_gc->of_dev_id_data)
        mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;

    irq_set_chip_data(irq, h->host_data);
    irq_set_chip_and_handler(irq, &mpc8xxx_irq_chip, handle_level_irq);

    return 0;
}
Example #3
0
static int mdp5_hw_irqdomain_map(struct irq_domain *d,
		unsigned int irq, irq_hw_number_t hwirq)
{
	struct mdp5_kms *mdp5_kms = d->host_data;

	if (!(VALID_IRQS & (1 << hwirq)))
		return -EPERM;

	irq_set_chip_and_handler(irq, &mdp5_hw_irq_chip, handle_level_irq);
	irq_set_chip_data(irq, mdp5_kms);

	return 0;
}
Example #4
0
int __init setup_hd64461(void)
{
	int i, nid = cpu_to_node(boot_cpu_data);

	if (!MACH_HD64461)
		return 0;

	printk(KERN_INFO
	       "HD64461 configured at 0x%x on irq %d(mapped into %d to %d)\n",
	       HD64461_IOBASE, CONFIG_HD64461_IRQ, HD64461_IRQBASE,
	       HD64461_IRQBASE + 15);

/* Should be at processor specific part.. */
#if defined(CONFIG_CPU_SUBTYPE_SH7709)
	__raw_writew(0x2240, INTC_ICR1);
#endif
	__raw_writew(0xffff, HD64461_NIMR);

	/*  IRQ 80 -> 95 belongs to HD64461  */
	for (i = HD64461_IRQBASE; i < HD64461_IRQBASE + 16; i++) {
		unsigned int irq;

		irq = create_irq_nr(i, nid);
		if (unlikely(irq == 0)) {
			pr_err("%s: failed hooking irq %d for HD64461\n",
			       __func__, i);
			return -EBUSY;
		}

		if (unlikely(irq != i)) {
			pr_err("%s: got irq %d but wanted %d, bailing.\n",
			       __func__, irq, i);
			destroy_irq(irq);
			return -EINVAL;
		}

		irq_set_chip_and_handler(i, &hd64461_irq_chip,
					 handle_level_irq);
	}

	irq_set_chained_handler(CONFIG_HD64461_IRQ, hd64461_irq_demux);
	irq_set_irq_type(CONFIG_HD64461_IRQ, IRQ_TYPE_LEVEL_LOW);

#ifdef CONFIG_HD64461_ENABLER
	printk(KERN_INFO "HD64461: enabling PCMCIA devices\n");
	__raw_writeb(0x4c, HD64461_PCC1CSCIER);
	__raw_writeb(0x00, HD64461_PCC1CSCR);
#endif

	return 0;
}
Example #5
0
/*
 * Called from the processor-specific init to enable GPIO interrupt support.
 */
void __init at91_gpio_irq_setup(void)
{
	unsigned		pioc;
	int			gpio_irqnbr = 0;
	struct at91_gpio_chip	*this, *prev;

	/* Setup proper .irq_set_type function */
	if (has_pio3())
		gpio_irqchip.irq_set_type = alt_gpio_irq_type;
	else
		gpio_irqchip.irq_set_type = gpio_irq_type;

	for (pioc = 0, this = gpio_chip, prev = NULL;
			pioc++ < gpio_banks;
			prev = this, this++) {
		int offset;

		__raw_writel(~0, this->regbase + PIO_IDR);

		/* setup irq domain for this GPIO controller */
		at91_gpio_irqdomain(this);

		for (offset = 0; offset < this->chip.ngpio; offset++) {
			unsigned int virq = irq_find_mapping(this->domain, offset);
			irq_set_lockdep_class(virq, &gpio_lock_class);

			/*
			 * Can use the "simple" and not "edge" handler since it's
			 * shorter, and the AIC handles interrupts sanely.
			 */
			irq_set_chip_and_handler(virq, &gpio_irqchip,
						 handle_simple_irq);
			set_irq_flags(virq, IRQF_VALID);
			irq_set_chip_data(virq, this);

			gpio_irqnbr++;
		}

		/* The toplevel handler handles one bank of GPIOs, except
		 * on some SoC it can handles up to three...
		 * We only set up the handler for the first of the list.
		 */
		if (prev && prev->next == this)
			continue;

		this->pioc_virq = irq_create_mapping(NULL, this->pioc_hwirq);
		irq_set_chip_data(this->pioc_virq, this);
		irq_set_chained_handler(this->pioc_virq, gpio_irq_handler);
	}
	pr_info("AT91: %d gpio irqs in %d banks\n", gpio_irqnbr, gpio_banks);
}
Example #6
0
/**
 * @brief: machine interrupt initial
 * 
 * @author: caolianming
 * @date: 2014-01-09
 * @param [in] void:
 */
void __init ak39_init_irq(void)
{
	int i;
	
	/* 1st, clear all interrupts */
	__raw_readl(AK_INT_STATUS);
	__raw_readl(AK_SYSCTRL_INT_STATUS);

	/* 2nd, mask all interrutps */
	__raw_writel(0x0, AK_IRQ_MASK);
	__raw_writel(0x0, AK_FIQ_MASK);
	__raw_writel(0x0, AK_SYSCTRL_INT_MASK);

	/* mask all gpio interrupts */
	__raw_writel(0x0, AK_GPIO_INT_MASK1);
	__raw_writel(0x0, AK_GPIO_INT_MASK2);

	/* mask all l2 interrupts */
	__raw_writel(0x0, AK_L2MEM_IRQ_ENABLE);

	for (i = IRQ_MEM; i <= IRQ_USBOTG_DMA; i++) {
		irq_set_chip_and_handler(i, &ak39_irq_chip, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	irq_set_chained_handler(IRQ_SYSCTRL, ak39_sysctrl_handler);

	for (i = IRQ_SARADC; i <= IRQ_RTC_WATCHDOG; i++) {
		irq_set_chip_and_handler(i, &ak39_sysctrl_chip, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
	irq_set_chained_handler(IRQ_GPIO, ak39_gpio_irqhandler);

	for (i = IRQ_GPIO_0; i < NR_IRQS; i++) {
		irq_set_chip_and_handler(i, &ak39_gpioirq_chip, handle_level_irq);
		set_irq_flags(i, IRQF_VALID);
	}
}
static int wcd9xxx_irq_setup_downstream_irq(
			struct wcd9xxx_core_resource *wcd9xxx_res)
{
	int irq, virq, ret;

	pr_debug("%s: enter\n", __func__);

	for (irq = 0; irq < wcd9xxx_res->num_irqs; irq++) {
		
		virq = wcd9xxx_map_irq(wcd9xxx_res, irq);
		pr_debug("%s: irq %d -> %d\n", __func__, irq, virq);
		if (virq == NO_IRQ) {
			pr_err("%s, No interrupt specifier for irq %d\n",
			       __func__, irq);
			return NO_IRQ;
		}

		ret = irq_set_chip_data(virq, wcd9xxx_res);
		if (ret) {
			pr_err("%s: Failed to configure irq %d (%d)\n",
			       __func__, irq, ret);
			return ret;
		}

		if (wcd9xxx_res->irq_level_high[irq])
			irq_set_chip_and_handler(virq, &wcd9xxx_irq_chip,
						 handle_level_irq);
		else
			irq_set_chip_and_handler(virq, &wcd9xxx_irq_chip,
						 handle_edge_irq);

		irq_set_nested_thread(virq, 1);
	}

	pr_debug("%s: leave\n", __func__);

	return 0;
}
Example #8
0
static int icoll_irq_domain_map(struct irq_domain *d, unsigned int virq,
				irq_hw_number_t hw)
{
	struct irq_chip *chip;

	if (icoll_priv.type == ICOLL)
		chip = &mxs_icoll_chip;
	else
		chip = &asm9260_icoll_chip;

	irq_set_chip_and_handler(virq, chip, handle_level_irq);

	return 0;
}
Example #9
0
static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
				      irq_hw_number_t hw)
{
	struct intc_irqpin_priv *p = h->host_data;

	p->irq[hw].domain_irq = virq;
	p->irq[hw].hw_irq = hw;

	intc_irqpin_dbg(&p->irq[hw], "map");
	irq_set_chip_data(virq, h->host_data);
	irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class);
	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	return 0;
}
Example #10
0
static int at91_aic_irq_map(struct irq_domain *h, unsigned int virq,
							irq_hw_number_t hw)
{
	/* Put virq number in Source Vector Register */
	at91_aic_write(AT91_AIC_SVR(hw), virq);

	/* Active Low interrupt, without priority */
	at91_aic_write(AT91_AIC_SMR(hw), AT91_AIC_SRCTYPE_LOW);

	irq_set_chip_and_handler(virq, &at91_aic_chip, handle_level_irq);
	set_irq_flags(virq, IRQF_VALID | IRQF_PROBE);

	return 0;
}
Example #11
0
void __init arch_init_irq(void)
{
	int i;

	mips_cpu_irq_init();

	for (i = 0; i <= SURFBOARDINT_END; i++)
		irq_set_chip_and_handler(i, &ralink_irq_chip, handle_level_irq);

	set_c0_status(ST0_IM);

	/* Enable global interrupt bit */
	*(volatile u32 *)(RALINK_INTENA) = M_SURFBOARD_GLOBAL_INT;
}
static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
		irq_hw_number_t hwirq)
{
	struct fpga_irq_data *f = d->host_data;

	/* Skip invalid IRQs, only register handlers for the real ones */
	if (!(f->valid & BIT(hwirq)))
		return -EPERM;
	irq_set_chip_data(irq, f);
	irq_set_chip_and_handler(irq, &f->chip,
				handle_level_irq);
	set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
	return 0;
}
Example #13
0
static int opb_host_map(struct irq_domain *host, unsigned int virq,
		irq_hw_number_t hwirq)
{
	struct opb_pic *opb;

	opb = host->host_data;


	irq_set_chip_data(virq, opb);
	irq_set_chip_and_handler(virq, &opb_irq_chip, handle_level_irq);
	irq_set_irq_type(virq, IRQ_TYPE_NONE);

	return 0;
}
Example #14
0
/*
 * irq init
 */
static void __init init_adm8668_irqs(void)
{
	int i;

	/* disable all interrupts for the moment */
	intc_write_reg(IRQ_MASK, IRQ_DISABLE_REG);

	for (i = 0; i <= ADM8668_IRQ_MAX; i++)
		irq_set_chip_and_handler(i, &adm8668_irq_type,
			handle_level_irq);

	/* hw0 is where our interrupts are uh.. interrupted at. */
	set_c0_status(IE_IRQ0);
}
Example #15
0
static int s3c24xx_irq_map_of(struct irq_domain *h, unsigned int virq,
							irq_hw_number_t hw)
{
	unsigned int ctrl_num = hw / 32;
	unsigned int intc_hw = hw % 32;
	struct s3c_irq_intc *intc = s3c_intc[ctrl_num];
	struct s3c_irq_intc *parent_intc = intc->parent;
	struct s3c_irq_data *irq_data = &intc->irqs[intc_hw];

	/* attach controller pointer to irq_data */
	irq_data->intc = intc;
	irq_data->offset = intc_hw;

	if (!parent_intc)
		irq_set_chip_and_handler(virq, &s3c_irq_chip, handle_edge_irq);
	else
		irq_set_chip_and_handler(virq, &s3c_irq_level_chip,
					 handle_edge_irq);

	irq_set_chip_data(virq, irq_data);

	return 0;
}
Example #16
0
void mcp2210_irq_disable(struct mcp2210_device *dev)
{
	mcp2210_info();
	if (dev->is_irq_probed) {
		const int virq_end = dev->irq_base + dev->nr_irqs;
		int virq;

		for (virq = dev->irq_base; virq < virq_end; ++virq) {
			irq_set_status_flags(virq, IRQ_NOREQUEST);
			irq_set_chip_and_handler(virq, NULL, NULL);
			synchronize_irq(virq);
		}
	}
}
static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
                                irq_hw_number_t hw)
{
    struct mpc8xxx_gpio_chip *mpc8xxx_gc = h->host_data;

    if (mpc8xxx_gc->of_dev_id_data)
        mpc8xxx_irq_chip.irq_set_type = mpc8xxx_gc->of_dev_id_data;

    irq_set_chip_data(virq, h->host_data);
    irq_set_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
    irq_set_irq_type(virq, IRQ_TYPE_NONE);

    return 0;
}
Example #18
0
static int pmc_irq_map(struct irq_domain *h, unsigned int virq,
                       irq_hw_number_t hw)
{
    struct at91_pmc	*pmc = h->host_data;

    irq_set_lockdep_class(virq, &pmc_lock_class);

    irq_set_chip_and_handler(virq, &pmc_irq,
                             handle_level_irq);
    set_irq_flags(virq, IRQF_VALID);
    irq_set_chip_data(virq, pmc);

    return 0;
}
static int irqc_irq_domain_map(struct irq_domain *h, unsigned int virq,
			       irq_hw_number_t hw)
{
	struct irqc_priv *p = h->host_data;

	p->irq[hw].domain_irq = virq;
	p->irq[hw].hw_irq = hw;

	irqc_dbg(&p->irq[hw], "map");
	irq_set_chip_data(virq, h->host_data);
	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
	set_irq_flags(virq, IRQF_VALID); /* kill me now */
	return 0;
}
Example #20
0
void __init arch_init_irq(void)
{
	int i;
	//extern irq_desc_t irq_desc[];

	/* init CPU irqs */
	mips_cpu_irq_init();

	/* init sys irqs */
	sys_irq_base = M36_SYS_IRQ_BASE;
	for (i=sys_irq_base; i < sys_irq_base + M36_NUM_SYS_IRQ; i++)
		irq_set_chip_and_handler(i, &sys_irq_controller,handle_percpu_irq);

	/* Default all ICU IRQs to off and enable IM bit(IP3) of CP0 status for sys IRQ */
#if 	1
	*((unsigned long *)(0xB8000038)) = 0;
	*((unsigned long *)(0xB800003C)) = 0;
	*((unsigned long *)(0xB80000EC)) = 0;
	write_c0_status(read_c0_status() | STATUSF_IP3);
#else
	*M6303_MSYSINT1REG = 0;
	*M6303_MSYSINT2REG = 0;
#endif 

#ifdef CONFIG_REMOTE_DEBUG
	printk("Setting debug traps - please connect the remote debugger.\n");

	set_debug_traps();

	// you may move this line to whereever you want
	breakpoint();
#endif

	if((*(unsigned short *)0xB8000002 == 0x3901)  \
      || (*(unsigned short *)0xB8000002 == 0x3701) \
	  || (*(unsigned short *)0xB8000002 == 0x3503))
	{
		sys_rpc_addr = 0xB8040037;
		sys_rpc_mask = 0x0C;
		sys_rpc_irq1_mask = 0x08;
		sys_rpc_irq2_mask = 0x04;
	}
	else
	{
		sys_rpc_addr = 0xB8040036;
		sys_rpc_mask = 0xC0;
		sys_rpc_irq1_mask = 0x80;
		sys_rpc_irq2_mask = 0x40;		
	}
}
Example #21
0
void systemasic_irq_init(void)
{
	int irq_base, i;

	irq_base = irq_alloc_descs(HW_EVENT_IRQ_BASE, HW_EVENT_IRQ_BASE,
				   HW_EVENT_IRQ_MAX - HW_EVENT_IRQ_BASE, -1);
	if (IS_ERR_VALUE(irq_base)) {
		pr_err("%s: failed hooking irqs\n", __func__);
		return;
	}

	for (i = HW_EVENT_IRQ_BASE; i < HW_EVENT_IRQ_MAX; i++)
		irq_set_chip_and_handler(i, &systemasic_int, handle_level_irq);
}
static int mv64x60_host_map(struct irq_domain *h, unsigned int virq,
			  irq_hw_number_t hwirq)
{
	int level1;

	irq_set_status_flags(virq, IRQ_LEVEL);

	level1 = (hwirq & MV64x60_LEVEL1_MASK) >> MV64x60_LEVEL1_OFFSET;
	BUG_ON(level1 > MV64x60_LEVEL1_GPP);
	irq_set_chip_and_handler(virq, mv64x60_chips[level1],
				 handle_level_irq);

	return 0;
}
Example #23
0
void __init arch_init_irq(void)
{
	int i;

	clear_c0_status(0xff04); /* clear ERL */
	set_c0_status(0x0400);   /* set IP2 */

	/* Set up MIPS CPU irq */
	mips_cpu_irq_init();

	/* Set up INTC irq */
	intc_base = ioremap(INTC_IOBASE, 0xfff);

	writel(0xffffffff, intc_base + IMSR_OFF);
	writel(0xffffffff, intc_base + PART_OFF + IMSR_OFF);
	for (i = IRQ_INTC_BASE; i < IRQ_INTC_BASE + INTC_NR_IRQS; i++) {
		irq_set_chip_data(i, (void *)(i - IRQ_INTC_BASE));
		irq_set_chip_and_handler(i, &jzintc_chip, handle_level_irq);
	}

	for (i = IRQ_OST_BASE; i < IRQ_OST_BASE + OST_NR_IRQS; i++) {
		irq_set_chip_data(i, (void *)(i - IRQ_OST_BASE));
		irq_set_chip_and_handler(i, &ost_irq_type, handle_level_irq);
	}
#ifdef CONFIG_SMP
	init_intc_affinity();
	set_intc_cpu(26,0);
	set_intc_cpu(27,1);
#endif
	/* enable cpu interrupt mask */
	set_c0_status(IE_IRQ0 | IE_IRQ1);

#ifdef CONFIG_SMP
	setup_ipi();
#endif
	return;
}
void __init ixdp2351_init_irq(void)
{
	int irq;

	/*                                                   */
	*IXDP2351_CPLD_INTA_MASK_SET_REG = (u16) -1;
	*IXDP2351_CPLD_INTB_MASK_SET_REG = (u16) -1;
	*IXDP2351_CPLD_INTA_SIM_REG = 0;
	*IXDP2351_CPLD_INTB_SIM_REG = 0;

	ixp23xx_init_irq();

	for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE);
	     irq <
	     IXP23XX_MACH_IRQ(IXDP2351_INTA_IRQ_BASE + IXDP2351_INTA_IRQ_NUM);
	     irq++) {
		if (IXDP2351_INTA_IRQ_MASK(irq) & IXDP2351_INTA_IRQ_VALID) {
			set_irq_flags(irq, IRQF_VALID);
			irq_set_chip_and_handler(irq, &ixdp2351_inta_chip,
						 handle_level_irq);
		}
	}

	for (irq = IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE);
	     irq <
	     IXP23XX_MACH_IRQ(IXDP2351_INTB_IRQ_BASE + IXDP2351_INTB_IRQ_NUM);
	     irq++) {
		if (IXDP2351_INTB_IRQ_MASK(irq) & IXDP2351_INTB_IRQ_VALID) {
			set_irq_flags(irq, IRQF_VALID);
			irq_set_chip_and_handler(irq, &ixdp2351_intb_chip,
						 handle_level_irq);
		}
	}

	irq_set_chained_handler(IRQ_IXP23XX_INTA, ixdp2351_inta_handler);
	irq_set_chained_handler(IRQ_IXP23XX_INTB, ixdp2351_intb_handler);
}
static int __devinit tps6586x_irq_init(struct tps6586x *tps6586x, int irq,
				       int irq_base)
{
	int i, ret;
	u8 tmp[4];

	if (!irq_base) {
		dev_warn(tps6586x->dev, "No interrupt support on IRQ base\n");
		return -EINVAL;
	}

	mutex_init(&tps6586x->irq_lock);
	for (i = 0; i < 5; i++) {
		tps6586x->mask_cache[i] = 0xff;
		tps6586x->mask_reg[i] = 0xff;
		tps6586x_write(tps6586x->dev, TPS6586X_INT_MASK1 + i, 0xff);
	}

	tps6586x_reads(tps6586x->dev, TPS6586X_INT_ACK1, sizeof(tmp), tmp);

	tps6586x->irq_base = irq_base;

	tps6586x->irq_chip.name = "tps6586x";
	tps6586x->irq_chip.irq_enable = tps6586x_irq_enable;
	tps6586x->irq_chip.irq_disable = tps6586x_irq_disable;
	tps6586x->irq_chip.irq_bus_lock = tps6586x_irq_lock;
	tps6586x->irq_chip.irq_bus_sync_unlock = tps6586x_irq_sync_unlock;

	for (i = 0; i < ARRAY_SIZE(tps6586x_irqs); i++) {
		int __irq = i + tps6586x->irq_base;
		irq_set_chip_data(__irq, tps6586x);
		irq_set_chip_and_handler(__irq, &tps6586x->irq_chip,
					 handle_simple_irq);
		irq_set_nested_thread(__irq, 1);
#ifdef CONFIG_ARM
		set_irq_flags(__irq, IRQF_VALID);
#endif
	}

	ret = request_threaded_irq(irq, NULL, tps6586x_irq, IRQF_ONESHOT,
				   "tps6586x", tps6586x);

	if (!ret) {
		device_init_wakeup(tps6586x->dev, 1);
		enable_irq_wake(irq);
	}

	return ret;
}
Example #26
0
int __init s5p_init_irq_eint(void)
{
	int irq;

	for (irq = IRQ_EINT(0); irq <= IRQ_EINT(15); irq++)
		irq_set_chip(irq, &s5p_irq_vic_eint);

	for (irq = IRQ_EINT(16); irq <= IRQ_EINT(31); irq++) {
		irq_set_chip_and_handler(irq, &s5p_irq_eint, handle_level_irq);
		set_irq_flags(irq, IRQF_VALID);
	}

	irq_set_chained_handler(IRQ_EINT16_31, s5p_irq_demux_eint16_31);
	return 0;
}
Example #27
0
static int max8997_irq_domain_map(struct irq_domain *d, unsigned int irq,
					irq_hw_number_t hw)
{
	struct max8997_dev *max8997 = d->host_data;

	irq_set_chip_data(irq, max8997);
	irq_set_chip_and_handler(irq, &max8997_irq_chip, handle_edge_irq);
	irq_set_nested_thread(irq, 1);
#ifdef CONFIG_ARM
	set_irq_flags(irq, IRQF_VALID);
#else
	irq_set_noprobe(irq);
#endif
	return 0;
}
Example #28
0
File: irq.c Project: 4oh4ed/linux
int cpu_claim_irq(unsigned int irq, struct irq_chip *type, void *data)
{
	if (irq_has_action(irq))
		return -EBUSY;
	if (irq_get_chip(irq) != &cpu_interrupt_type)
		return -EBUSY;

	/* for iosapic interrupts */
	if (type) {
		irq_set_chip_and_handler(irq, type, handle_percpu_irq);
		irq_set_chip_data(irq, data);
		__cpu_unmask_irq(irq);
	}
	return 0;
}
Example #29
0
static void claim_cpu_irqs(void)
{
	int i;
	for (i = CPU_IRQ_BASE; i <= CPU_IRQ_MAX; i++) {
		irq_set_chip_and_handler(i, &cpu_interrupt_type,
					 handle_percpu_irq);
	}

	irq_set_handler(TIMER_IRQ, handle_percpu_irq);
	setup_irq(TIMER_IRQ, &timer_action);
#ifdef CONFIG_SMP
	irq_set_handler(IPI_IRQ, handle_percpu_irq);
	setup_irq(IPI_IRQ, &ipi_action);
#endif
}
Example #30
0
void __init msm_init_sirc(void)
{
	int i;

	sirc_int_enable[0] = 0;
	sirc_int_enable[1] = 0;

	for (i = FIRST_SIRC_IRQ; i <= LAST_SIRC_IRQ; i++) {
		irq_set_chip_and_handler(i, &sirc_irq_chip, handle_edge_irq);
		set_irq_flags(i, IRQF_VALID);
	}

	irq_set_chained_handler(INT_SIRC_0, sirc_irq_handler);
	irq_set_irq_wake(INT_SIRC_0, 1);
}