int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); if (is_serdes_configured(SGMII_TSEC1)) { puts("eTSEC1 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; } num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); if (is_serdes_configured(SGMII_TSEC2)) { puts("eTSEC2 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); if (is_serdes_configured(SGMII_TSEC3)) { puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; } num++; #endif #ifdef CONFIG_TSEC4 SET_STD_TSEC_INFO(tsec_info[num], 4); if (is_serdes_configured(SGMII_TSEC4)) { puts("eTSEC4 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; } num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_init(tsec_info, num); #endif mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); }
int misc_init_r(void) { serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; __maybe_unused ccsr_gur_t *gur; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw3; gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_SRIO1 if (is_serdes_configured(SRIO1)) { set_next_law(CONFIG_SYS_RIO1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_RIO_1); } else { printf (" SRIO1: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO1); /* disable */ #endif #ifdef CONFIG_SRIO2 if (is_serdes_configured(SRIO2)) { set_next_law(CONFIG_SYS_RIO2_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_RIO_2); } else { printf (" SRIO2: disabled\n"); } #else setbits_be32(&gur->devdisr, FSL_CORENET_DEVDISR_SRIO2); /* disable */ #endif /* Warn if the expected SERDES reference clocks don't match the * actual reference clocks. This needs to be done after calling * p4080_erratum_serdes8(), since that function may modify the clocks. */ sw3 = in_8(&PIXIS_SW(3)); actual[0] = (sw3 & 0x40) ? SRDS_PLLCR0_RFCK_SEL_125 : SRDS_PLLCR0_RFCK_SEL_100; actual[1] = (sw3 & 0x20) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; actual[2] = (sw3 & 0x10) ? SRDS_PLLCR0_RFCK_SEL_156_25 : SRDS_PLLCR0_RFCK_SEL_125; for (i = 0; i < NUM_SRDS_BANKS; i++) { u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) { printf("Warning: SERDES bank %u expects reference clock" " %sMHz, but actual is %sMHz\n", i + 1, serdes_clock_to_string(expected), serdes_clock_to_string(actual[i])); } } return 0; }
int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[3]; int num = 0; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); if (is_serdes_configured(SGMII_TSEC1)) { puts("eTSEC1 is in sgmii mode\n"); tsec_info[num].flags |= TSEC_SGMII; tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; } else { tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; } num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); if (is_serdes_configured(SGMII_TSEC2)) { puts("eTSEC2 is in sgmii mode\n"); tsec_info[num].flags |= TSEC_SGMII; tsec_info[num].mii_devname = "LS1021A_SGMII_MDIO"; } else { tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); tsec_info[num].mii_devname = "LS1021A_RGMII_MDIO"; num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_FSL_SGMII_RISER fsl_sgmii_riser_init(tsec_info, num); #endif mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); /* Register the virtual MDIO front-ends */ ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_RGMII_MDIO"); ls1021a_mdio_init(DEFAULT_MII_NAME, "LS1021A_SGMII_MDIO"); tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); }
phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]); /* handle RGMII first */ if ((port == FM1_DTSEC2) && ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == FSL_CORENET_RCWSR13_MAC2_GMII_SEL_ENET_PORT)) { if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) return PHY_INTERFACE_MODE_RGMII; else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) return PHY_INTERFACE_MODE_MII; } if ((port == FM1_DTSEC4) && ((rcwsr13 & FSL_CORENET_RCWSR13_MAC2_GMII_SEL) == FSL_CORENET_RCWSR13_MAC2_GMII_SEL_L2_SWITCH)) { if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_RGMII) return PHY_INTERFACE_MODE_RGMII; else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == FSL_CORENET_RCWSR13_EC1_FM1_DTSEC4_MII) return PHY_INTERFACE_MODE_MII; } if (port == FM1_DTSEC5) { if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII) return PHY_INTERFACE_MODE_RGMII; else if ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_MII) return PHY_INTERFACE_MODE_MII; } switch (port) { case FM1_DTSEC1: case FM1_DTSEC2: if (is_serdes_configured(QSGMII_SW1_A + port - FM1_DTSEC1) || is_serdes_configured(SGMII_SW1_MAC1 + port - FM1_DTSEC1)) return PHY_INTERFACE_MODE_QSGMII; case FM1_DTSEC3: case FM1_DTSEC4: case FM1_DTSEC5: if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) return PHY_INTERFACE_MODE_SGMII; break; default: return PHY_INTERFACE_MODE_NONE; } return PHY_INTERFACE_MODE_NONE; }
phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr11 = in_be32(&gur->rcwsr[11]); if (is_device_disabled(port)) return PHY_INTERFACE_MODE_NONE; if ((port == FM1_10GEC1) && (is_serdes_configured(XAUI_FM1))) return PHY_INTERFACE_MODE_XGMII; if ((port == FM2_10GEC1) && (is_serdes_configured(XAUI_FM2))) return PHY_INTERFACE_MODE_XGMII; /* handle RGMII first */ if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_RGMII)) return PHY_INTERFACE_MODE_RGMII; if ((port == FM1_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC1) == FSL_CORENET_RCWSR11_EC1_FM1_DTSEC5_MII)) return PHY_INTERFACE_MODE_MII; if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_RGMII)) return PHY_INTERFACE_MODE_RGMII; if ((port == FM2_DTSEC5) && ((rcwsr11 & FSL_CORENET_RCWSR11_EC2) == FSL_CORENET_RCWSR11_EC2_FM2_DTSEC5_MII)) return PHY_INTERFACE_MODE_MII; switch (port) { case FM1_DTSEC1: case FM1_DTSEC2: case FM1_DTSEC3: case FM1_DTSEC4: case FM1_DTSEC5: if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) return PHY_INTERFACE_MODE_SGMII; break; case FM2_DTSEC1: case FM2_DTSEC2: case FM2_DTSEC3: case FM2_DTSEC4: case FM2_DTSEC5: if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) return PHY_INTERFACE_MODE_SGMII; break; default: return PHY_INTERFACE_MODE_NONE; } return PHY_INTERFACE_MODE_NONE; }
void ft_srio_setup(void *blob) { #ifdef CONFIG_SRIO1 if (!is_serdes_configured(SRIO1)) { fdt_del_node_and_alias(blob, "rio0"); } #else fdt_del_node_and_alias(blob, "rio0"); #endif #ifdef CONFIG_SRIO2 if (!is_serdes_configured(SRIO2)) { fdt_del_node_and_alias(blob, "rio1"); } #else fdt_del_node_and_alias(blob, "rio1"); #endif }
void erratum_a010315(void) { int i; for (i = PCIE1; i <= PCIE4; i++) if (!is_serdes_configured(i)) { debug("PCIe%d: disabled all R/W permission!\n", i); set_pcie_ns_access(i, 0); } }
static void ft_pcie_ls_setup(void *blob, const char *pci_compat, unsigned long ctrl_addr, enum srds_prtcl dev) { int off; off = fdt_node_offset_by_compat_reg(blob, pci_compat, (phys_addr_t)ctrl_addr); if (off < 0) return; if (!is_serdes_configured(dev)) fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0); }
int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; int num = 0; char *tmp; unsigned int vscfw_addr; #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); if (is_serdes_configured(SGMII_TSEC3)) { puts("eTSEC3 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; } num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_VSC7385_ENET /* If a VSC7385 microcode image is present, then upload it. */ if ((tmp = getenv ("vscfw_addr")) != NULL) { vscfw_addr = simple_strtoul (tmp, NULL, 16); printf("uploading VSC7385 microcode from %x\n", vscfw_addr); if (vsc7385_upload_firmware((void *) vscfw_addr, CONFIG_VSC7385_IMAGE_SIZE)) puts("Failure uploading VSC7385 microcode.\n"); } else puts("No address specified for VSC7385 microcode.\n"); #endif mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); return pci_eth_init(bis); }
phy_interface_t fman_port_enet_if(enum fm_port port) { struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]); if (is_device_disabled(port)) { printf("%s:%d: port(%d) is disabled\n", __func__, __LINE__, port); return PHY_INTERFACE_MODE_NONE; } if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) return PHY_INTERFACE_MODE_XGMII; if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9))) return PHY_INTERFACE_MODE_NONE; if (port == FM1_DTSEC3) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) { printf("%s:%d: port(FM1_DTSEC3) is OK\n", __func__, __LINE__); return PHY_INTERFACE_MODE_RGMII; } if (port == FM1_DTSEC4) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) { printf("%s:%d: port(FM1_DTSEC4) is OK\n", __func__, __LINE__); return PHY_INTERFACE_MODE_RGMII; } /* handle SGMII */ switch (port) { case FM1_DTSEC1: case FM1_DTSEC2: if ((port == FM1_DTSEC2) && is_serdes_configured(SGMII_2500_FM1_DTSEC2)) return PHY_INTERFACE_MODE_SGMII_2500; case FM1_DTSEC5: case FM1_DTSEC6: case FM1_DTSEC9: if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) return PHY_INTERFACE_MODE_SGMII; else if ((port == FM1_DTSEC9) && is_serdes_configured(SGMII_2500_FM1_DTSEC9)) return PHY_INTERFACE_MODE_SGMII_2500; break; default: break; } /* handle QSGMII */ switch (port) { case FM1_DTSEC1: case FM1_DTSEC2: case FM1_DTSEC5: case FM1_DTSEC6: /* only MAC 1,2,5,6 available for QSGMII */ if (is_serdes_configured(QSGMII_FM1_A)) return PHY_INTERFACE_MODE_QSGMII; break; default: break; } return PHY_INTERFACE_MODE_NONE; }
phy_interface_t fman_port_enet_if(enum fm_port port) { ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]); if (is_device_disabled(port)) return PHY_INTERFACE_MODE_NONE; if ((port == FM1_10GEC1 || port == FM1_10GEC2) && ((is_serdes_configured(XAUI_FM1_MAC9)) || (is_serdes_configured(XAUI_FM1_MAC10)) || (is_serdes_configured(XFI_FM1_MAC9)) || (is_serdes_configured(XFI_FM1_MAC10)))) return PHY_INTERFACE_MODE_XGMII; if ((port == FM2_10GEC1 || port == FM2_10GEC2) && ((is_serdes_configured(XAUI_FM2_MAC9)) || (is_serdes_configured(XAUI_FM2_MAC10)) || (is_serdes_configured(XFI_FM2_MAC9)) || (is_serdes_configured(XFI_FM2_MAC10)))) return PHY_INTERFACE_MODE_XGMII; #define FSL_CORENET_RCWSR13_EC1 0x60000000 /* bits 417..418 */ #define FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC1_FM2_GPIO 0x40000000 #define FSL_CORENET_RCWSR13_EC2 0x18000000 /* bits 419..420 */ #define FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII 0x00000000 #define FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII 0x08000000 #define FSL_CORENET_RCWSR13_EC2_FM1_GPIO 0x10000000 /* handle RGMII first */ if ((port == FM2_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC1) == FSL_CORENET_RCWSR13_EC1_FM2_DTSEC5_RGMII)) return PHY_INTERFACE_MODE_RGMII; if ((port == FM1_DTSEC5) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == FSL_CORENET_RCWSR13_EC2_FM1_DTSEC5_RGMII)) return PHY_INTERFACE_MODE_RGMII; if ((port == FM2_DTSEC6) && ((rcwsr13 & FSL_CORENET_RCWSR13_EC2) == FSL_CORENET_RCWSR13_EC2_FM2_DTSEC6_RGMII)) return PHY_INTERFACE_MODE_RGMII; switch (port) { case FM1_DTSEC1: case FM1_DTSEC2: case FM1_DTSEC3: case FM1_DTSEC4: case FM1_DTSEC5: case FM1_DTSEC6: case FM1_DTSEC9: case FM1_DTSEC10: if (is_serdes_configured(SGMII_FM1_DTSEC1 + port - FM1_DTSEC1)) return PHY_INTERFACE_MODE_SGMII; break; case FM2_DTSEC1: case FM2_DTSEC2: case FM2_DTSEC3: case FM2_DTSEC4: case FM2_DTSEC5: case FM2_DTSEC6: case FM2_DTSEC9: case FM2_DTSEC10: if (is_serdes_configured(SGMII_FM2_DTSEC1 + port - FM2_DTSEC1)) return PHY_INTERFACE_MODE_SGMII; break; default: return PHY_INTERFACE_MODE_NONE; } return PHY_INTERFACE_MODE_NONE; }
phy_interface_t fman_port_enet_if(enum fm_port port) { struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]); if (is_device_disabled(port)) return PHY_INTERFACE_MODE_NONE; if ((port == FM1_10GEC1) && (is_serdes_configured(XFI_FM1_MAC9))) return PHY_INTERFACE_MODE_XGMII; if ((port == FM1_DTSEC9) && (is_serdes_configured(XFI_FM1_MAC9))) return PHY_INTERFACE_MODE_NONE; if ((port == FM1_10GEC2) && (is_serdes_configured(XFI_FM1_MAC10))) return PHY_INTERFACE_MODE_XGMII; if ((port == FM1_DTSEC10) && (is_serdes_configured(XFI_FM1_MAC10))) return PHY_INTERFACE_MODE_NONE; if (port == FM1_DTSEC3) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC1) == FSL_CHASSIS2_RCWSR13_EC1_DTSEC3_RGMII) return PHY_INTERFACE_MODE_RGMII; if (port == FM1_DTSEC4) if ((rcwsr13 & FSL_CHASSIS2_RCWSR13_EC2) == FSL_CHASSIS2_RCWSR13_EC2_DTSEC4_RGMII) return PHY_INTERFACE_MODE_RGMII; /* handle SGMII, only MAC 2/5/6/9/10 available */ switch (port) { case FM1_DTSEC2: case FM1_DTSEC5: case FM1_DTSEC6: case FM1_DTSEC9: case FM1_DTSEC10: if (is_serdes_configured(SGMII_FM1_DTSEC2 + port - FM1_DTSEC2)) return PHY_INTERFACE_MODE_SGMII; break; default: break; } /* handle 2.5G SGMII, only MAC 5/9/10 available */ switch (port) { case FM1_DTSEC5: case FM1_DTSEC9: case FM1_DTSEC10: if (is_serdes_configured(SGMII_2500_FM1_DTSEC5 + port - FM1_DTSEC5)) return PHY_INTERFACE_MODE_SGMII_2500; break; default: break; } /* handle QSGMII, only MAC 1/5/6/10 available */ switch (port) { case FM1_DTSEC1: case FM1_DTSEC5: case FM1_DTSEC6: case FM1_DTSEC10: if (is_serdes_configured(QSGMII_FM1_A)) return PHY_INTERFACE_MODE_QSGMII; break; default: break; } return PHY_INTERFACE_MODE_NONE; }
void pci_init_board(void) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); struct fsl_pci_info pci_info[4]; u32 devdisr, pordevsr, io_sel, sdrs2_io_sel; u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel; int first_free_busno = 0; int num = 0; int pcie_ep, pcie_configured; devdisr = in_be32(&gur->devdisr); pordevsr = in_be32(&gur->pordevsr); porpllsr = in_be32(&gur->porpllsr); io_sel = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; sdrs2_io_sel = (pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27; debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x\n", devdisr, sdrs2_io_sel, io_sel); if (sdrs2_io_sel == 7) printf("Serdes2 disalbed\n"); else if (sdrs2_io_sel == 4) { printf("eTSEC1 is in sgmii mode.\n"); printf("eTSEC3 is in sgmii mode.\n"); } else if (sdrs2_io_sel == 6) printf("eTSEC1 is in sgmii mode.\n"); puts("\n"); #ifdef CONFIG_PCIE3 pcie_configured = is_serdes_configured(PCIE3); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE3)){ set_next_law(CONFIG_SYS_PCIE3_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_3); set_next_law(CONFIG_SYS_PCIE3_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_3); SET_STD_PCIE_INFO(pci_info[num], 3); pcie_ep = fsl_setup_hose(&pcie3_hose, pci_info[num].regs); printf("PCIE3: connected to Slot3 as %s (base address %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie3_hose, first_free_busno); } else { printf("PCIE3: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE3); /* disable */ #endif #ifdef CONFIG_PCIE1 pcie_configured = is_serdes_configured(PCIE1); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){ set_next_law(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_1); set_next_law(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_1); SET_STD_PCIE_INFO(pci_info[num], 1); pcie_ep = fsl_setup_hose(&pcie1_hose, pci_info[num].regs); printf("PCIE1: connected to Slot1 as %s (base address %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie1_hose, first_free_busno); } else { printf("PCIE1: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE); /* disable */ #endif #ifdef CONFIG_PCIE2 pcie_configured = is_serdes_configured(PCIE2); if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE2)){ set_next_law(CONFIG_SYS_PCIE2_MEM_PHYS, LAW_SIZE_128M, LAW_TRGT_IF_PCIE_2); set_next_law(CONFIG_SYS_PCIE2_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCIE_2); SET_STD_PCIE_INFO(pci_info[num], 2); pcie_ep = fsl_setup_hose(&pcie2_hose, pci_info[num].regs); printf("PCIE2: connected to Slot 2 as %s (base address %lx)\n", pcie_ep ? "Endpoint" : "Root Complex", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pcie2_hose, first_free_busno); } else { printf("PCIE2: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCIE2); /* disable */ #endif #ifdef CONFIG_PCI1 pci_speed = 66666000; pci_32 = 1; pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; if (!(devdisr & MPC85xx_DEVDISR_PCI1)) { set_next_law(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_256M, LAW_TRGT_IF_PCI); set_next_law(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_PCI); SET_STD_PCI_INFO(pci_info[num], 1); pci_agent = fsl_setup_hose(&pci1_hose, pci_info[num].regs); printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter", pci_info[num].regs); first_free_busno = fsl_pci_init_port(&pci_info[num++], &pci1_hose, first_free_busno); } else { printf("PCI: disabled\n"); } puts("\n"); #else setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */ #endif }
int init_sata(int dev) { u32 length, align; cmd_hdr_tbl_t *cmd_hdr; u32 cda; u32 val32; fsl_sata_reg_t *reg; u32 sig; int i; fsl_sata_t *sata; if (dev < 0 || dev > (CONFIG_SYS_SATA_MAX_DEVICE - 1)) { printf("the sata index %d is out of ranges\n\r", dev); return -1; } #ifdef CONFIG_MPC85xx if ((dev == 0) && (!is_serdes_configured(SATA1))) { printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); return -1; } if ((dev == 1) && (!is_serdes_configured(SATA2))) { printf("SATA%d [dev = %d] is not enabled\n", dev+1, dev); return -1; } #endif /* Allocate SATA device driver struct */ sata = (fsl_sata_t *)malloc(sizeof(fsl_sata_t)); if (!sata) { printf("alloc the sata device struct failed\n\r"); return -1; } /* Zero all of the device driver struct */ memset((void *)sata, 0, sizeof(fsl_sata_t)); /* Save the private struct to block device struct */ sata_dev_desc[dev].priv = (void *)sata; sprintf(sata->name, "SATA%d", dev); /* Set the controller register base address to device struct */ reg = (fsl_sata_reg_t *)(fsl_sata_info[dev].sata_reg_base); sata->reg_base = reg; /* Allocate the command header table, 4 bytes aligned */ length = sizeof(struct cmd_hdr_tbl); align = SATA_HC_CMD_HDR_TBL_ALIGN; sata->cmd_hdr_tbl_offset = (void *)malloc(length + align); if (!sata) { printf("alloc the command header failed\n\r"); return -1; } cmd_hdr = (cmd_hdr_tbl_t *)(((u32)sata->cmd_hdr_tbl_offset + align) & ~(align - 1)); sata->cmd_hdr = cmd_hdr; /* Zero all of the command header table */ memset((void *)sata->cmd_hdr_tbl_offset, 0, length + align); /* Allocate command descriptor for all command */ length = sizeof(struct cmd_desc) * SATA_HC_MAX_CMD; align = SATA_HC_CMD_DESC_ALIGN; sata->cmd_desc_offset = (void *)malloc(length + align); if (!sata->cmd_desc_offset) { printf("alloc the command descriptor failed\n\r"); return -1; } sata->cmd_desc = (cmd_desc_t *)(((u32)sata->cmd_desc_offset + align) & ~(align - 1)); /* Zero all of command descriptor */ memset((void *)sata->cmd_desc_offset, 0, length + align); /* Link the command descriptor to command header */ for (i = 0; i < SATA_HC_MAX_CMD; i++) { cda = ((u32)sata->cmd_desc + SATA_HC_CMD_DESC_SIZE * i) & ~(CMD_HDR_CDA_ALIGN - 1); cmd_hdr->cmd_slot[i].cda = cpu_to_le32(cda); } /* To have safe state, force the controller offline */ val32 = in_le32(®->hcontrol); val32 &= ~HCONTROL_ONOFF; val32 |= HCONTROL_FORCE_OFFLINE; out_le32(®->hcontrol, val32); /* Wait the controller offline */ ata_wait_register(®->hstatus, HSTATUS_ONOFF, 0, 1000); #if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001) /* * For P1022/1013 Rev1.0 silicon, after power on SATA host * controller is configured in legacy mode instead of the * expected enterprise mode. software needs to clear bit[28] * of HControl register to change to enterprise mode from * legacy mode. */ { u32 svr = get_svr(); if (IS_SVR_REV(svr, 1, 0) && ((SVR_SOC_VER(svr) == SVR_P1022) || (SVR_SOC_VER(svr) == SVR_P1022_E) || (SVR_SOC_VER(svr) == SVR_P1013) || (SVR_SOC_VER(svr) == SVR_P1013_E))) { out_le32(®->hstatus, 0x20000000); out_le32(®->hcontrol, 0x00000100); } } #endif /* Set the command header base address to CHBA register to tell DMA */ out_le32(®->chba, (u32)cmd_hdr & ~0x3); /* Snoop for the command header */ val32 = in_le32(®->hcontrol); val32 |= HCONTROL_HDR_SNOOP; out_le32(®->hcontrol, val32); /* Disable all of interrupts */ val32 = in_le32(®->hcontrol); val32 &= ~HCONTROL_INT_EN_ALL; out_le32(®->hcontrol, val32); /* Clear all of interrupts */ val32 = in_le32(®->hstatus); out_le32(®->hstatus, val32); /* Set the ICC, no interrupt coalescing */ out_le32(®->icc, 0x01000000); /* No PM attatched, the SATA device direct connect */ out_le32(®->cqpmp, 0); /* Clear SError register */ val32 = in_le32(®->serror); out_le32(®->serror, val32); /* Clear CER register */ val32 = in_le32(®->cer); out_le32(®->cer, val32); /* Clear DER register */ val32 = in_le32(®->der); out_le32(®->der, val32); /* No device detection or initialization action requested */ out_le32(®->scontrol, 0x00000300); /* Configure the transport layer, default value */ out_le32(®->transcfg, 0x08000016); /* Configure the link layer, default value */ out_le32(®->linkcfg, 0x0000ff34); /* Bring the controller online */ val32 = in_le32(®->hcontrol); val32 |= HCONTROL_ONOFF; out_le32(®->hcontrol, val32); mdelay(100); /* print sata device name */ if (!dev) printf("%s ", sata->name); else printf(" %s ", sata->name); /* Wait PHY RDY signal changed for 500ms */ ata_wait_register(®->hstatus, HSTATUS_PHY_RDY, HSTATUS_PHY_RDY, 500); /* Check PHYRDY */ val32 = in_le32(®->hstatus); if (val32 & HSTATUS_PHY_RDY) { sata->link = 1; } else { sata->link = 0; printf("(No RDY)\n\r"); return -1; } /* Wait for signature updated, which is 1st D2H */ ata_wait_register(®->hstatus, HSTATUS_SIGNATURE, HSTATUS_SIGNATURE, 10000); if (val32 & HSTATUS_SIGNATURE) { sig = in_le32(®->sig); debug("Signature updated, the sig =%08x\n\r", sig); sata->ata_device_type = ata_dev_classify(sig); } /* Check the speed */ val32 = in_le32(®->sstatus); if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN1) printf("(1.5 Gbps)\n\r"); else if ((val32 & SSTATUS_SPD_MASK) == SSTATUS_SPD_GEN2) printf("(3 Gbps)\n\r"); return 0; }
int board_eth_init(bd_t *bis) { struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; ccsr_gur_t *gur __attribute__((unused)) = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); int num = 0; #ifdef CONFIG_VSC7385_ENET char *tmp; unsigned int vscfw_addr; #endif #ifdef CONFIG_TSEC1 SET_STD_TSEC_INFO(tsec_info[num], 1); num++; #endif #ifdef CONFIG_TSEC2 SET_STD_TSEC_INFO(tsec_info[num], 2); if (is_serdes_configured(SGMII_TSEC2)) { printf("eTSEC2 is in sgmii mode.\n"); tsec_info[num].flags |= TSEC_SGMII; } num++; #endif #ifdef CONFIG_TSEC3 SET_STD_TSEC_INFO(tsec_info[num], 3); num++; #endif if (!num) { printf("No TSECs initialized\n"); return 0; } #ifdef CONFIG_VSC7385_ENET /* If a VSC7385 microcode image is present, then upload it. */ tmp = env_get("vscfw_addr"); if (tmp) { vscfw_addr = simple_strtoul(tmp, NULL, 16); printf("uploading VSC7385 microcode from %x\n", vscfw_addr); if (vsc7385_upload_firmware((void *) vscfw_addr, CONFIG_VSC7385_IMAGE_SIZE)) puts("Failure uploading VSC7385 microcode.\n"); } else puts("No address specified for VSC7385 microcode.\n"); #endif mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1); mdio_info.name = DEFAULT_MII_NAME; fsl_pq_mdio_init(bis, &mdio_info); tsec_eth_init(bis, tsec_info, num); #if defined(CONFIG_UEC_ETH) /* QE0 and QE3 need to be exposed for UCC1 and UCC5 Eth mode */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE0); setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE3); uec_standard_init(bis); #endif return pci_eth_init(bis); }