static int str9xpec_blank_check(struct flash_bank *bank, int first, int last) { struct scan_field field; uint8_t status; struct jtag_tap *tap; int i; uint8_t *buffer = NULL; struct str9xpec_flash_controller *str9xpec_info = bank->driver_priv; tap = str9xpec_info->tap; if (!str9xpec_info->isc_enable) str9xpec_isc_enable(bank); if (!str9xpec_info->isc_enable) return ERROR_FLASH_OPERATION_FAILED; buffer = calloc(DIV_ROUND_UP(64, 8), 1); LOG_DEBUG("blank check: first_bank: %i, last_bank: %i", first, last); for (i = first; i <= last; i++) buf_set_u32(buffer, str9xpec_info->sector_bits[i], 1, 1); /* execute ISC_BLANK_CHECK command */ str9xpec_set_instr(tap, ISC_BLANK_CHECK, TAP_IRPAUSE); field.num_bits = 64; field.out_value = buffer; field.in_value = NULL; jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); jtag_add_sleep(40000); /* read blank check result */ field.num_bits = 64; field.out_value = NULL; field.in_value = buffer; jtag_add_dr_scan(tap, 1, &field, TAP_IRPAUSE); jtag_execute_queue(); status = str9xpec_isc_status(tap); for (i = first; i <= last; i++) { if (buf_get_u32(buffer, str9xpec_info->sector_bits[i], 1)) bank->sectors[i].is_erased = 0; else bank->sectors[i].is_erased = 1; } free(buffer); str9xpec_isc_disable(bank); if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) return ERROR_FLASH_OPERATION_FAILED; return ERROR_OK; }
/* read reg from lakemont core shadow ram, update reg cache if needed */ static int read_hw_reg(struct target *t, int reg, uint32_t *regval, uint8_t cache) { struct x86_32_common *x86_32 = target_to_x86_32(t); struct lakemont_core_reg *arch_info; arch_info = x86_32->cache->reg_list[reg].arch_info; x86_32->flush = 0; /* dont flush scans till we have a batch */ if (submit_reg_pir(t, reg) != ERROR_OK) return ERROR_FAIL; if (submit_instruction_pir(t, SRAMACCESS) != ERROR_OK) return ERROR_FAIL; if (submit_instruction_pir(t, SRAM2PDR) != ERROR_OK) return ERROR_FAIL; x86_32->flush = 1; scan.out[0] = RDWRPDR; if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK) return ERROR_FAIL; if (drscan(t, NULL, scan.out, PDR_SIZE) != ERROR_OK) return ERROR_FAIL; jtag_add_sleep(DELAY_SUBMITPIR); *regval = buf_get_u32(scan.out, 0, 32); if (cache) { buf_set_u32(x86_32->cache->reg_list[reg].value, 0, 32, *regval); x86_32->cache->reg_list[reg].valid = 1; x86_32->cache->reg_list[reg].dirty = 0; } LOG_DEBUG("reg=%s, op=0x%016" PRIx64 ", val=0x%08" PRIx32, x86_32->cache->reg_list[reg].name, arch_info->op, *regval); return ERROR_OK; }
static int str9xpec_isc_disable(struct flash_bank *bank) { uint8_t status; struct jtag_tap *tap; struct str9xpec_flash_controller *str9xpec_info = bank->driver_priv; tap = str9xpec_info->tap; if (!str9xpec_info->isc_enable) return ERROR_OK; if (str9xpec_set_instr(tap, ISC_DISABLE, TAP_IDLE) != ERROR_OK) return ERROR_TARGET_INVALID; /* delay to handle aborts */ jtag_add_sleep(50); /* check ISC status */ status = str9xpec_isc_status(tap); if (!(status & ISC_STATUS_MODE)) { /* we have left isc mode */ str9xpec_info->isc_enable = 0; LOG_DEBUG("ISC_MODE Disabled"); } return ERROR_OK; }
static int str9xpec_erase_area(struct flash_bank *bank, int first, int last) { struct scan_field field; uint8_t status; struct jtag_tap *tap; int i; uint8_t *buffer = NULL; struct str9xpec_flash_controller *str9xpec_info = bank->driver_priv; tap = str9xpec_info->tap; if (!str9xpec_info->isc_enable) str9xpec_isc_enable(bank); if (!str9xpec_info->isc_enable) return ISC_STATUS_ERROR; buffer = calloc(DIV_ROUND_UP(64, 8), 1); LOG_DEBUG("erase: first_bank: %i, last_bank: %i", first, last); /* last bank: 0xFF signals a full erase (unlock complete device) */ /* last bank: 0xFE signals a option byte erase */ if (last == 0xFF) { for (i = 0; i < 64; i++) buf_set_u32(buffer, i, 1, 1); } else if (last == 0xFE) buf_set_u32(buffer, 49, 1, 1); else { for (i = first; i <= last; i++) buf_set_u32(buffer, str9xpec_info->sector_bits[i], 1, 1); } LOG_DEBUG("ISC_ERASE"); /* execute ISC_ERASE command */ str9xpec_set_instr(tap, ISC_ERASE, TAP_IRPAUSE); field.num_bits = 64; field.out_value = buffer; field.in_value = NULL; jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); jtag_execute_queue(); jtag_add_sleep(10); /* wait for erase completion */ while (!((status = str9xpec_isc_status(tap)) & ISC_STATUS_BUSY)) alive_sleep(1); free(buffer); str9xpec_isc_disable(bank); return status; }
int arc_ocd_assert_reset(struct target *target) { struct arc32_common *arc32 = target_to_arc32(target); LOG_DEBUG("target->state: %s", target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { /* allow scripts to override the reset event */ target_handle_event(target, TARGET_EVENT_RESET_ASSERT); register_cache_invalidate(arc32->core_cache); /* An ARC target might be in halt state after reset, so * if script requested processor to resume, then it must * be manually started to ensure that this request * is satisfied. */ if (target->state == TARGET_HALTED && !target->reset_halt) { /* Resume the target and continue from the current * PC register value. */ LOG_DEBUG("Starting CPU execution after reset"); CHECK_RETVAL(target_resume(target, 1, 0, 0, 0)); } target->state = TARGET_RESET; return ERROR_OK; } /* some cores support connecting while srst is asserted * use that mode is it has been configured */ bool srst_asserted = false; if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_reset_config & RESET_SRST_NO_GATING)) { jtag_add_reset(0, 1); srst_asserted = true; } if (jtag_reset_config & RESET_HAS_SRST) { /* should issue a srst only, but we may have to assert trst as well */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) jtag_add_reset(1, 1); else if (!srst_asserted) jtag_add_reset(0, 1); } target->state = TARGET_RESET; jtag_add_sleep(50000); register_cache_invalidate(arc32->core_cache); if (target->reset_halt) CHECK_RETVAL(target_halt(target)); return ERROR_OK; }
static int str9xpec_write_options(struct flash_bank *bank) { struct scan_field field; uint8_t status; struct jtag_tap *tap; struct str9xpec_flash_controller *str9xpec_info = NULL; str9xpec_info = bank->driver_priv; tap = str9xpec_info->tap; /* erase config options first */ status = str9xpec_erase_area(bank, 0xFE, 0xFE); if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) return status; if (!str9xpec_info->isc_enable) str9xpec_isc_enable(bank); if (!str9xpec_info->isc_enable) return ISC_STATUS_ERROR; /* according to data 64th bit has to be set */ buf_set_u32(str9xpec_info->options, 63, 1, 1); /* set option byte address */ str9xpec_set_address(bank, 0x50); /* execute ISC_PROGRAM command */ str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE); field.num_bits = 64; field.out_value = str9xpec_info->options; field.in_value = NULL; jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); /* small delay before polling */ jtag_add_sleep(50); str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE); do { field.num_bits = 8; field.out_value = NULL; field.in_value = &status; jtag_add_dr_scan(tap, 1, &field, TAP_IRPAUSE); jtag_execute_queue(); } while (!(status & ISC_STATUS_BUSY)); str9xpec_isc_disable(bank); return status; }
int arc_ocd_assert_reset(struct target *target) { struct arc32_common *arc32 = target_to_arc32(target); LOG_DEBUG("target->state: %s", target_state_name(target)); enum reset_types jtag_reset_config = jtag_get_reset_config(); if (target_has_event_action(target, TARGET_EVENT_RESET_ASSERT)) { /* allow scripts to override the reset event */ target_handle_event(target, TARGET_EVENT_RESET_ASSERT); register_cache_invalidate(arc32->core_cache); target->state = TARGET_RESET; return ERROR_OK; } /* some cores support connecting while srst is asserted * use that mode is it has been configured */ bool srst_asserted = false; if (!(jtag_reset_config & RESET_SRST_PULLS_TRST) && (jtag_reset_config & RESET_SRST_NO_GATING)) { jtag_add_reset(0, 1); srst_asserted = true; } if (jtag_reset_config & RESET_HAS_SRST) { /* should issue a srst only, but we may have to assert trst as well */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) jtag_add_reset(1, 1); else if (!srst_asserted) jtag_add_reset(0, 1); } target->state = TARGET_RESET; jtag_add_sleep(50000); register_cache_invalidate(arc32->core_cache); if (target->reset_halt) CHECK_RETVAL(target_halt(target)); return ERROR_OK; }
static int virtex2_load(struct pld_device *pld_device, const char *filename) { struct virtex2_pld_device *virtex2_info = pld_device->driver_priv; struct xilinx_bit_file bit_file; int retval; unsigned int i; struct scan_field field; field.tap = virtex2_info->tap; field.in_value = NULL; if ((retval = xilinx_read_bit_file(&bit_file, filename)) != ERROR_OK) return retval; jtag_set_end_state(TAP_IDLE); virtex2_set_instr(virtex2_info->tap, 0xb); /* JPROG_B */ jtag_execute_queue(); jtag_add_sleep(1000); virtex2_set_instr(virtex2_info->tap, 0x5); /* CFG_IN */ jtag_execute_queue(); for (i = 0; i < bit_file.length; i++) bit_file.data[i] = flip_u32(bit_file.data[i], 8); field.num_bits = bit_file.length * 8; field.out_value = bit_file.data; jtag_add_dr_scan(1, &field, jtag_set_end_state(TAP_DRPAUSE)); jtag_execute_queue(); jtag_add_tlr(); jtag_set_end_state(TAP_IDLE); virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */ jtag_add_runtest(13, jtag_set_end_state(TAP_IDLE)); virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */ virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */ virtex2_set_instr(virtex2_info->tap, 0xc); /* JSTART */ jtag_add_runtest(13, jtag_set_end_state(TAP_IDLE)); virtex2_set_instr(virtex2_info->tap, 0x3f); /* BYPASS */ jtag_execute_queue(); return ERROR_OK; }
/* * PIR (Probe Mode Instruction Register), SUBMITPIR is an "IR only" TAP * command; there is no corresponding data register */ static int submit_pir(struct target *t, uint64_t op) { struct x86_32_common *x86_32 = target_to_x86_32(t); uint32_t tapstatus = 0; uint8_t op_buf[8]; buf_set_u64(op_buf, 0, 64, op); int flush = x86_32->flush; x86_32->flush = 0; scan.out[0] = WRPIR; if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK) return ERROR_FAIL; if (drscan(t, op_buf, scan.out, PIR_SIZE) != ERROR_OK) return ERROR_FAIL; scan.out[0] = SUBMITPIR; x86_32->flush = flush; if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK) return ERROR_FAIL; jtag_add_sleep(DELAY_SUBMITPIR); /* HACK */ if (x86_32->flush) { int cnt = 10; do { tapstatus = get_tapstatus(t); if (!(tapstatus & TS_PIR_BIT)) return ERROR_OK; LOG_DEBUG("%s Waiting for TS_PIR_BIT, TS = 0x%08" PRIx32, __func__, tapstatus); usleep(100); cnt--; } while (cnt); LOG_ERROR("%s TS_PIR_BIT did not clear, TS = 0x%08" PRIx32, __func__, tapstatus); return ERROR_FAIL; /* TODO: find a nicer way to wait until PM_BIT changes*/ } return ERROR_OK; }
/* * PIR (Probe Mode Instruction Register), SUBMITPIR is an "IR only" TAP * command; there is no corresponding data register */ static int submit_pir(struct target *t, uint64_t op) { struct x86_32_common *x86_32 = target_to_x86_32(t); uint8_t op_buf[8]; buf_set_u64(op_buf, 0, 64, op); int flush = x86_32->flush; x86_32->flush = 0; scan.out[0] = WRPIR; if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK) return ERROR_FAIL; if (drscan(t, op_buf, scan.out, PIR_SIZE) != ERROR_OK) return ERROR_FAIL; scan.out[0] = SUBMITPIR; x86_32->flush = flush; if (irscan(t, scan.out, NULL, LMT_IRLEN) != ERROR_OK) return ERROR_FAIL; jtag_add_sleep(DELAY_SUBMITPIR); return ERROR_OK; }
static int xtensa_assert_reset(struct target *target) { struct xtensa_common *xtensa = target_to_xtensa(target); enum reset_types jtag_reset_config = jtag_get_reset_config(); if (jtag_reset_config & RESET_HAS_SRST) { /* default to asserting srst */ if (jtag_reset_config & RESET_SRST_PULLS_TRST) jtag_add_reset(1, 1); else jtag_add_reset(0, 1); } target->state = TARGET_RESET; jtag_add_sleep(5000); register_cache_invalidate(xtensa->core_cache); LOG_DEBUG("%s", __func__); return ERROR_OK; }
int mips_ejtag_exit_debug(struct mips_ejtag *ejtag_info) { uint32_t pracc_list[] = {MIPS32_DRET, 0}; struct pracc_queue_info ctx = {.max_code = 1, .pracc_list = pracc_list, .code_count = 1, .store_count = 0}; /* execute our dret instruction */ ctx.retval = mips32_pracc_queue_exec(ejtag_info, &ctx, NULL); /* pic32mx/mz workaround, false pending at low core clock */ jtag_add_sleep(1000); return ctx.retval; } /* mips_ejtag_init_mmr - asign Memory-Mapped Registers depending * on EJTAG version. */ static void mips_ejtag_init_mmr(struct mips_ejtag *ejtag_info) { if (ejtag_info->ejtag_version == EJTAG_VERSION_20) { ejtag_info->ejtag_ibs_addr = EJTAG_V20_IBS; ejtag_info->ejtag_iba0_addr = EJTAG_V20_IBA0; ejtag_info->ejtag_ibc_offs = EJTAG_V20_IBC_OFFS; ejtag_info->ejtag_ibm_offs = EJTAG_V20_IBM_OFFS; ejtag_info->ejtag_dbs_addr = EJTAG_V20_DBS; ejtag_info->ejtag_dba0_addr = EJTAG_V20_DBA0; ejtag_info->ejtag_dbc_offs = EJTAG_V20_DBC_OFFS; ejtag_info->ejtag_dbm_offs = EJTAG_V20_DBM_OFFS; ejtag_info->ejtag_dbv_offs = EJTAG_V20_DBV_OFFS; ejtag_info->ejtag_iba_step_size = EJTAG_V20_IBAn_STEP; ejtag_info->ejtag_dba_step_size = EJTAG_V20_DBAn_STEP; } else { ejtag_info->ejtag_ibs_addr = EJTAG_V25_IBS; ejtag_info->ejtag_iba0_addr = EJTAG_V25_IBA0; ejtag_info->ejtag_ibm_offs = EJTAG_V25_IBM_OFFS; ejtag_info->ejtag_ibasid_offs = EJTAG_V25_IBASID_OFFS; ejtag_info->ejtag_ibc_offs = EJTAG_V25_IBC_OFFS; ejtag_info->ejtag_dbs_addr = EJTAG_V25_DBS; ejtag_info->ejtag_dba0_addr = EJTAG_V25_DBA0; ejtag_info->ejtag_dbm_offs = EJTAG_V25_DBM_OFFS; ejtag_info->ejtag_dbasid_offs = EJTAG_V25_DBASID_OFFS; ejtag_info->ejtag_dbc_offs = EJTAG_V25_DBC_OFFS; ejtag_info->ejtag_dbv_offs = EJTAG_V25_DBV_OFFS; ejtag_info->ejtag_iba_step_size = EJTAG_V25_IBAn_STEP; ejtag_info->ejtag_dba_step_size = EJTAG_V25_DBAn_STEP; } } static void ejtag_v20_print_imp(struct mips_ejtag *ejtag_info) { LOG_DEBUG("EJTAG v2.0: features:%s%s%s%s%s%s%s%s", EJTAG_IMP_HAS(EJTAG_V20_IMP_SDBBP) ? " SDBBP_SPECIAL2" : " SDBBP", EJTAG_IMP_HAS(EJTAG_V20_IMP_EADDR_NO32BIT) ? " EADDR>32bit" : " EADDR=32bit", EJTAG_IMP_HAS(EJTAG_V20_IMP_COMPLEX_BREAK) ? " COMPLEX_BREAK" : "", EJTAG_IMP_HAS(EJTAG_V20_IMP_DCACHE_COH) ? " DCACHE_COH" : " DCACHE_NOT_COH", EJTAG_IMP_HAS(EJTAG_V20_IMP_ICACHE_COH) ? " ICACHE_COH" : " ICACHE_NOT_COH", EJTAG_IMP_HAS(EJTAG_V20_IMP_NOPB) ? " noPB" : " PB", EJTAG_IMP_HAS(EJTAG_V20_IMP_NODB) ? " noDB" : " DB", EJTAG_IMP_HAS(EJTAG_V20_IMP_NOIB) ? " noIB" : " IB"); LOG_DEBUG("EJTAG v2.0: Break Channels: %i", (ejtag_info->impcode >> EJTAG_V20_IMP_BCHANNELS_SHIFT) & EJTAG_V20_IMP_BCHANNELS_MASK); }
static int str9xpec_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count) { struct str9xpec_flash_controller *str9xpec_info = bank->driver_priv; uint32_t dwords_remaining = (count / 8); uint32_t bytes_remaining = (count & 0x00000007); uint32_t bytes_written = 0; uint8_t status; uint32_t check_address = offset; struct jtag_tap *tap; struct scan_field field; uint8_t *scanbuf; int i; int first_sector = 0; int last_sector = 0; tap = str9xpec_info->tap; if (!str9xpec_info->isc_enable) str9xpec_isc_enable(bank); if (!str9xpec_info->isc_enable) return ERROR_FLASH_OPERATION_FAILED; if (offset & 0x7) { LOG_WARNING("offset 0x%" PRIx32 " breaks required 8-byte alignment", offset); return ERROR_FLASH_DST_BREAKS_ALIGNMENT; } for (i = 0; i < bank->num_sectors; i++) { uint32_t sec_start = bank->sectors[i].offset; uint32_t sec_end = sec_start + bank->sectors[i].size; /* check if destination falls within the current sector */ if ((check_address >= sec_start) && (check_address < sec_end)) { /* check if destination ends in the current sector */ if (offset + count < sec_end) check_address = offset + count; else check_address = sec_end; } if ((offset >= sec_start) && (offset < sec_end)) first_sector = i; if ((offset + count >= sec_start) && (offset + count < sec_end)) last_sector = i; } if (check_address != offset + count) return ERROR_FLASH_DST_OUT_OF_BANK; LOG_DEBUG("first_sector: %i, last_sector: %i", first_sector, last_sector); scanbuf = calloc(DIV_ROUND_UP(64, 8), 1); LOG_DEBUG("ISC_PROGRAM"); for (i = first_sector; i <= last_sector; i++) { str9xpec_set_address(bank, str9xpec_info->sector_bits[i]); dwords_remaining = dwords_remaining < (bank->sectors[i].size/8) ? dwords_remaining : (bank->sectors[i].size/8); while (dwords_remaining > 0) { str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE); field.num_bits = 64; field.out_value = (buffer + bytes_written); field.in_value = NULL; jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); /* small delay before polling */ jtag_add_sleep(50); str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE); do { field.num_bits = 8; field.out_value = NULL; field.in_value = scanbuf; jtag_add_dr_scan(tap, 1, &field, TAP_IRPAUSE); jtag_execute_queue(); status = buf_get_u32(scanbuf, 0, 8); } while (!(status & ISC_STATUS_BUSY)); if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) return ERROR_FLASH_OPERATION_FAILED; /* if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL) return ERROR_FLASH_OPERATION_FAILED; */ dwords_remaining--; bytes_written += 8; } } if (bytes_remaining) { uint8_t last_dword[8] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; /* copy the last remaining bytes into the write buffer */ memcpy(last_dword, buffer+bytes_written, bytes_remaining); str9xpec_set_instr(tap, ISC_PROGRAM, TAP_IRPAUSE); field.num_bits = 64; field.out_value = last_dword; field.in_value = NULL; jtag_add_dr_scan(tap, 1, &field, TAP_IDLE); /* small delay before polling */ jtag_add_sleep(50); str9xpec_set_instr(tap, ISC_NOOP, TAP_IRPAUSE); do { field.num_bits = 8; field.out_value = NULL; field.in_value = scanbuf; jtag_add_dr_scan(tap, 1, &field, TAP_IRPAUSE); jtag_execute_queue(); status = buf_get_u32(scanbuf, 0, 8); } while (!(status & ISC_STATUS_BUSY)); if ((status & ISC_STATUS_ERROR) != STR9XPEC_ISC_SUCCESS) return ERROR_FLASH_OPERATION_FAILED; /* if ((status & ISC_STATUS_INT_ERROR) != STR9XPEC_ISC_INTFAIL) return ERROR_FLASH_OPERATION_FAILED; */ } free(scanbuf); str9xpec_isc_disable(bank); return ERROR_OK; }
static int handle_xsvf_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc) { u8 *dr_out_buf = NULL; /* from host to device (TDI) */ u8 *dr_in_buf = NULL; /* from device to host (TDO) */ u8 *dr_in_mask = NULL; int xsdrsize = 0; int xruntest = 0; /* number of TCK cycles OR microseconds */ int xrepeat = 0; /* number of retries */ tap_state_t xendir = TAP_IDLE; /* see page 8 of the SVF spec, initial xendir to be TAP_IDLE */ tap_state_t xenddr = TAP_IDLE; u8 opcode; u8 uc; long file_offset = 0; int loop_count = 0; tap_state_t loop_state = TAP_IDLE; int loop_clocks = 0; int loop_usecs = 0; int do_abort = 0; int unsupported = 0; int tdo_mismatch = 0; int result; int verbose = 1; char* filename; int runtest_requires_tck = 0; /* a flag telling whether to clock TCK during waits, or simply sleep, controled by virt2 */ /* use NULL to indicate a "plain" xsvf file which accounts for additional devices in the scan chain, otherwise the device that should be affected */ jtag_tap_t *tap = NULL; if (argc < 2) { command_print(cmd_ctx, "usage: xsvf <device#|plain> <file> [<variant>] [quiet]"); return ERROR_FAIL; } filename = args[1]; /* we mess with args starting point below, snapshot filename here */ if (strcmp(args[0], "plain") != 0) { tap = jtag_TapByString( args[0] ); if (!tap ) { command_print( cmd_ctx, "Tap: %s unknown", args[0] ); return ERROR_FAIL; } } if ((xsvf_fd = open(filename, O_RDONLY)) < 0) { command_print(cmd_ctx, "file \"%s\" not found", filename); return ERROR_FAIL; } /* if this argument is present, then interpret xruntest counts as TCK cycles rather than as usecs */ if ((argc > 2) && (strcmp(args[2], "virt2") == 0)) { runtest_requires_tck = 1; --argc; ++args; } if ((argc > 2) && (strcmp(args[2], "quiet") == 0)) { verbose = 0; } LOG_USER("xsvf processing file: \"%s\"", filename); while( read(xsvf_fd, &opcode, 1) > 0 ) { /* record the position of the just read opcode within the file */ file_offset = lseek(xsvf_fd, 0, SEEK_CUR) - 1; switch (opcode) { case XCOMPLETE: LOG_DEBUG("XCOMPLETE"); result = jtag_execute_queue(); if (result != ERROR_OK) { tdo_mismatch = 1; break; } break; case XTDOMASK: LOG_DEBUG("XTDOMASK"); if (dr_in_mask && (xsvf_read_buffer(xsdrsize, xsvf_fd, dr_in_mask) != ERROR_OK)) do_abort = 1; break; case XRUNTEST: { u8 xruntest_buf[4]; if (read(xsvf_fd, xruntest_buf, 4) < 0) { do_abort = 1; break; } xruntest = be_to_h_u32(xruntest_buf); LOG_DEBUG("XRUNTEST %d 0x%08X", xruntest, xruntest); } break; case XREPEAT: { u8 myrepeat; if (read(xsvf_fd, &myrepeat, 1) < 0) do_abort = 1; else { xrepeat = myrepeat; LOG_DEBUG("XREPEAT %d", xrepeat ); } } break; case XSDRSIZE: { u8 xsdrsize_buf[4]; if (read(xsvf_fd, xsdrsize_buf, 4) < 0) { do_abort = 1; break; } xsdrsize = be_to_h_u32(xsdrsize_buf); LOG_DEBUG("XSDRSIZE %d", xsdrsize); if( dr_out_buf ) free(dr_out_buf); if( dr_in_buf) free(dr_in_buf); if( dr_in_mask) free(dr_in_mask); dr_out_buf = malloc((xsdrsize + 7) / 8); dr_in_buf = malloc((xsdrsize + 7) / 8); dr_in_mask = malloc((xsdrsize + 7) / 8); } break; case XSDR: /* these two are identical except for the dr_in_buf */ case XSDRTDO: { int limit = xrepeat; int matched = 0; int attempt; const char* op_name = (opcode == XSDR ? "XSDR" : "XSDRTDO"); if (xsvf_read_buffer(xsdrsize, xsvf_fd, dr_out_buf) != ERROR_OK) { do_abort = 1; break; } if (opcode == XSDRTDO) { if(xsvf_read_buffer(xsdrsize, xsvf_fd, dr_in_buf) != ERROR_OK ) { do_abort = 1; break; } } if (limit < 1) limit = 1; LOG_DEBUG("%s %d", op_name, xsdrsize); for( attempt=0; attempt<limit; ++attempt ) { scan_field_t field; if( attempt>0 ) { /* perform the XC9500 exception handling sequence shown in xapp067.pdf and illustrated in psuedo code at end of this file. We start from state DRPAUSE: go to Exit2-DR go to Shift-DR go to Exit1-DR go to Update-DR go to Run-Test/Idle This sequence should be harmless for other devices, and it will be skipped entirely if xrepeat is set to zero. */ static tap_state_t exception_path[] = { TAP_DREXIT2, TAP_DRSHIFT, TAP_DREXIT1, TAP_DRUPDATE, TAP_IDLE, }; jtag_add_pathmove( sizeof(exception_path)/sizeof(exception_path[0]), exception_path); if (verbose) LOG_USER("%s %d retry %d", op_name, xsdrsize, attempt); } field.tap = tap; field.num_bits = xsdrsize; field.out_value = dr_out_buf; field.out_mask = NULL; field.in_value = NULL; jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL); if (tap == NULL) jtag_add_plain_dr_scan(1, &field, TAP_DRPAUSE); else jtag_add_dr_scan(1, &field, TAP_DRPAUSE); /* LOG_DEBUG("FLUSHING QUEUE"); */ result = jtag_execute_queue(); if (result == ERROR_OK) { matched = 1; break; } } if (!matched) { LOG_USER( "%s mismatch", op_name); tdo_mismatch = 1; break; } /* See page 19 of XSVF spec regarding opcode "XSDR" */ if (xruntest) { xsvf_add_statemove(TAP_IDLE); if (runtest_requires_tck) jtag_add_clocks(xruntest); else jtag_add_sleep(xruntest); } else if (xendir != TAP_DRPAUSE) /* we are already in TAP_DRPAUSE */ xsvf_add_statemove(xenddr); } break; case XSETSDRMASKS: LOG_ERROR("unsupported XSETSDRMASKS\n"); unsupported = 1; break; case XSDRINC: LOG_ERROR("unsupported XSDRINC\n"); unsupported = 1; break; case XSDRB: LOG_ERROR("unsupported XSDRB\n"); unsupported = 1; break; case XSDRC: LOG_ERROR("unsupported XSDRC\n"); unsupported = 1; break; case XSDRE: LOG_ERROR("unsupported XSDRE\n"); unsupported = 1; break; case XSDRTDOB: LOG_ERROR("unsupported XSDRTDOB\n"); unsupported = 1; break; case XSDRTDOC: LOG_ERROR("unsupported XSDRTDOC\n"); unsupported = 1; break; case XSDRTDOE: LOG_ERROR("unsupported XSDRTDOE\n"); unsupported = 1; break; case XSTATE: { tap_state_t mystate; tap_state_t *path; int path_len; if (read(xsvf_fd, &uc, 1) < 0) { do_abort = 1; break; } mystate = xsvf_to_tap(uc); LOG_DEBUG("XSTATE 0x%02X %s", uc, tap_state_name(mystate) ); path = calloc(XSTATE_MAX_PATH, 4); path_len = 1; path[0] = mystate; if (xsvf_read_xstates(xsvf_fd, path, XSTATE_MAX_PATH, &path_len) != ERROR_OK) do_abort = 1; else { int i,lasti; /* here the trick is that jtag_add_pathmove() must end in a stable * state, so we must only invoke jtag_add_tlr() when we absolutely * have to */ for(i=0,lasti=0; i<path_len; i++) { if(path[i]==TAP_RESET) { if(i>lasti) { jtag_add_pathmove(i-lasti,path+lasti); } lasti=i+1; jtag_add_tlr(); } } if(i>=lasti) { jtag_add_pathmove(i-lasti, path+lasti); } } free(path); } break; case XENDIR: { tap_state_t mystate; if (read(xsvf_fd, &uc, 1) < 0) { do_abort = 1; break; } /* see page 22 of XSVF spec */ mystate = uc == 1 ? TAP_IRPAUSE : TAP_IDLE; LOG_DEBUG("XENDIR 0x%02X %s", uc, tap_state_name(mystate)); /* assuming that the XRUNTEST comes from SVF RUNTEST, then only these states * should come here because the SVF spec only allows these with a RUNTEST */ if (mystate != TAP_IRPAUSE && mystate != TAP_DRPAUSE && mystate != TAP_RESET && mystate != TAP_IDLE ) { LOG_ERROR("illegal XENDIR endstate: \"%s\"", tap_state_name(mystate)); unsupported = 1; break; } xendir = mystate; } break; case XENDDR: { tap_state_t mystate; if (read(xsvf_fd, &uc, 1) < 0) { do_abort = 1; break; } /* see page 22 of XSVF spec */ mystate = uc == 1 ? TAP_DRPAUSE : TAP_IDLE; LOG_DEBUG("XENDDR %02X %s", uc, tap_state_name(mystate)); if (mystate != TAP_IRPAUSE && mystate != TAP_DRPAUSE && mystate != TAP_RESET && mystate != TAP_IDLE ) { LOG_ERROR("illegal XENDDR endstate: \"%s\"", tap_state_name( mystate )); unsupported = 1; break; } xenddr = mystate; } break; case XSIR: case XSIR2: { u8 short_buf[2]; u8* ir_buf; int bitcount; tap_state_t my_end_state = xruntest ? TAP_IDLE : xendir; if( opcode == XSIR ) { /* one byte bitcount */ if (read(xsvf_fd, short_buf, 1) < 0) { do_abort = 1; break; } bitcount = short_buf[0]; LOG_DEBUG("XSIR %d", bitcount); } else { if (read(xsvf_fd, short_buf, 2) < 0) { do_abort = 1; break; } bitcount = be_to_h_u16(short_buf); LOG_DEBUG("XSIR2 %d", bitcount); } ir_buf = malloc((bitcount+7) / 8); if (xsvf_read_buffer(bitcount, xsvf_fd, ir_buf) != ERROR_OK) do_abort = 1; else { scan_field_t field; field.tap = tap; field.num_bits = bitcount; field.out_value = ir_buf; field.out_mask = NULL; field.in_value = NULL; field.in_check_value = NULL; field.in_check_mask = NULL; field.in_handler = NULL; field.in_handler_priv = NULL; if (tap == NULL) jtag_add_plain_ir_scan(1, &field, my_end_state); else jtag_add_ir_scan(1, &field, my_end_state); if (xruntest) { if (runtest_requires_tck) jtag_add_clocks(xruntest); else jtag_add_sleep(xruntest); } /* Note that an -irmask of non-zero in your config file * can cause this to fail. Setting -irmask to zero cand work * around the problem. */ /* LOG_DEBUG("FLUSHING QUEUE"); */ result = jtag_execute_queue(); if(result != ERROR_OK) { tdo_mismatch = 1; } } free(ir_buf); } break; case XCOMMENT: { int ndx = 0; char comment[128]; do { if (read(xsvf_fd, &uc, 1) < 0) { do_abort = 1; break; } if ( ndx < sizeof(comment)-1 ) comment[ndx++] = uc; } while (uc != 0); comment[sizeof(comment)-1] = 0; /* regardless, terminate */ if (verbose) LOG_USER(comment); } break; case XWAIT: { /* expected in stream: XWAIT <u8 wait_state> <u8 end_state> <u32 usecs> */ u8 wait; u8 end; u8 delay_buf[4]; tap_state_t wait_state; tap_state_t end_state; int delay; if ( read(xsvf_fd, &wait, 1) < 0 || read(xsvf_fd, &end, 1) < 0 || read(xsvf_fd, delay_buf, 4) < 0) { do_abort = 1; break; } wait_state = xsvf_to_tap(wait); end_state = xsvf_to_tap(end); delay = be_to_h_u32(delay_buf); LOG_DEBUG("XWAIT %s %s usecs:%d", tap_state_name(wait_state), tap_state_name(end_state), delay); if (runtest_requires_tck && wait_state == TAP_IDLE ) { jtag_add_runtest(delay, end_state); } else { xsvf_add_statemove( wait_state ); jtag_add_sleep(delay); xsvf_add_statemove( end_state ); } } break; case XWAITSTATE: { /* expected in stream: XWAITSTATE <u8 wait_state> <u8 end_state> <u32 clock_count> <u32 usecs> */ u8 clock_buf[4]; u8 usecs_buf[4]; u8 wait; u8 end; tap_state_t wait_state; tap_state_t end_state; int clock_count; int usecs; if ( read(xsvf_fd, &wait, 1) < 0 || read(xsvf_fd, &end, 1) < 0 || read(xsvf_fd, clock_buf, 4) < 0 || read(xsvf_fd, usecs_buf, 4) < 0 ) { do_abort = 1; break; } wait_state = xsvf_to_tap( wait ); end_state = xsvf_to_tap( end ); clock_count = be_to_h_u32(clock_buf); usecs = be_to_h_u32(usecs_buf); LOG_DEBUG("XWAITSTATE %s %s clocks:%i usecs:%i", tap_state_name(wait_state), tap_state_name(end_state), clock_count, usecs); /* the following states are 'stable', meaning that they have a transition * in the state diagram back to themselves. This is necessary because we will * be issuing a number of clocks in this state. This set of allowed states is also * determined by the SVF RUNTEST command's allowed states. */ if (wait_state != TAP_IRPAUSE && wait_state != TAP_DRPAUSE && wait_state != TAP_RESET && wait_state != TAP_IDLE) { LOG_ERROR("illegal XWAITSTATE wait_state: \"%s\"", tap_state_name( wait_state )); unsupported = 1; } xsvf_add_statemove( wait_state ); jtag_add_clocks( clock_count ); jtag_add_sleep( usecs ); xsvf_add_statemove( end_state ); } break; case LCOUNT: { /* expected in stream: LCOUNT <u32 loop_count> */ u8 count_buf[4]; if ( read(xsvf_fd, count_buf, 4) < 0 ) { do_abort = 1; break; } loop_count = be_to_h_u32(count_buf); LOG_DEBUG("LCOUNT %d", loop_count); } break; case LDELAY: { /* expected in stream: LDELAY <u8 wait_state> <u32 clock_count> <u32 usecs_to_sleep> */ u8 state; u8 clock_buf[4]; u8 usecs_buf[4]; if ( read(xsvf_fd, &state, 1) < 0 || read(xsvf_fd, clock_buf, 4) < 0 || read(xsvf_fd, usecs_buf, 4) < 0 ) { do_abort = 1; break; } loop_state = xsvf_to_tap(state); loop_clocks = be_to_h_u32(clock_buf); loop_usecs = be_to_h_u32(usecs_buf); LOG_DEBUG("LDELAY %s clocks:%d usecs:%d", tap_state_name(loop_state), loop_clocks, loop_usecs); } break; /* LSDR is more like XSDRTDO than it is like XSDR. It uses LDELAY which * comes with clocks !AND! sleep requirements. */ case LSDR: { int limit = loop_count; int matched = 0; int attempt; LOG_DEBUG("LSDR"); if ( xsvf_read_buffer(xsdrsize, xsvf_fd, dr_out_buf) != ERROR_OK || xsvf_read_buffer(xsdrsize, xsvf_fd, dr_in_buf) != ERROR_OK ) { do_abort = 1; break; } if (limit < 1) limit = 1; for( attempt=0; attempt<limit; ++attempt ) { scan_field_t field; xsvf_add_statemove( loop_state ); jtag_add_clocks(loop_clocks); jtag_add_sleep(loop_usecs); field.tap = tap; field.num_bits = xsdrsize; field.out_value = dr_out_buf; field.out_mask = NULL; field.in_value = NULL; if (attempt > 0 && verbose) LOG_USER("LSDR retry %d", attempt); jtag_set_check_value(&field, dr_in_buf, dr_in_mask, NULL); if (tap == NULL) jtag_add_plain_dr_scan(1, &field, TAP_DRPAUSE); else jtag_add_dr_scan(1, &field, TAP_DRPAUSE); /* LOG_DEBUG("FLUSHING QUEUE"); */ result = jtag_execute_queue(); if(result == ERROR_OK) { matched = 1; break; } } if (!matched ) { LOG_USER( "LSDR mismatch" ); tdo_mismatch = 1; break; } } break; case XTRST: { u8 trst_mode; if (read(xsvf_fd, &trst_mode, 1) < 0) { do_abort = 1; break; } switch( trst_mode ) { case XTRST_ON: jtag_add_reset(1, 0); break; case XTRST_OFF: case XTRST_Z: jtag_add_reset(0, 0); break; case XTRST_ABSENT: break; default: LOG_ERROR( "XTRST mode argument (0x%02X) out of range", trst_mode ); do_abort = 1; } } break; default: LOG_ERROR("unknown xsvf command (0x%02X)\n", uc); unsupported = 1; } if (do_abort || unsupported || tdo_mismatch) { LOG_DEBUG("xsvf failed, setting taps to reasonable state"); /* upon error, return the TAPs to a reasonable state */ xsvf_add_statemove( TAP_IDLE ); jtag_execute_queue(); break; } } if (tdo_mismatch) { command_print(cmd_ctx, "TDO mismatch, somewhere near offset %lu in xsvf file, aborting", file_offset ); return ERROR_FAIL; } if (unsupported) { command_print(cmd_ctx, "unsupported xsvf command: 0x%02X in xsvf file at offset %ld, aborting", uc, lseek(xsvf_fd, 0, SEEK_CUR)-1 ); return ERROR_FAIL; } if (do_abort) { command_print(cmd_ctx, "premature end of xsvf file detected, aborting"); return ERROR_FAIL; } if (dr_out_buf) free(dr_out_buf); if (dr_in_buf) free(dr_in_buf); if (dr_in_mask) free(dr_in_mask); close(xsvf_fd); command_print(cmd_ctx, "XSVF file programmed successfully"); return ERROR_OK; }