void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) { struct pcie_port *pp = &ks_pcie->pp; u32 start = pp->mem.start, end = pp->mem.end; int i, tr_size; /* Disable BARs for inbound access */ ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base); writel(0, pp->dbi_base + PCI_BASE_ADDRESS_0); writel(0, pp->dbi_base + PCI_BASE_ADDRESS_1); ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base); /* Set outbound translation size per window division */ writel(CFG_PCIM_WIN_SZ_IDX & 0x7, ks_pcie->va_app_base + OB_SIZE); tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M; /* Using Direct 1:1 mapping of RC <-> PCI memory space */ for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) { writel(start | 1, ks_pcie->va_app_base + OB_OFFSET_INDEX(i)); writel(0, ks_pcie->va_app_base + OB_OFFSET_HI(i)); start += tr_size; } /* Enable OB translation */ writel(OB_XLAT_EN_VAL | readl(ks_pcie->va_app_base + CMD_STATUS), ks_pcie->va_app_base + CMD_STATUS); }
void ks_dw_pcie_setup_rc_app_regs(struct keystone_pcie *ks_pcie) { struct dw_pcie *pci = ks_pcie->pci; struct pcie_port *pp = &pci->pp; u32 start = pp->mem->start, end = pp->mem->end; int i, tr_size; u32 val; /* Disable BARs for inbound access */ ks_dw_pcie_set_dbi_mode(ks_pcie); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_1, 0); ks_dw_pcie_clear_dbi_mode(ks_pcie); /* Set outbound translation size per window division */ ks_dw_app_writel(ks_pcie, OB_SIZE, CFG_PCIM_WIN_SZ_IDX & 0x7); tr_size = (1 << (CFG_PCIM_WIN_SZ_IDX & 0x7)) * SZ_1M; /* Using Direct 1:1 mapping of RC <-> PCI memory space */ for (i = 0; (i < CFG_PCIM_WIN_CNT) && (start < end); i++) { ks_dw_app_writel(ks_pcie, OB_OFFSET_INDEX(i), start | 1); ks_dw_app_writel(ks_pcie, OB_OFFSET_HI(i), 0); start += tr_size; } /* Enable OB translation */ val = ks_dw_app_readl(ks_pcie, CMD_STATUS); ks_dw_app_writel(ks_pcie, CMD_STATUS, OB_XLAT_EN_VAL | val); }
/** * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization * * This sets BAR0 to enable inbound access for MSI_IRQ register */ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) { struct keystone_pcie *ks_pcie = to_keystone_pcie(pp); /* Configure and set up BAR0 */ ks_dw_pcie_set_dbi_mode(ks_pcie->va_app_base); /* Enable BAR0 */ writel(1, pp->dbi_base + PCI_BASE_ADDRESS_0); writel(SZ_4K - 1, pp->dbi_base + PCI_BASE_ADDRESS_0); ks_dw_pcie_clear_dbi_mode(ks_pcie->va_app_base); /* * For BAR0, just setting bus address for inbound writes (MSI) should * be sufficient. Use physical address to avoid any conflicts. */ writel(ks_pcie->app.start, pp->dbi_base + PCI_BASE_ADDRESS_0); }
/** * ks_dw_pcie_v3_65_scan_bus() - keystone scan_bus post initialization * * This sets BAR0 to enable inbound access for MSI_IRQ register */ void ks_dw_pcie_v3_65_scan_bus(struct pcie_port *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); struct keystone_pcie *ks_pcie = to_keystone_pcie(pci); /* Configure and set up BAR0 */ ks_dw_pcie_set_dbi_mode(ks_pcie); /* Enable BAR0 */ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 1); dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, SZ_4K - 1); ks_dw_pcie_clear_dbi_mode(ks_pcie); /* * For BAR0, just setting bus address for inbound writes (MSI) should * be sufficient. Use physical address to avoid any conflicts. */ dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, ks_pcie->app.start); }