static void change_register (running_machine *machine, int reg, UINT8 val) {
static const UINT8 Mask[8] =
{ 0x03, 0xfb, 0x0f, 0xff, 0x07, 0x7f, 0x07, 0xff };
static const char *const modes[] = {
"Mode 0 (GRAPHIC 1)", "Mode 1 (TEXT 1)", "Mode 2 (GRAPHIC 2)",
"Mode 1+2 (TEXT 1 variation)", "Mode 3 (MULTICOLOR)",
"Mode 1+3 (BOGUS)", "Mode 2+3 (MULTICOLOR variation)",
"Mode 1+2+3 (BOGUS)" };
UINT8 b;
val &= Mask[reg];
tms.Regs[reg] = val;
logerror("TMS9928A: Reg %d = %02xh\n", reg, (int)val);
switch (reg) {
case 0:
/* re-calculate masks and pattern generator & colour */
if (val & 2) {
tms.colour = ((tms.Regs[3] & 0x80) * 64) & (tms.vramsize - 1);
tms.colourmask = (tms.Regs[3] & 0x7f) * 8 | 7;
tms.pattern = ((tms.Regs[4] & 4) * 2048) & (tms.vramsize - 1);
tms.patternmask = (tms.Regs[4] & 3) * 256 |
(tms.colourmask & 255);
} else {
tms.colour = (tms.Regs[3] * 64) & (tms.vramsize - 1);
tms.pattern = (tms.Regs[4] * 2048) & (tms.vramsize - 1);
}
logerror("TMS9928A: %s\n", modes[TMS_MODE]);
break;
case 1:
/* check for changes in the INT line */
b = (val & 0x20) && (tms.StatusReg & 0x80) ;
if (b != tms.INT) {
tms.INT = b;
if (tms.INTCallback) tms.INTCallback (machine, tms.INT);
}
logerror("TMS9928A: %s\n", modes[TMS_MODE]);
break;
case 2:
tms.nametbl = (val * 1024) & (tms.vramsize - 1);
break;
case 3:
if (tms.Regs[0] & 2) {
tms.colour = ((val & 0x80) * 64) & (tms.vramsize - 1);
tms.colourmask = (val & 0x7f) * 8 | 7;
} else {
tms.colour = (val * 64) & (tms.vramsize - 1);
}
tms.patternmask = (tms.Regs[4] & 3) * 256 | (tms.colourmask & 255);
break;
case 4:
if (tms.Regs[0] & 2) {
tms.pattern = ((val & 4) * 2048) & (tms.vramsize - 1);
tms.patternmask = (val & 3) * 256 | 255;
} else {
tms.pattern = (val * 2048) & (tms.vramsize - 1);
}
break;
case 5:
tms.spriteattribute = (val * 128) & (tms.vramsize - 1);
break;
case 6:
tms.spritepattern = (val * 2048) & (tms.vramsize - 1);
break;
case 7:
/* The backdrop is updated at TMS9928A_refresh() */
break;
}
}
static WRITE_HANDLER(switches_w) {
logerror("switch write: %i %i\n", offset, data);
}
ADDRESS_MAP_END
TIMER_CALLBACK_MEMBER(tubep_state::rjammer_scanline_callback)
{
int scanline = param;
m_curr_scanline = scanline;//for debugging
/* CPU #0 interrupt */
/* activates at the start of VBLANK signal which happens at the beginning of scaline number 240 */
if (scanline == 240)
{
logerror("VBLANK CPU#0\n");
m_maincpu->set_input_line(0, ASSERT_LINE);
}
/* CPU #1 interrupt */
/* activates at the _end_ of VBLANK signal which happens at the beginning of scanline number 16 */
if (scanline == 16)
{
logerror("/VBLANK CPU#1\n");
m_slave->set_input_line(0, HOLD_LINE);
}
/* CPU #3 MS2010-A NMI */
/* activates at the _end_ of VBLANK signal which happens at the beginning of scanline number 16 */
if (scanline == 16)
{
logerror("/nmi CPU#3\n");
tubep_vblank_end(); /* switch buffered sprite RAM page */
m_mcu->set_input_line(INPUT_LINE_NMI, ASSERT_LINE);
}
/* CPU #3 MS2010-A NMI */
/* deactivates at the start of VBLANK signal which happens at the beginning of scanline number 240*/
if (scanline == 240)
{
logerror("CPU#3 nmi clear\n");
m_mcu->set_input_line(INPUT_LINE_NMI, CLEAR_LINE);
}
/* sound CPU interrupt */
/* activates whenever line V6 from video part goes lo->hi that is when the scanline becomes 64 and 192 */
if ((scanline == 64) || (scanline == 192))
{
m_soundcpu->set_input_line(0, ASSERT_LINE); /* sound cpu interrupt (music tempo) */
}
m_screen->update_partial(m_screen->vpos());
logerror("scanline=%3i scrgetvpos(0)=%3i\n", scanline, m_screen->vpos());
scanline++;
if (scanline >= 264)
scanline = 0;
m_interrupt_timer->adjust(m_screen->time_until_pos(scanline), scanline);
}
static WRITE16_HANDLER( rprot_w )
{
logerror("rprot_w %02x\n", data);
}
static void HandleMemSingle( UINT32 insn )
{
UINT32 rn, rnv, off, rd;
/* Fetch the offset */
if (insn & INSN_I)
{
off = decodeShift(insn, NULL);
}
else
{
off = insn & INSN_SDT_IMM;
}
/* Calculate Rn, accounting for PC */
rn = (insn & INSN_RN) >> INSN_RN_SHIFT;
// if (rn==0xf) logerror("%08x: Source R15\n",R15);
if (insn & INSN_SDT_P)
{
/* Pre-indexed addressing */
if (insn & INSN_SDT_U)
{
rnv = (GetRegister(rn) + off);
}
else
{
rnv = (GetRegister(rn) - off);
}
if (insn & INSN_SDT_W)
{
SetRegister(rn,rnv);
if (ARM_DEBUG_CORE && rn == eR15)
logerror("writeback R15 %08x\n", R15);
}
else if (rn == eR15)
{
rnv = (rnv & ADDRESS_MASK) + 8;
}
}
else
{
/* Post-indexed addressing */
if (rn == eR15)
{
rnv = (R15 & ADDRESS_MASK) + 8;
}
else
{
rnv = GetRegister(rn);
}
}
/* Do the transfer */
rd = (insn & INSN_RD) >> INSN_RD_SHIFT;
if (insn & INSN_SDT_L)
{
/* Load */
arm_icount -= S_CYCLE + I_CYCLE + N_CYCLE;
if (insn & INSN_SDT_B)
{
if (ARM_DEBUG_CORE && rd == eR15)
logerror("read byte R15 %08x\n", R15);
SetRegister(rd,(UINT32) READ8(rnv));
}
else
{
if (rd == eR15)
{
R15 = (READ32(rnv) & ADDRESS_MASK) | (R15 & PSR_MASK) | (R15 & MODE_MASK);
change_pc(R15 & ADDRESS_MASK);
/*
The docs are explicit in that the bottom bits should be masked off
when writing to R15 in this way, however World Cup Volleyball 95 has
an example of an unaligned jump (bottom bits = 2) where execution
should definitely continue from the rounded up address.
In other cases, 4 is subracted from R15 here to account for pipelining.
*/
if ((READ32(rnv)&3)==0)
R15 -= 4;
arm_icount -= S_CYCLE + N_CYCLE;
}
else
{
SetRegister(rd,READ32(rnv));
}
}
}
else
{
/* Store */
arm_icount -= 2 * N_CYCLE;
if (insn & INSN_SDT_B)
{
if (ARM_DEBUG_CORE && rd==eR15)
logerror("Wrote R15 in byte mode\n");
WRITE8(rnv, (UINT8) GetRegister(rd) & 0xffu);
}
else
{
if (ARM_DEBUG_CORE && rd==eR15)
logerror("Wrote R15 in 32bit mode\n");
WRITE32(rnv, rd == eR15 ? R15 + 8 : GetRegister(rd));
}
}
/* Do post-indexing writeback */
if (!(insn & INSN_SDT_P)/* && (insn&INSN_SDT_W)*/)
{
if (insn & INSN_SDT_U)
{
/* Writeback is applied in pipeline, before value is read from mem,
so writeback is effectively ignored */
if (rd==rn) {
SetRegister(rn,GetRegister(rd));
}
else {
if ((insn&INSN_SDT_W)!=0)
logerror("%08x: RegisterWritebackIncrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0);
SetRegister(rn,(rnv + off));
}
}
else
{
/* Writeback is applied in pipeline, before value is read from mem,
so writeback is effectively ignored */
if (rd==rn) {
SetRegister(rn,GetRegister(rd));
}
else {
SetRegister(rn,(rnv - off));
if ((insn&INSN_SDT_W)!=0)
logerror("%08x: RegisterWritebackDecrement %d %d %d\n",R15,(insn & INSN_SDT_P)!=0,(insn&INSN_SDT_W)!=0,(insn & INSN_SDT_U)!=0);
}
}
}
} /* HandleMemSingle */
static int arm_execute( int cycles )
{
UINT32 pc;
UINT32 insn;
arm_icount = cycles;
do
{
CALL_MAME_DEBUG;
/* load instruction */
pc = R15;
insn = cpu_readop32( pc & ADDRESS_MASK );
switch (insn >> INSN_COND_SHIFT)
{
case COND_EQ:
if (Z_IS_CLEAR(pc)) goto L_Next;
break;
case COND_NE:
if (Z_IS_SET(pc)) goto L_Next;
break;
case COND_CS:
if (C_IS_CLEAR(pc)) goto L_Next;
break;
case COND_CC:
if (C_IS_SET(pc)) goto L_Next;
break;
case COND_MI:
if (N_IS_CLEAR(pc)) goto L_Next;
break;
case COND_PL:
if (N_IS_SET(pc)) goto L_Next;
break;
case COND_VS:
if (V_IS_CLEAR(pc)) goto L_Next;
break;
case COND_VC:
if (V_IS_SET(pc)) goto L_Next;
break;
case COND_HI:
if (C_IS_CLEAR(pc) || Z_IS_SET(pc)) goto L_Next;
break;
case COND_LS:
if (C_IS_SET(pc) && Z_IS_CLEAR(pc)) goto L_Next;
break;
case COND_GE:
if (!(pc & N_MASK) != !(pc & V_MASK)) goto L_Next; /* Use x ^ (x >> ...) method */
break;
case COND_LT:
if (!(pc & N_MASK) == !(pc & V_MASK)) goto L_Next;
break;
case COND_GT:
if (Z_IS_SET(pc) || (!(pc & N_MASK) != !(pc & V_MASK))) goto L_Next;
break;
case COND_LE:
if (Z_IS_CLEAR(pc) && (!(pc & N_MASK) == !(pc & V_MASK))) goto L_Next;
break;
case COND_NV:
goto L_Next;
}
/* Condition satisfied, so decode the instruction */
if ((insn & 0x0fc000f0u) == 0x00000090u) /* Multiplication */
{
HandleMul(insn);
R15 += 4;
}
else if (!(insn & 0x0c000000u)) /* Data processing */
{
HandleALU(insn);
}
else if ((insn & 0x0c000000u) == 0x04000000u) /* Single data access */
{
HandleMemSingle(insn);
R15 += 4;
}
else if ((insn & 0x0e000000u) == 0x08000000u ) /* Block data access */
{
HandleMemBlock(insn);
R15 += 4;
}
else if ((insn & 0x0e000000u) == 0x0a000000u) /* Branch */
{
HandleBranch(insn);
}
else if ((insn & 0x0f000000u) == 0x0e000000u) /* Coprocessor */
{
HandleCoPro(insn);
R15 += 4;
}
else if ((insn & 0x0f000000u) == 0x0f000000u) /* Software interrupt */
{
pc=R15+4;
R15 = eARM_MODE_SVC; /* Set SVC mode so PC is saved to correct R14 bank */
SetRegister( 14, pc ); /* save PC */
R15 = (pc&PSR_MASK)|(pc&IRQ_MASK)|0x8|eARM_MODE_SVC|I_MASK|(pc&MODE_MASK);
change_pc(pc&ADDRESS_MASK);
arm_icount -= 2 * S_CYCLE + N_CYCLE;
}
else /* Undefined */
{
logerror("%08x: Undefined instruction\n",R15);
L_Next:
arm_icount -= S_CYCLE;
R15 += 4;
}
arm_check_irq_state();
} while( arm_icount > 0 );
return cycles - arm_icount;
} /* arm_execute */
INLINE void cpu_write32( int addr, UINT32 data )
{
/* Unaligned writes are treated as normal writes */
program_write_dword_32le(addr&ADDRESS_MASK,data);
if (ARM_DEBUG_CORE && addr&3) logerror("%08x: Unaligned write %08x\n",R15,addr);
}
