void ltq_disable_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; int irq_nr = d->irq - INT_NUM_IRQ0; ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); irq_nr %= INT_NUM_IM_OFFSET; ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); }
void ltq_disable_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE; int im = offset / INT_NUM_IM_OFFSET; offset %= INT_NUM_IM_OFFSET; ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier); }
void ltq_mask_and_ack_irq(struct irq_data *d) { u32 ier = LTQ_ICU_IM0_IER; u32 isr = LTQ_ICU_IM0_ISR; int irq_nr = d->irq - INT_NUM_IRQ0; ier += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); isr += LTQ_ICU_OFFSET * (irq_nr / INT_NUM_IM_OFFSET); irq_nr %= INT_NUM_IM_OFFSET; ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); ltq_icu_w32((1 << irq_nr), isr); }
static void ltq_hw_irqdispatch(int module) { u32 irq; irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET)); if (irq == 0) return; irq = __fls(irq); do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, LTQ_EBU_PCC_ISTAT); }
static void ltq_hw_irqdispatch(int module) { u32 irq; irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET)); if (irq == 0) return; /* silicon bug causes only the msb set to 1 to be valid. all * other bits might be bogus */ irq = __fls(irq); do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); /* if this is a EBU irq, we need to ack it or get a deadlock */ if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, LTQ_EBU_PCC_ISTAT); }