/* * mdp4_overlay0_done_mddi: called from isr */ void mdp4_overlay0_done_mddi(struct mdp_dma_data *dma) { int diff; if (mddi_pipe->blt_addr == 0) { mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE); spin_lock(&mdp_spin_lock); dma->busy = FALSE; spin_unlock(&mdp_spin_lock); complete(&dma->comp); if (busy_wait_cnt) busy_wait_cnt--; mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); return; } /* blt enabled */ if (mddi_pipe->blt_end == 0) mddi_pipe->ov_cnt++; pr_debug("%s: ov_cnt=%d dmap_cnt=%d\n", __func__, mddi_pipe->ov_cnt, mddi_pipe->dmap_cnt); if (mddi_pipe->blt_cnt == 0) { /* first kickoff since blt enabled */ mdp_intr_mask |= INTR_DMA_P_DONE; outp32(MDP_INTR_ENABLE, mdp_intr_mask); } mddi_pipe->blt_cnt++; diff = mddi_pipe->ov_cnt - mddi_pipe->dmap_cnt; if (diff >= 2) { mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); return; } spin_lock(&mdp_spin_lock); dma->busy = FALSE; dma->dmap_busy = TRUE; spin_unlock(&mdp_spin_lock); complete(&dma->comp); if (busy_wait_cnt) busy_wait_cnt--; pr_debug("%s: kickoff dmap\n", __func__); mdp4_blt_xy_update(mddi_pipe); mdp_enable_irq(MDP_DMA2_TERM); /* enable intr */ /* kick off dmap */ outpdw(MDP_BASE + 0x000c, 0x0); mdp4_stat.kickoff_dmap++; mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); }
/* * mdp4_overlay0_done_dsi_cmd: called from isr */ void mdp4_overlay0_done_dsi_cmd(struct mdp_dma_data *dma) { int diff; if (dsi_pipe->blt_addr == 0) { spin_lock(&mdp_spin_lock); dma->busy = FALSE; spin_unlock(&mdp_spin_lock); complete(&dma->comp); if (busy_wait_cnt) busy_wait_cnt--; mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); return; } /* blt enabled */ if (dsi_pipe->blt_end == 0) dsi_pipe->ov_cnt++; pr_debug("%s: ov_cnt=%d dmap_cnt=%d\n", __func__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt); if (dsi_pipe->blt_cnt == 0) { /* first kickoff since blt enabled */ mdp_intr_mask |= INTR_DMA_P_DONE; outp32(MDP_INTR_ENABLE, mdp_intr_mask); } dsi_pipe->blt_cnt++; diff = dsi_pipe->ov_cnt - dsi_pipe->dmap_cnt; if (diff >= 2) { mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); return; } spin_lock(&mdp_spin_lock); dma->busy = FALSE; dma->dmap_busy = TRUE; spin_unlock(&mdp_spin_lock); complete(&dma->comp); if (busy_wait_cnt) busy_wait_cnt--; pr_debug("%s: kickoff dmap\n", __func__); mdp4_blt_xy_update(dsi_pipe); mdp_enable_irq(MDP_DMA2_TERM); /* enable intr */ /* kick off dmap */ outpdw(MDP_BASE + 0x000c, 0x0); mdp4_stat.kickoff_dmap++; /* trigger dsi cmd engine */ mipi_dsi_cmd_mdp_start(); mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); }
/* * mdp4_overlay1_done_dsi_cmd: called from isr */ void mdp4_overlay0_done_dsi_cmd() { mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); if (busy_wait_cnt) busy_wait_cnt--; }
/* * mdp4_overlay0_done_mddi: called from isr */ void mdp4_overlay0_done_mddi(struct mdp_dma_data *dma) { mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); dma->busy = FALSE; complete(&dma->comp); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE); if (busy_wait_cnt) busy_wait_cnt--; pr_debug("%s: ISR-done\n", __func__); if (mddi_pipe->blt_addr) { if (mddi_pipe->blt_cnt == 0) { mdp4_overlayproc_cfg(mddi_pipe); mdp4_overlay_dmap_xy(mddi_pipe); mddi_pipe->ov_cnt = 0; mddi_pipe->dmap_cnt = 0; /* BLT start from next frame */ } else { mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_ON, FALSE); mdp4_blt_xy_update(mddi_pipe); outpdw(MDP_BASE + 0x000c, 0x0); /* start DMAP */ } mddi_pipe->blt_cnt++; mddi_pipe->ov_cnt++; } }
/* * mdp4_overlay0_done_mddi: called from isr */ void mdp4_overlay0_done_mddi() { mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); if (pending_pipe) complete(&pending_pipe->comp); }
static void vsync_irq_disable_nosync(int intr, int term) { outp32(MDP_INTR_CLEAR, intr); mdp_intr_mask &= ~intr; outp32(MDP_INTR_ENABLE, mdp_intr_mask); mdp_disable_irq_nosync(term); pr_debug("%s: IRQ-dis done, term=%x\n", __func__, term); }
/* * mdp4_dmap_done_dsi: called from isr * DAM_P_DONE only used when blt enabled */ void mdp4_dma_p_done_dsi(struct mdp_dma_data *dma) { int diff; spin_lock(&mdp_done_lock); mdp_disable_irq_nosync(MDP_DMA2_TERM); /* disable intr */ spin_lock(&mdp_spin_lock); dsi_pipe->dmap_cnt++; diff = dsi_pipe->ov_cnt - dsi_pipe->dmap_cnt; #ifdef BLTDEBUG printk(KERN_INFO "%s: ov_cnt=%d dmap_cnt=%d\n", __func__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt); #endif if (diff <= 0) { dma->dmap_busy = FALSE; dma->dmap_pid = __LINE__; complete(&dma->dmap_comp); if (dsi_pipe->blt_end) { dsi_pipe->blt_end = 0; dsi_pipe->blt_addr = 0; wmb(); #ifdef BLTDEBUG PR_DISP_INFO("%s(%d): END, ov_cnt=%d dmap_cnt=%d\n", __func__, __LINE__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt); #endif mdp_intr_mask &= ~INTR_DMA_P_DONE; outp32(MDP_INTR_ENABLE, mdp_intr_mask); } spin_unlock(&mdp_spin_lock); spin_unlock(&mdp_done_lock); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE); return; } dma->busy = FALSE; dma->busy_pid = __LINE__; spin_unlock(&mdp_spin_lock); complete(&dma->comp); if (atomic_read(&busy_wait_cnt)) atomic_dec(&busy_wait_cnt); mdp4_blt_xy_update(dsi_pipe); mdp_enable_irq(MDP_DMA2_TERM); /* enable intr */ spin_unlock(&mdp_done_lock); #ifdef BLTDEBUG printk(KERN_INFO "%s: kickoff dmap\n", __func__); #endif /* kick off dmap */ outpdw(MDP_BASE + 0x000c, 0x0); wmb(); /* trigger dsi cmd engine */ mipi_dsi_cmd_mdp_sw_trigger(); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE); }
/* * mdp4_overlay1_done_dsi: called from isr */ void mdp4_overlay0_done_dsi_video(struct mdp_dma_data *dma) { spin_lock(&mdp_spin_lock); dma->busy = FALSE; mdp4_dsi_video_blt_dmap_update(dsi_pipe); dsi_pipe->dmap_cnt++; mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); spin_unlock(&mdp_spin_lock); complete(&dma->comp); }
/* * mdp4_overlay0_done_mddi: called from isr */ void mdp4_overlay0_done_mddi() { #ifdef MDP4_NONBLOCKING mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); #endif if (pending_pipe) complete(&pending_pipe->comp); }
/* * mdp4_overlay0_done_dsi_cmd: called from isr */ void mdp4_overlay0_done_dsi_cmd(struct mdp_dma_data *dma) { int diff; mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); spin_lock(&mdp_spin_lock); rmb(); if (dsi_pipe->blt_addr == 0) { dma->busy = FALSE; complete(&dma->comp); if (atomic_read(&busy_wait_cnt)) atomic_dec(&busy_wait_cnt); spin_unlock(&mdp_spin_lock); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE); return; } /* blt enabled */ if (dsi_pipe->blt_end == 0) dsi_pipe->ov_cnt++; #ifdef BLTDEBUG printk("%s: ov_cnt=%d dmap_cnt=%d\n", __func__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt); #endif if (dsi_pipe->blt_cnt == 0) { /* first kickoff since blt enabled */ mdp_intr_mask |= INTR_DMA_P_DONE; outp32(MDP_INTR_ENABLE, mdp_intr_mask); } dsi_pipe->blt_cnt++; diff = dsi_pipe->ov_cnt - dsi_pipe->dmap_cnt; if (diff >= 2) { spin_unlock(&mdp_spin_lock); return; } dma->busy = FALSE; dma->dmap_busy = TRUE; complete(&dma->comp); if (atomic_read(&busy_wait_cnt)) atomic_dec(&busy_wait_cnt); spin_unlock(&mdp_spin_lock); mdp4_blt_xy_update(dsi_pipe); mdp_enable_irq(MDP_DMA2_TERM); /* enable intr */ #ifdef BLTDEBUG printk("%s: kickoff dmap\n", __func__); #endif /* kick off dmap */ outpdw(MDP_BASE + 0x000c, 0x0); /* trigger dsi cmd engine */ mipi_dsi_cmd_mdp_sw_trigger(); }
static void vsync_irq_disable(int intr, int term) { unsigned long flag; spin_lock_irqsave(&mdp_spin_lock, flag); /* no need to clrear other interrupts for comamnd mode */ mdp_intr_mask &= ~intr; outp32(MDP_INTR_ENABLE, mdp_intr_mask); mdp_disable_irq_nosync(term); spin_unlock_irqrestore(&mdp_spin_lock, flag); }
static void vsync_irq_disable(int intr, int term) { unsigned long flag; spin_lock_irqsave(&mdp_spin_lock, flag); mdp_intr_mask &= ~intr; outp32(MDP_INTR_ENABLE, mdp_intr_mask); mdp_disable_irq_nosync(term); spin_unlock_irqrestore(&mdp_spin_lock, flag); }
static void vsync_irq_disable(int intr, int term) { unsigned long flag; spin_lock_irqsave(&mdp_spin_lock, flag); outp32(MDP_INTR_CLEAR, intr); mdp_intr_mask &= ~intr; outp32(MDP_INTR_ENABLE, mdp_intr_mask); mdp_disable_irq_nosync(term); spin_unlock_irqrestore(&mdp_spin_lock, flag); pr_debug("%s: IRQ-dis done, term=%x\n", __func__, term); }
void mdp4_overlay1_done_writeback(struct mdp_dma_data *dma) { spin_lock(&mdp_spin_lock); dma->busy = FALSE; if (busy_wait_cnt) busy_wait_cnt = 0; mdp_disable_irq_nosync(MDP_OVERLAY2_TERM); spin_unlock(&mdp_spin_lock); complete_all(&dma->comp); pr_debug("%s ovdone interrupt\n", __func__); }
/* * mdp4_overlay0_done_lcdc: called from isr */ void mdp4_overlay0_done_lcdc(struct mdp_dma_data *dma) { spin_lock(&mdp_spin_lock); dma->busy = FALSE; if (lcdc_pipe->blt_addr == 0) { spin_unlock(&mdp_spin_lock); return; } mdp4_lcdc_blt_dmap_update(lcdc_pipe); lcdc_pipe->dmap_cnt++; mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); spin_unlock(&mdp_spin_lock); complete(&dma->comp); }
/* * mdp4_dmap_done_dsi: called from isr * DAM_P_DONE only used when blt enabled */ void mdp4_dma_p_done_dsi(struct mdp_dma_data *dma) { int diff; dsi_pipe->dmap_cnt++; diff = dsi_pipe->ov_cnt - dsi_pipe->dmap_cnt; pr_debug("%s: ov_cnt=%d dmap_cnt=%d\n", __func__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt); if (diff <= 0) { spin_lock(&mdp_spin_lock); dma->dmap_busy = FALSE; complete(&dma->dmap_comp); spin_unlock(&mdp_spin_lock); if (dsi_pipe->blt_end) { dsi_pipe->blt_end = 0; dsi_pipe->blt_addr = 0; wmb(); pr_debug("%s: END, ov_cnt=%d dmap_cnt=%d\n", __func__, dsi_pipe->ov_cnt, dsi_pipe->dmap_cnt); mdp_intr_mask &= ~INTR_DMA_P_DONE; outp32(MDP_INTR_ENABLE, mdp_intr_mask); } ov_cnt++; mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE); mdp_disable_irq_nosync(MDP_DMA2_TERM); /* disable intr */ return; } spin_lock(&mdp_spin_lock); dma->busy = FALSE; spin_unlock(&mdp_spin_lock); complete(&dma->comp); if (busy_wait_cnt) busy_wait_cnt--; pr_debug("%s: kickoff dmap\n", __func__); mdp4_blt_xy_update(dsi_pipe); /* kick off dmap */ outpdw(MDP_BASE + 0x000c, 0x0); mdp4_stat.kickoff_dmap++; wmb(); /* trigger dsi cmd engine */ mipi_dsi_cmd_mdp_start(); ov_cnt++; mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE); }
/* * mdp4_dma_p_done_dsi: called from isr * DAM_P_DONE only used when blt enabled */ void mdp4_dma_p_done_dsi(struct mdp_dma_data *dma) { spin_lock(&mdp_spin_lock); dma->dmap_busy = FALSE; spin_unlock(&mdp_spin_lock); complete(&dma->dmap_comp); mdp_disable_irq_nosync(MDP_DMA2_TERM); if (dsi_pipe && dsi_pipe->ov_blt_addr) { spin_lock(&mdp_spin_lock); mdp4_blt_dmap_xy_update(dsi_pipe); if (dsi_pipe->blt_end) { dsi_pipe->blt_end = 0; dsi_pipe->dma_blt_addr = 0; dsi_pipe->ov_blt_addr = 0; } spin_unlock(&mdp_spin_lock); } mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE); }
/* * mdp4_overlay0_done_mddi: called from isr */ void mdp4_overlay0_done_mddi(struct mdp_dma_data *dma) { mdp_disable_irq_nosync(MDP_OVERLAY0_TERM); dma->busy = FALSE; /* FUJITSU:2012-05-29 DISP add prevent set_lut interruption start */ mutex_unlock(&msm_fb_ioctl_lut_sem); /* FUJITSU:2012-05-29 DISP add prevent set_lut interruption end */ complete(&dma->comp); mdp_pipe_ctrl(MDP_OVERLAY0_BLOCK, MDP_BLOCK_POWER_OFF, TRUE); if (busy_wait_cnt) busy_wait_cnt--; pr_debug("%s: ISR-done\n", __func__); if (mddi_pipe->blt_addr) { if (mddi_pipe->blt_cnt == 0) { mdp4_overlayproc_cfg(mddi_pipe); mdp4_overlay_dmap_xy(mddi_pipe); mddi_pipe->ov_cnt = 0; mddi_pipe->dmap_cnt = 0; /* BLT start from next frame */ } else { mdp_pipe_ctrl(MDP_DMA2_BLOCK, MDP_BLOCK_POWER_ON, FALSE); mdp4_blt_xy_update(mddi_pipe); outpdw(MDP_BASE + 0x000c, 0x0); /* start DMAP */ } mddi_pipe->blt_cnt++; mddi_pipe->ov_cnt++; } }
void mdp4_dma_s_done_mddi() { mdp_disable_irq_nosync(MDP_DMA_S_TERM); if (pending_pipe) complete(&pending_pipe->comp); }