void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; int needs_reset; unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); pc87360_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_default_resource_map(); needs_reset = setup_coherent_ht_domain(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* This is needed to be able to call udelay(). It could be moved to * memreset_setup, since udelay is called in memreset. */ init_timer(); // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); memreset_setup(); sdram_initialize(nodes, ctrl); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; int needs_reset; unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_khepri_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif needs_reset |= ht_setup_chains_x(); if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); memreset_setup(); sdram_initialize(nodes, ctrl); #if 0 dump_pci_devices(); #endif post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const u16 spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; int needs_reset; unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); lpc47b397_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); sio_gpio_setup(); setup_mb_resource_map(); needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); memreset_setup(); sdram_initialize(nodes, ctrl); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { //first node RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node RC1|DIMM0, RC1|DIMM2, RC1|DIMM4, RC1|DIMM6, RC1|DIMM1, RC1|DIMM3, RC1|DIMM5, RC1|DIMM7, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 // third node RC2|DIMM0, RC2|DIMM2, 0, 0, RC2|DIMM1, RC2|DIMM3, 0, 0, // four node RC3|DIMM0, RC3|DIMM2, RC3|DIMM4, RC3|DIMM6, RC3|DIMM1, RC3|DIMM3, RC3|DIMM5, RC3|DIMM7, #endif }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset; unsigned bsp_apicid = 0; #if CONFIG_SET_FIDVID struct cpuid_result cpuid1; #endif if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_mb_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if 0 //it your CPU min fid is 1G, you can change HT to 1G and FID to max one time. needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); #endif #if CONFIG_SET_FIDVID /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { { /* Read FIDVID_STATUS */ msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } } else { print_debug("Changing FIDVID not supported\n"); } #endif #if 1 needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } #endif allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); #if 0 int i; for(i=0;i<4;i++) { activate_spd_rom(&cpu[i]); dump_smbus_registers(); } #endif memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ // init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 print_pci_devices(); #endif #if 0 // dump_pci_devices(); dump_pci_device_index_wait(PCI_DEV(0, 0x18, 2), 0x98); dump_pci_device_index_wait(PCI_DEV(0, 0x19, 2), 0x98); #endif post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { struct sys_info *sysinfo = &sysinfo_car; u32 bsp_apicid = 0, val; msr_t msr; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ /* mov bsp to bus 0xff when > 8 nodes */ set_bsp_node_CHtExtNodeCfgEn(); enumerate_ht_chain(); } post_code(0x30); if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); /* mmconf is inited in init_cpus */ /* All cores run this but the BSP(node0,core0) is the only core that returns. */ } post_code(0x32); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); // dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE); /* Halt if there was a built in self test failure */ report_bist_failure(bist); // Load MPB val = cpuid_eax(1); printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); update_microcode(val); post_code(0x33); cpuSetAMDMSR(); post_code(0x34); amd_ht_init(sysinfo); post_code(0x35); /* Setup nodes PCI space and start core 0 AP init. */ finalize_node_setup(sysinfo); /* Setup any mainboard PCI settings etc. */ setup_mb_resource_map(); post_code(0x36); /* wait for all the APs core0 started by finalize_node_setup. */ /* FIXME: A bunch of cores are going to start output to serial at once. It would be nice to fixup prink spinlocks for ROM XIP mode. I think it could be done by putting the spinlock flag in the cache of the BSP located right after sysinfo. */ wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS /* Core0 on each node is configured. Now setup any additional cores. */ printk(BIOS_DEBUG, "start_other_cores()\n"); start_other_cores(); post_code(0x37); wait_all_other_cores_started(bsp_apicid); #endif post_code(0x38); #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x39); if (!warm_reset_detect(0)) { // BSP is node 0 init_fidvid_bsp(bsp_apicid, sysinfo->nodes); } else { init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0 } post_code(0x3A); /* show final fid and vid */ msr=rdmsr(0xc0010071); printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ if (!warm_reset_detect(0)) { print_info("...WARM RESET...\n\n\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); die("After soft_reset_x - shouldn't see this message!!!\n"); } post_code(0x3B); /* FIXME: Move this to chipset init. enable cf9 for hard reset */ print_debug("enable_cf9_x()\n"); enable_cf9_x(sysinfo->sbbusn, sysinfo->sbdn); post_code(0x3C); /* It's the time to set ctrl in sysinfo now; */ printk(BIOS_DEBUG, "fill_mem_ctrl()\n"); fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); post_code(0x3D); printk(BIOS_DEBUG, "enable_smbus()\n"); enable_smbus(); post_code(0x3E); memreset_setup(); post_code(0x40); // die("Die Before MCT init."); printk(BIOS_DEBUG, "raminit_amdmct()\n"); raminit_amdmct(sysinfo); post_code(0x41); /* dump_pci_device_range(PCI_DEV(0, 0x18, 0), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 1), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 2), 0, 0x200); dump_pci_device_range(PCI_DEV(0, 0x18, 3), 0, 0x200); */ // die("After MCT init before CAR disabled."); post_code(0x42); post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB. post_code(0x43); // Should never see this post code. }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr[] = { // first node DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, // second node DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, }; struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE); int needs_reset; unsigned bsp_apicid = 0; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); /* Setup the rom access for 4M */ amd8111_enable_rom(); } if (bist == 0) { bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo); } w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); uart_init(); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_mb_resource_map(); print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\n"); #if CONFIG_MEM_TRAIN_SEQ == 1 set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram #endif setup_coherent_ht_domain(); // routing table and start other core0 wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain, * So here need to make sure last core0 is started, esp for two way system, * (there may be apic id conflicts in that case) */ start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif /* it will set up chains and store link pair for optimization later */ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn #if SET_FIDVID == 1 { msr_t msr; msr=rdmsr(0xc0010042); print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr=rdmsr(0xc0010042); print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\n"); } #endif needs_reset = optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); // fidvid change will issue one LDTSTOP and the HT change will be effective too if (needs_reset) { print_info("ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl in sysinfo now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); enable_smbus(); #if 0 dump_smbus_registers(); #endif memreset_setup(); //do we need apci timer, tsc...., only debug need it for better output /* all ap stopped? */ init_timer(); // Need to use TMICT to synconize FID/VID sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); #if 0 dump_pci_devices(); #endif post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { //first node RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 //second node RC1|DIMM0, RC1|DIMM2, 0, 0, RC1|DIMM1, RC1|DIMM3, 0, 0, #endif }; struct sys_info *sysinfo = &sysinfo_car; int needs_reset = 0; unsigned bsp_apicid = 0; if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx,sysinfo); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); setup_dl145g1_resource_map(); //setup_default_resource_map(); setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif ht_setup_chains_x(sysinfo); #if CONFIG_SET_FIDVID /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ struct cpuid_result cpuid1 = cpuid(0x80000007); if ((cpuid1.edx & 0x6) == 0x6) { { /* Read FIDVID_STATUS */ msr_t msr; msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid %08x%08x\n", msr.hi, msr.lo); } enable_fid_change(); enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn); init_fidvid_bsp(bsp_apicid); // show final fid and vid { msr_t msr; msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid %08x%08x\n", msr.hi, msr.lo); } } else { printk(BIOS_DEBUG, "Changing FIDVID not supported\n"); } #endif needs_reset |= optimize_link_coherent_ht(); needs_reset |= optimize_link_incoherent_ht(sysinfo); if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn); } enable_smbus(); int i; for(i = 0; i < 2; i++) { activate_spd_rom(&sysinfo->ctrl[i]); } for(i = RC0; i <= RC1; i<<=1) { change_i2c_mux(i); } //dump_spd_registers(&sysinfo->ctrl[0]); //dump_spd_registers(&sysinfo->ctrl[1]); //dump_smbus_registers(); allow_all_aps_stop(bsp_apicid); //It's the time to set ctrl now; fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); memreset_setup(); #if CONFIG_SET_FIDVID init_timer(); // Need to use TMICT to synchronize FID/VID #endif sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); //dump_pci_devices(); post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { DIMM0, DIMM2, 0, 0, DIMM1, DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 DIMM4, DIMM6, 0, 0, DIMM5, DIMM7, 0, 0, #endif }; int needs_reset; unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); // post_code(0x32); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_s2891_resource_map(); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); dump_pci_device(PCI_DEV(0, 0x19, 0)); #endif needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); #if 0 dump_spd_registers(&cpu[0]); dump_smbus_registers(); #endif memreset_setup(); sdram_initialize(nodes, ctrl); #if 0 print_pci_devices(); dump_pci_devices(); #endif post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { DIMM0, 0, 0, 0, DIMM1, 0, 0, 0, }; int needs_reset; unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; if (!cpu_init_detectedx && boot_cpu()) { /* Nothing special needs to be done to find bus 0 */ /* Allow the HT devices to be found */ enumerate_ht_chain(); sio_setup(); } if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); // post_code(0x32); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); #if 0 dump_pci_device(PCI_DEV(0, 0x18, 0)); #endif needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #if CONFIG_SET_FIDVID /* Check to see if processor is capable of changing FIDVID */ /* otherwise it will throw a GP# when reading FIDVID_STATUS */ if ((cpuid_edx(0x80000007) & 0x6) == 0x6) { msr_t msr; /* Read FIDVID_STATUS */ msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "begin msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); enable_fid_change(); init_fidvid_bsp(bsp_apicid); msr = rdmsr(0xc0010042); printk(BIOS_DEBUG, "end msr fid, vid: hi=0x%x, lo=0x%x\n", msr.hi, msr.lo); } #endif needs_reset |= ht_setup_chains_x(); needs_reset |= ck804_early_setup_x(); if (needs_reset) { printk(BIOS_INFO, "ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); #if 0 dump_spd_registers(&cpu[0]); dump_smbus_registers(); #endif memreset_setup(); sdram_initialize(nodes, ctrl); #if 0 print_pci_devices(); dump_pci_devices(); #endif post_cache_as_ram(); }
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { static const uint16_t spd_addr [] = { RC0|DIMM0, RC0|DIMM2, 0, 0, RC0|DIMM1, RC0|DIMM3, 0, 0, #if CONFIG_MAX_PHYSICAL_CPUS > 1 RC1|DIMM0, RC1|DIMM2, 0, 0, RC1|DIMM1, RC1|DIMM3, 0, 0, #endif #if CONFIG_MAX_PHYSICAL_CPUS > 2 RC2|DIMM0, RC2|DIMM2, 0, 0, RC2|DIMM1, RC2|DIMM3, 0, 0, RC3|DIMM0, RC3|DIMM2, 0, 0, RC3|DIMM1, RC3|DIMM3, 0, 0, #endif }; int needs_reset; unsigned bsp_apicid = 0, nodes; struct mem_controller ctrl[8]; if (bist == 0) bsp_apicid = init_cpus(cpu_init_detectedx); w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); console_init(); /* Halt if there was a built in self test failure */ report_bist_failure(bist); setup_s4882_resource_map(); needs_reset = setup_coherent_ht_domain(); wait_all_core0_started(); #if CONFIG_LOGICAL_CPUS==1 // It is said that we should start core1 after all core0 launched start_other_cores(); wait_all_other_cores_started(bsp_apicid); #endif // automatically set that for you, but you might meet tight space needs_reset |= ht_setup_chains_x(); if (needs_reset) { print_info("ht reset -\n"); soft_reset(); } allow_all_aps_stop(bsp_apicid); nodes = get_nodes(); //It's the time to set ctrl now; fill_mem_ctrl(nodes, ctrl, spd_addr); enable_smbus(); memreset_setup(); sdram_initialize(nodes, ctrl); post_cache_as_ram(); }