void set_pmu_rsthold(void) { uint32_t rstnhold_cofig0; uint32_t rstnhold_cofig1; slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0); slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1); rstnhold_cofig0 = BIT_WITH_WMSK(PRESETN_NOC_PMU_HOLD) | BIT_WITH_WMSK(PRESETN_INTMEM_PMU_HOLD) | BIT_WITH_WMSK(HRESETN_CM0S_PMU_HOLD) | BIT_WITH_WMSK(HRESETN_CM0S_NOC_PMU_HOLD) | BIT_WITH_WMSK(DRESETN_CM0S_PMU_HOLD) | BIT_WITH_WMSK(POESETN_CM0S_PMU_HOLD) | BIT_WITH_WMSK(PRESETN_TIMER_PMU_0_1_HOLD) | BIT_WITH_WMSK(RESETN_TIMER_PMU_0_HOLD) | BIT_WITH_WMSK(RESETN_TIMER_PMU_1_HOLD) | BIT_WITH_WMSK(PRESETN_UART_M0_PMU_HOLD) | BIT_WITH_WMSK(RESETN_UART_M0_PMU_HOLD) | BIT_WITH_WMSK(PRESETN_WDT_PMU_HOLD); rstnhold_cofig1 = BIT_WITH_WMSK(PRESETN_RKPWM_PMU_HOLD) | BIT_WITH_WMSK(PRESETN_PMUGRF_HOLD) | BIT_WITH_WMSK(PRESETN_SGRF_HOLD) | BIT_WITH_WMSK(PRESETN_GPIO0_HOLD) | BIT_WITH_WMSK(PRESETN_GPIO1_HOLD) | BIT_WITH_WMSK(PRESETN_CRU_PMU_HOLD) | BIT_WITH_WMSK(PRESETN_PVTM_PMU_HOLD); mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0, rstnhold_cofig0); mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1, rstnhold_cofig1); }
static uint32_t get_table_index(void) { uint32_t product; uint32_t cut_ver; uint32_t index; product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK; cut_ver = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK; switch (product) { case RCAR_PRODUCT_H3: if (cut_ver == RCAR_CUT_VER10) index = OLD_API_TABLE1; else if (cut_ver == RCAR_CUT_VER11) index = OLD_API_TABLE1; else if (cut_ver == RCAR_CUT_VER20) index = OLD_API_TABLE2; else /* Later than H3 Ver.2.0 */ index = NEW_API_TABLE; break; case RCAR_PRODUCT_M3: if (cut_ver == RCAR_CUT_VER10) index = OLD_API_TABLE3; else /* M3 Ver.1.1 or later */ index = NEW_API_TABLE; break; default: index = NEW_API_TABLE; break; } return index; }
static int poplar_pwr_domain_on(u_register_t mpidr) { unsigned int cpu = plat_core_pos_by_mpidr(mpidr); unsigned int regval, regval_bak; /* Select 400MHz before start slave cores */ regval_bak = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP)); mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), 0x206); mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), 0x606); /* Clear the slave cpu arm_por_srst_req reset */ regval = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST)); regval &= ~(1 << (cpu + CPU_REG_COREPO_SRST)); mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST), regval); /* Clear the slave cpu reset */ regval = mmio_read_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST)); regval &= ~(1 << (cpu + CPU_REG_CORE_SRST)); mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_RST), regval); /* Restore cpu frequency */ regval = regval_bak & (~(1 << REG_CPU_LP_CPU_SW_BEGIN)); mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), regval); mmio_write_32((uintptr_t)(REG_BASE_CRG + REG_CPU_LP), regval_bak); return PSCI_E_SUCCESS; }
static void init_mmc1_pll(void) { uint32_t data; /* select SYSPLL as the source of MMC1 */ /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */ mmio_write_32(PERI_SC_CLK_SEL0, 1 << 11 | 1 << 27); do { data = mmio_read_32(PERI_SC_CLK_SEL0); } while (!(data & (1 << 11))); /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */ mmio_write_32(PERI_SC_CLK_SEL0, 1 << 30); do { data = mmio_read_32(PERI_SC_CLK_SEL0); } while (data & (1 << 14)); mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 1)); do { data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); } while (!(data & (1 << 1))); data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); data |= 1 << 2; mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); do { /* 1.2GHz / 50 = 24MHz */ mmio_write_32(PERI_SC_CLKCFG8BIT2, 0x31 | (1 << 7)); data = mmio_read_32(PERI_SC_CLKCFG8BIT2); } while ((data & 0x31) != 0x31); }
void spm_kick_im_to_fetch(const struct pcm_desc *pcmdesc) { unsigned int ptr = 0, len, con0; ptr = (unsigned int)(unsigned long)(pcmdesc->base); len = pcmdesc->size - 1; if (mmio_read_32(SPM_PCM_IM_PTR) != ptr || mmio_read_32(SPM_PCM_IM_LEN) != len || pcmdesc->sess > 2) { mmio_write_32(SPM_PCM_IM_PTR, ptr); mmio_write_32(SPM_PCM_IM_LEN, len); } else { mmio_setbits_32(SPM_PCM_CON1, CON1_CFG_KEY | CON1_IM_SLAVE); } /* kick IM to fetch (only toggle IM_KICK) */ con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_IM_KICK); mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); /* kick IM to fetch (only toggle PCM_KICK) */ con0 = mmio_read_32(SPM_PCM_CON0) & ~(CON0_IM_KICK | CON0_PCM_KICK); mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY | CON0_PCM_KICK); mmio_write_32(SPM_PCM_CON0, con0 | CON0_CFG_KEY); }
static void zynqmp_nopmu_pwr_domain_suspend(const psci_power_state_t *target_state) { uint32_t r; unsigned int cpu_id = plat_my_core_pos(); for (size_t i = 0; i <= PLAT_MAX_PWR_LVL; i++) VERBOSE("%s: target_state->pwr_domain_state[%lu]=%x\n", __func__, i, target_state->pwr_domain_state[i]); /* set power down request */ r = mmio_read_32(APU_PWRCTL); r |= (1 << cpu_id); mmio_write_32(APU_PWRCTL, r); /* program RVBAR */ mmio_write_32(APU_RVBAR_L_0 + (cpu_id << 3), zynqmp_sec_entry); mmio_write_32(APU_RVBAR_H_0 + (cpu_id << 3), zynqmp_sec_entry >> 32); /* clear VINITHI */ r = mmio_read_32(APU_CONFIG_0); r &= ~(1 << APU_CONFIG_0_VINITHI_SHIFT << cpu_id); mmio_write_32(APU_CONFIG_0, r); /* enable power up on IRQ */ mmio_write_32(PMU_GLOBAL_REQ_PWRUP_EN, 1 << cpu_id); }
void spm_kick_pcm_to_run(struct pwr_ctrl *pwrctrl) { unsigned int con1; con1 = mmio_read_32(SPM_PCM_CON1) & ~(CON1_PCM_WDT_WAKE_MODE | CON1_PCM_WDT_EN); mmio_write_32(SPM_PCM_CON1, CON1_CFG_KEY | con1); if (mmio_read_32(SPM_PCM_TIMER_VAL) > PCM_TIMER_MAX) mmio_write_32(SPM_PCM_TIMER_VAL, PCM_TIMER_MAX); mmio_write_32(SPM_PCM_WDT_TIMER_VAL, mmio_read_32(SPM_PCM_TIMER_VAL) + PCM_WDT_TIMEOUT); mmio_write_32(SPM_PCM_CON1, con1 | CON1_CFG_KEY | CON1_PCM_WDT_EN); mmio_write_32(SPM_PCM_PASR_DPD_0, 0); mmio_write_32(SPM_PCM_MAS_PAUSE_MASK, 0xffffffff); mmio_write_32(SPM_PCM_REG_DATA_INI, 0); mmio_clrbits_32(SPM_CLK_CON, CC_DISABLE_DORM_PWR); mmio_write_32(SPM_PCM_FLAGS, pwrctrl->pcm_flags); mmio_clrsetbits_32(SPM_CLK_CON, CC_LOCK_INFRA_DCM, (pwrctrl->infra_dcm_lock ? CC_LOCK_INFRA_DCM : 0)); mmio_write_32(SPM_PCM_PWR_IO_EN, (pwrctrl->r0_ctrl_en ? PCM_PWRIO_EN_R0 : 0) | (pwrctrl->r7_ctrl_en ? PCM_PWRIO_EN_R7 : 0)); }
static void init_ddr(int freq) { unsigned int data; int ret; data = mmio_read_32((0xf7032000 + 0x030)); data |= 1; mmio_write_32((0xf7032000 + 0x030), data); data = mmio_read_32((0xf7032000 + 0x010)); data |= 1; mmio_write_32((0xf7032000 + 0x010), data); udelay(100); do { data = mmio_read_32((0xf7032000 + 0x030)); data &= 3 << 28; } while (data != (3 << 28)); do { data = mmio_read_32((0xf7032000 + 0x010)); data &= 3 << 28; } while (data != (3 << 28)); ret = lpddr3_freq_init(freq); if (ret) return; }
static void hikey960_ufs_reset(void) { unsigned int data, mask; mmio_write_32(CRG_PERDIS7_REG, 1 << 14); mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); do { data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); } while (data & BIT_SYSCTRL_REF_CLOCK_EN); /* use abb clk */ mmio_clrbits_32(UFS_SYS_UFS_SYSCTRL_REG, BIT_UFS_REFCLK_SRC_SE1); mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_REFCLK_ISO_EN); mmio_write_32(PCTRL_PERI_CTRL3_REG, (1 << 0) | (1 << 16)); mdelay(1); mmio_write_32(CRG_PEREN7_REG, 1 << 14); mmio_setbits_32(UFS_SYS_PHY_CLK_CTRL_REG, BIT_SYSCTRL_REF_CLOCK_EN); mmio_write_32(CRG_PERRSTEN3_REG, PERI_UFS_BIT); do { data = mmio_read_32(CRG_PERRSTSTAT3_REG); } while ((data & PERI_UFS_BIT) == 0); mmio_setbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_MTCMOS_EN); mdelay(1); mmio_setbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_PWR_READY); mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, MASK_UFS_DEVICE_RESET); /* clear SC_DIV_UFS_PERIBUS */ mask = SC_DIV_UFS_PERIBUS << 16; mmio_write_32(CRG_CLKDIV17_REG, mask); /* set SC_DIV_UFSPHY_CFG(3) */ mask = SC_DIV_UFSPHY_CFG_MASK << 16; data = SC_DIV_UFSPHY_CFG(3); mmio_write_32(CRG_CLKDIV16_REG, mask | data); data = mmio_read_32(UFS_SYS_PHY_CLK_CTRL_REG); data &= ~MASK_SYSCTRL_CFG_CLOCK_FREQ; data |= 0x39; mmio_write_32(UFS_SYS_PHY_CLK_CTRL_REG, data); mmio_clrbits_32(UFS_SYS_PHY_CLK_CTRL_REG, MASK_SYSCTRL_REF_CLOCK_SEL); mmio_setbits_32(UFS_SYS_CLOCK_GATE_BYPASS_REG, MASK_UFS_CLK_GATE_BYPASS); mmio_setbits_32(UFS_SYS_UFS_SYSCTRL_REG, MASK_UFS_SYSCTRL_BYPASS); mmio_setbits_32(UFS_SYS_PSW_CLK_CTRL_REG, BIT_SYSCTRL_PSW_CLK_EN); mmio_clrbits_32(UFS_SYS_PSW_POWER_CTRL_REG, BIT_UFS_PSW_ISO_CTRL); mmio_clrbits_32(UFS_SYS_PHY_ISO_EN_REG, BIT_UFS_PHY_ISO_CTRL); mmio_clrbits_32(UFS_SYS_HC_LP_CTRL_REG, BIT_SYSCTRL_LP_ISOL_EN); mmio_write_32(CRG_PERRSTDIS3_REG, PERI_ARST_UFS_BIT); mmio_setbits_32(UFS_SYS_RESET_CTRL_EN_REG, BIT_SYSCTRL_LP_RESET_N); mdelay(1); mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, MASK_UFS_DEVICE_RESET | BIT_UFS_DEVICE_RESET); mdelay(20); mmio_write_32(UFS_SYS_UFS_DEVICE_RESET_CTRL_REG, 0x03300330); mmio_write_32(CRG_PERRSTDIS3_REG, PERI_UFS_BIT); do { data = mmio_read_32(CRG_PERRSTSTAT3_REG); } while (data & PERI_UFS_BIT); }
static void init_mmc0_pll(void) { unsigned int data; data = hi6553_read_8(0x084); data |= 0x7; hi6553_write_8(0x084, data); /* select SYSPLL as the source of MMC0 */ /* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */ mmio_write_32(PERI_SC_CLK_SEL0, 1 << 5 | 1 << 21); do { data = mmio_read_32(PERI_SC_CLK_SEL0); } while (!(data & (1 << 5))); /* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */ mmio_write_32(PERI_SC_CLK_SEL0, 1 << 29); do { data = mmio_read_32(PERI_SC_CLK_SEL0); } while (data & (1 << 13)); mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 0)); do { data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0); } while (!(data & (1 << 0))); data = mmio_read_32(PERI_SC_PERIPH_CLKEN12); data |= 1 << 1; mmio_write_32(PERI_SC_PERIPH_CLKEN12, data); do { mmio_write_32(PERI_SC_CLKCFG8BIT1, (1 << 7) | 0xb); data = mmio_read_32(PERI_SC_CLKCFG8BIT1); } while ((data & 0xb) != 0xb); }
int mailbox_read_response(int job_id, uint32_t *response) { int rin = 0; int rout = 0; int response_length = 0; int resp = 0; int total_resp_len = 0; int timeout = 100000; mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_TO_SDM, 1); while (mmio_read_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM) != 1) { if (timeout-- < 0) return MBOX_NO_RESPONSE; } mmio_write_32(MBOX_OFFSET + MBOX_DOORBELL_FROM_SDM, 0); rin = mmio_read_32(MBOX_OFFSET + MBOX_RIN); rout = mmio_read_32(MBOX_OFFSET + MBOX_ROUT); while (rout != rin) { resp = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + ((rout++)*4)); rout %= MBOX_RESP_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); if (MBOX_RESP_CLIENT_ID(resp) != MBOX_ATF_CLIENT_ID || MBOX_RESP_JOB_ID(resp) != job_id) { return MBOX_WRONG_ID; } if (MBOX_RESP_ERR(resp) > 0) { INFO("Error in response: %x\n", resp); return -resp; } response_length = MBOX_RESP_LEN(resp); while (response_length) { response_length--; resp = mmio_read_32(MBOX_OFFSET + MBOX_RESP_BUFFER + (rout)*4); if (response) { *(response + total_resp_len) = resp; total_resp_len++; } rout++; rout %= MBOX_RESP_BUFFER_SIZE; mmio_write_32(MBOX_OFFSET + MBOX_ROUT, rout); } return total_resp_len; } return MBOX_NO_RESPONSE; }
mstpcr_write(uint32_t mstpcr, uint32_t mstpsr, uint32_t target_bit) { uint32_t reg; reg = mmio_read_32(mstpcr); reg &= ~target_bit; cpg_write(mstpcr, reg); while ((mmio_read_32(mstpsr) & target_bit) != 0U) { } }
static void init_ddrc_qos(void) { unsigned int port, data; mmio_write_32((0xf7124000 + 0x088), 1); port = 0; mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x1210); mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x11111111); mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x11111111); mmio_write_32((0xf7120000 + 0x400 + 0 * 0x10), 0x001d0007); for (port = 3; port <= 4; port++) { mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x1210); mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x77777777); mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x77777777); } port = 1; mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x30000); mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x1234567); mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x1234567); mmio_write_32((0xf7124000 + 0x1f0), 0); mmio_write_32((0xf7124000 + 0x0bc), 0x3020100); mmio_write_32((0xf7124000 + 0x0d0), 0x3020100); mmio_write_32((0xf7124000 + 0x1f4), 0x01000100); mmio_write_32((0xf7124000 + 0x08c + 0 * 4), 0xd0670402); mmio_write_32((0xf7124000 + 0x068 + 0 * 4), 0x31); mmio_write_32((0xf7124000 + 0x000), 0x7); data = mmio_read_32((0xf7124000 + 0x09c)); data &= ~0xff0000; data |= 0x400000; mmio_write_32((0xf7124000 + 0x09c), data); data = mmio_read_32((0xf7124000 + 0x0ac)); data &= ~0xff0000; data |= 0x400000; mmio_write_32((0xf7124000 + 0x0ac), data); port = 2; mmio_write_32((0xf7120000 + 0x200 + port * 0x10), 0x30000); mmio_write_32((0xf7120000 + 0x204 + port * 0x10), 0x1234567); mmio_write_32((0xf7120000 + 0x208 + port * 0x10), 0x1234567); mmio_write_32((0xf7124000 + 0x09c), 0xff7fff); mmio_write_32((0xf7124000 + 0x0a0), 0xff); mmio_write_32((0xf7124000 + 0x0ac), 0xff7fff); mmio_write_32((0xf7124000 + 0x0b0), 0xff); mmio_write_32((0xf7124000 + 0x0bc), 0x3020100); mmio_write_32((0xf7124000 + 0x0d0), 0x3020100); }
static int uniphier_emmc_send_cmd(uintptr_t host_base, struct uniphier_mmc_cmd *cmd) { uint32_t mode = 0; uint32_t end_bit; uint32_t stat, flags, dma_addr; mmio_write_32(host_base + SDHCI_INT_STATUS, -1); mmio_write_32(host_base + SDHCI_SIGNAL_ENABLE, 0); mmio_write_32(host_base + SDHCI_ARGUMENT, cmd->cmdarg); if (cmd->is_data) mode = SDHCI_TRNS_DMA | SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_ACMD12 | SDHCI_TRNS_READ | SDHCI_TRNS_MULTI; mmio_write_16(host_base + SDHCI_TRANSFER_MODE, mode); if (!(cmd->resp_type & MMC_RSP_PRESENT)) flags = SDHCI_CMD_RESP_NONE; else if (cmd->resp_type & MMC_RSP_136) flags = SDHCI_CMD_RESP_LONG; else if (cmd->resp_type & MMC_RSP_BUSY) flags = SDHCI_CMD_RESP_SHORT_BUSY; else flags = SDHCI_CMD_RESP_SHORT; if (cmd->resp_type & MMC_RSP_CRC) flags |= SDHCI_CMD_CRC; if (cmd->resp_type & MMC_RSP_OPCODE) flags |= SDHCI_CMD_INDEX; if (cmd->is_data) flags |= SDHCI_CMD_DATA; if (cmd->resp_type & MMC_RSP_BUSY || cmd->is_data) end_bit = SDHCI_INT_DATA_END; else end_bit = SDHCI_INT_RESPONSE; mmio_write_16(host_base + SDHCI_COMMAND, SDHCI_MAKE_CMD(cmd->cmdidx, flags)); do { stat = mmio_read_32(host_base + SDHCI_INT_STATUS); if (stat & SDHCI_INT_ERROR) return -EIO; if (stat & SDHCI_INT_DMA_END) { mmio_write_32(host_base + SDHCI_INT_STATUS, stat); dma_addr = mmio_read_32(host_base + SDHCI_DMA_ADDRESS); mmio_write_32(host_base + SDHCI_DMA_ADDRESS, dma_addr); } } while (!(stat & end_bit)); return 0; }
static void plls_suspend(uint32_t pll_id) { plls_con[pll_id][0] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 0)); plls_con[pll_id][1] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 1)); plls_con[pll_id][2] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 2)); plls_con[pll_id][3] = mmio_read_32(CRU_BASE + PLL_CONS((pll_id), 3)); mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_SLOW_BITS); mmio_write_32(CRU_BASE + PLL_CONS((pll_id), 3), PLL_BYPASS); }
void spm_init_pcm_register(void) { mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL0)); mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R0); mmio_write_32(SPM_PCM_PWR_IO_EN, 0); mmio_write_32(SPM_PCM_REG_DATA_INI, mmio_read_32(SPM_POWER_ON_VAL1)); mmio_write_32(SPM_PCM_PWR_IO_EN, PCM_RF_SYNC_R7); mmio_write_32(SPM_PCM_PWR_IO_EN, 0); }
void rcar_swdt_init(void) { uint32_t rmsk, sr; #if (RCAR_LSI != RCAR_E3) uint32_t reg, val, product_cut, chk_data; reg = mmio_read_32(RCAR_PRR); product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); reg = mmio_read_32(RCAR_MODEMR); chk_data = reg & CHECK_MD13_MD14; #endif /* stop watchdog */ if (mmio_read_32(SWDT_WTCSRA) & SWDT_ENABLE) mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE); mmio_write_32(SWDT_WTCSRA, WTCSRA_UPPER_BYTE | WTCSRA_WOVFE | WTCSRA_CKS_DIV16); #if (RCAR_LSI == RCAR_E3) mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k); #else val = WTCNT_UPPER_BYTE; switch (chk_data) { case MD14_MD13_TYPE_0: case MD14_MD13_TYPE_2: val |= WTCNT_COUNT_8p13k; break; case MD14_MD13_TYPE_1: val |= WTCNT_COUNT_8p22k; break; case MD14_MD13_TYPE_3: val |= product_cut == (RCAR_PRODUCT_H3 | RCAR_CUT_VER10) ? WTCNT_COUNT_8p13k_H3VER10 : WTCNT_COUNT_8p13k; break; default: ERROR("MODEMR ERROR value = %x\n", chk_data); panic(); break; } mmio_write_32(SWDT_WTCNT, val); #endif rmsk = mmio_read_32(RST_WDTRSTCR) & WDTRSTCR_MASK_ALL; rmsk |= SWDT_RSTMSK | WDTRSTCR_UPPER_BYTE; mmio_write_32(RST_WDTRSTCR, rmsk); while ((mmio_read_8(SWDT_WTCSRA) & WTCSRA_WRFLG) != 0U) ; /* Start the System WatchDog Timer */ sr = mmio_read_32(SWDT_WTCSRA) & WTCSRA_MASK_ALL; mmio_write_32(SWDT_WTCSRA, (WTCSRA_UPPER_BYTE | sr | SWDT_ENABLE)); }
void clk_gate_con_save(void) { uint32_t i = 0; for (i = 0; i < PMUCRU_GATE_COUNT; i++) slp_data.pmucru_gate_con[i] = mmio_read_32(PMUCRU_BASE + PMUCRU_GATE_CON(i)); for (i = 0; i < CRU_GATE_COUNT; i++) slp_data.cru_gate_con[i] = mmio_read_32(CRU_BASE + CRU_GATE_CON(i)); }
static void plat_save_el3_dormant_data() { struct _el3_dormant_data *p = &el3_dormant_data[0]; p->mp0_l2actlr_el1 = read_l2actlr(); p->mp0_l2ectlr_el1 = read_l2ectlr(); //backup L2RSTDISABLE and set as "not disable L2 reset" p->mp0_l2rstdisable = mmio_read_32(MP0_CA7L_CACHE_CONFIG); mmio_write_32(MP0_CA7L_CACHE_CONFIG, mmio_read_32(MP0_CA7L_CACHE_CONFIG) & ~L2RSTDISABLE); }
/******************************************************************************* * This function tests the DDR address bus wiring. * This is inspired from the Data Bus Test algorithm written by Michael Barr * in "Programming Embedded Systems in C and C++" book. * resources.oreilly.com/examples/9781565923546/blob/master/Chapter6/ * File: memtest.c - This source code belongs to Public Domain. * Returns 0 if success, and address value else. ******************************************************************************/ static uint32_t ddr_test_addr_bus(void) { uint64_t addressmask = (ddr_priv_data.info.size - 1U); uint64_t offset; uint64_t testoffset = 0; /* Write the default pattern at each of the power-of-two offsets. */ for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; offset <<= 1) { mmio_write_32(STM32MP_DDR_BASE + (uint32_t)offset, DDR_PATTERN); } /* Check for address bits stuck high. */ mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_ANTIPATTERN); for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; offset <<= 1) { if (mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) != DDR_PATTERN) { return (uint32_t)(STM32MP_DDR_BASE + offset); } } mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN); /* Check for address bits stuck low or shorted. */ for (testoffset = sizeof(uint32_t); (testoffset & addressmask) != 0U; testoffset <<= 1) { mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_ANTIPATTERN); if (mmio_read_32(STM32MP_DDR_BASE) != DDR_PATTERN) { return STM32MP_DDR_BASE; } for (offset = sizeof(uint32_t); (offset & addressmask) != 0U; offset <<= 1) { if ((mmio_read_32(STM32MP_DDR_BASE + (uint32_t)offset) != DDR_PATTERN) && (offset != testoffset)) { return (uint32_t)(STM32MP_DDR_BASE + offset); } } mmio_write_32(STM32MP_DDR_BASE + (uint32_t)testoffset, DDR_PATTERN); } return 0; }
static uint32_t ddr_get_phy_pll_freq(void) { uint32_t ret = 0; uint32_t fb_div, pre_div; fb_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEC); fb_div |= (mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGED) & 0x1) << 8; pre_div = mmio_read_32(DDR_PHY_BASE + DDR_PHY_REGEE) & 0xff; ret = 2 * 24 * fb_div / (4 * pre_div); return ret; }
static void pll_suspend_prepare(uint32_t pll_id) { int i; if (pll_id == PPLL_ID) for (i = 0; i < PLL_CON_COUNT; i++) slp_data.plls_con[pll_id][i] = mmio_read_32(PMUCRU_BASE + PMUCRU_PPLL_CON(i)); else for (i = 0; i < PLL_CON_COUNT; i++) slp_data.plls_con[pll_id][i] = mmio_read_32(CRU_BASE + CRU_PLL_CON(pll_id, i)); }
void spm_get_wakeup_status(struct wake_status *wakesta) { wakesta->assert_pc = mmio_read_32(SPM_PCM_REG_DATA_INI); wakesta->r12 = mmio_read_32(SPM_PCM_REG12_DATA); wakesta->raw_sta = mmio_read_32(SPM_SLEEP_ISR_RAW_STA); wakesta->wake_misc = mmio_read_32(SPM_SLEEP_WAKEUP_MISC); wakesta->timer_out = mmio_read_32(SPM_PCM_TIMER_OUT); wakesta->r13 = mmio_read_32(SPM_PCM_REG13_DATA); wakesta->idle_sta = mmio_read_32(SPM_SLEEP_SUBSYS_IDLE_STA); wakesta->debug_flag = mmio_read_32(SPM_PCM_PASR_DPD_3); wakesta->event_reg = mmio_read_32(SPM_PCM_EVENT_REG_STA); wakesta->isr = mmio_read_32(SPM_SLEEP_ISR_STATUS); }
static void tegra_se_disable_clocks(void) { uint32_t val = 0; /* Disable entropy clock */ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_W); val &= ~ENTROPY_CLK_ENB_BIT; mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_W, val); /* Disable SE clock */ val = mmio_read_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V); val &= ~SE_CLK_ENB_BIT; mmio_write_32(TEGRA_CAR_RESET_BASE + TEGRA_CLK_OUT_ENB_V, val); }
/******************************************************************************* * Function that returns the system counter frequency ******************************************************************************/ unsigned int plat_get_syscnt_freq2(void) { uint32_t val; val = mmio_read_32(GXBB_SYS_CPU_CFG7); val &= 0xFDFFFFFF; mmio_write_32(GXBB_SYS_CPU_CFG7, val); val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL); val &= 0xFFFFFE00; mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val); return GXBB_OSC24M_CLK_IN_HZ; }
/** * ipi_mb_enquire_status() - Enquire IPI mailbox status * * @local - local IPI ID * @remote - remote IPI ID * * return - 0 idle, positive value for pending sending or receiving, * negative value for errors */ int ipi_mb_enquire_status(uint32_t local, uint32_t remote) { int ret = 0; uint32_t status; status = mmio_read_32(IPI_REG_BASE(local) + IPI_OBR_OFFSET); if (status & IPI_BIT_MASK(remote)) ret |= IPI_MB_STATUS_SEND_PENDING; status = mmio_read_32(IPI_REG_BASE(local) + IPI_ISR_OFFSET); if (status & IPI_BIT_MASK(remote)) ret |= IPI_MB_STATUS_RECV_PENDING; return ret; }
void hisi_pwrc_set_cluster_wfi(unsigned int cluster) { unsigned int reg = 0; if (cluster == 0) { reg = mmio_read_32(ACPU_SC_SNOOP_PWD); reg |= PD_DETECT_START0; mmio_write_32(ACPU_SC_SNOOP_PWD, reg); } else if (cluster == 1) { reg = mmio_read_32(ACPU_SC_SNOOP_PWD); reg |= PD_DETECT_START1; mmio_write_32(ACPU_SC_SNOOP_PWD, reg); } }
void hisi_pwrc_enable_debug(unsigned int core, unsigned int cluster) { unsigned int val, enable; enable = 1U << (core + PDBGUP_CLUSTER1_SHIFT * cluster); /* Enable debug module */ val = mmio_read_32(ACPU_SC_PDBGUP_MBIST); mmio_write_32(ACPU_SC_PDBGUP_MBIST, val | enable); do { /* RAW barrier */ val = mmio_read_32(ACPU_SC_PDBGUP_MBIST); } while (!(val & enable)); }
void spm_mcdi_wakeup_all_cores(void) { if (is_mcdi_ready() == 0) return; spm_mcdi_cpu_wake_up_event(1, 1); while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_ALL_CORE_AWAKE) ; spm_mcdi_cpu_wake_up_event(1, 0); while (mmio_read_32(SPM_PCM_REG5_DATA) != PCM_MCDI_OFFLOADED) ; spm_clean_after_wakeup(); clear_all_ready(); }
static void isps_control_clock(int flag) { unsigned int ret; /* flag: 0 -- disable clock, 1 -- enable clock */ if (flag) { ret = mmio_read_32(0xe8420364); ret |= 1; mmio_write_32(0xe8420364, ret); } else { ret = mmio_read_32(0xe8420364); ret &= ~1; mmio_write_32(0xe8420364, ret); } }