static void mt76x2_phy_channel_calibrate(struct mt76x02_dev *dev, bool mac_stopped) { struct ieee80211_channel *chan = dev->mt76.chandef.chan; bool is_5ghz = chan->band == NL80211_BAND_5GHZ; if (dev->cal.channel_cal_done) return; if (mt76x2_channel_silent(dev)) return; if (!dev->cal.tssi_cal_done) mt76x2_phy_tssi_init_cal(dev); if (!mac_stopped) mt76x2_mac_stop(dev, false); if (is_5ghz) mt76x02_mcu_calibrate(dev, MCU_CAL_LC, 0); mt76x02_mcu_calibrate(dev, MCU_CAL_TX_LOFT, is_5ghz); mt76x02_mcu_calibrate(dev, MCU_CAL_TXIQ, is_5ghz); mt76x02_mcu_calibrate(dev, MCU_CAL_RXIQC_FI, is_5ghz); mt76x02_mcu_calibrate(dev, MCU_CAL_TEMP_SENSOR, 0); mt76x02_mcu_calibrate(dev, MCU_CAL_TX_SHAPING, 0); if (!mac_stopped) mt76x2_mac_resume(dev); mt76x2_apply_gain_adj(dev); dev->cal.channel_cal_done = true; }
void mt76x2_stop_hardware(struct mt76x2_dev *dev) { cancel_delayed_work_sync(&dev->cal_work); cancel_delayed_work_sync(&dev->mac_work); mt76x2_mcu_set_radio_state(dev, false); mt76x2_mac_stop(dev, false); }
static int mt76x2_init_hardware(struct mt76x02_dev *dev) { int ret; mt76x02_dma_disable(dev); mt76x2_reset_wlan(dev, true); mt76x2_power_on(dev); ret = mt76x2_eeprom_init(dev); if (ret) return ret; ret = mt76x2_mac_reset(dev, true); if (ret) return ret; dev->mt76.rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); ret = mt76x02_dma_init(dev); if (ret) return ret; set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state); ret = mt76x2_mac_start(dev); if (ret) return ret; ret = mt76x2_mcu_init(dev); if (ret) return ret; mt76x2_mac_stop(dev, false); return 0; }
static int mt76x2_set_channel(struct mt76x2_dev *dev, struct cfg80211_chan_def *chandef) { int ret; cancel_delayed_work_sync(&dev->cal_work); set_bit(MT76_RESET, &dev->mt76.state); mt76_set_channel(&dev->mt76); tasklet_disable(&dev->pre_tbtt_tasklet); tasklet_disable(&dev->dfs_pd.dfs_tasklet); mt76x2_mac_stop(dev, true); ret = mt76x2_phy_set_channel(dev, chandef); /* channel cycle counters read-and-clear */ mt76_rr(dev, MT_CH_IDLE); mt76_rr(dev, MT_CH_BUSY); mt76x2_dfs_init_params(dev); mt76x2_mac_resume(dev); tasklet_enable(&dev->dfs_pd.dfs_tasklet); tasklet_enable(&dev->pre_tbtt_tasklet); clear_bit(MT76_RESET, &dev->mt76.state); mt76_txq_schedule_all(&dev->mt76); return ret; }
static int mt76x2u_set_channel(struct mt76x02_dev *dev, struct cfg80211_chan_def *chandef) { int err; cancel_delayed_work_sync(&dev->cal_work); set_bit(MT76_RESET, &dev->mt76.state); mt76_set_channel(&dev->mt76); mt76_clear(dev, MT_TXOP_CTRL_CFG, BIT(20)); mt76_clear(dev, MT_TXOP_HLDR_ET, BIT(1)); mt76x2_mac_stop(dev, false); err = mt76x2u_phy_set_channel(dev, chandef); mt76x2u_mac_resume(dev); clear_bit(MT76_RESET, &dev->mt76.state); mt76_txq_schedule_all(&dev->mt76); return err; }
int mt76x2_init_hardware(struct mt76x2_dev *dev) { static const u16 beacon_offsets[16] = { /* 1024 byte per beacon */ 0xc000, 0xc400, 0xc800, 0xcc00, 0xd000, 0xd400, 0xd800, 0xdc00, /* BSS idx 8-15 not used for beacons */ 0xc000, 0xc000, 0xc000, 0xc000, 0xc000, 0xc000, 0xc000, 0xc000, }; u32 val; int ret; dev->beacon_offsets = beacon_offsets; tasklet_init(&dev->pre_tbtt_tasklet, mt76x2_pre_tbtt_tasklet, (unsigned long) dev); dev->chainmask = 0x202; dev->slottime = 9; val = mt76_rr(dev, MT_WPDMA_GLO_CFG); val &= MT_WPDMA_GLO_CFG_DMA_BURST_SIZE | MT_WPDMA_GLO_CFG_BIG_ENDIAN | MT_WPDMA_GLO_CFG_HDR_SEG_LEN; val |= MT_WPDMA_GLO_CFG_TX_WRITEBACK_DONE; mt76_wr(dev, MT_WPDMA_GLO_CFG, val); mt76x2_reset_wlan(dev, true); mt76x2_power_on(dev); ret = mt76x2_eeprom_init(dev); if (ret) return ret; ret = mt76x2_mac_reset(dev, true); if (ret) return ret; ret = mt76x2_dma_init(dev); if (ret) return ret; set_bit(MT76_STATE_INITIALIZED, &dev->mt76.state); ret = mt76x2_mac_start(dev); if (ret) return ret; ret = mt76x2_mcu_init(dev); if (ret) return ret; mt76x2_mac_stop(dev, false); dev->rxfilter = mt76_rr(dev, MT_RX_FILTR_CFG); return 0; }