static int initialize_usbh1_port(struct platform_device *pdev) { iomux_v3_cfg_t usbh1stp = MX51_PAD_USBH1_STP__USBH1_STP; iomux_v3_cfg_t usbh1gpio = MX51_PAD_USBH1_STP__GPIO1_27; u32 v; void __iomem *usb_base; void __iomem *socregs_base; mxc_iomux_v3_setup_pad(usbh1gpio); gpio_request(EFIKAMX_USBH1_STP, "usbh1_stp"); gpio_direction_output(EFIKAMX_USBH1_STP, 0); msleep(1); gpio_set_value(EFIKAMX_USBH1_STP, 1); msleep(1); usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); socregs_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); /* The clock for the USBH1 ULPI port will come externally */ /* from the PHY. */ v = __raw_readl(socregs_base + MX51_USB_CTRL_1_OFFSET); __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, socregs_base + MX51_USB_CTRL_1_OFFSET); iounmap(usb_base); gpio_free(EFIKAMX_USBH1_STP); mxc_iomux_v3_setup_pad(usbh1stp); mdelay(10); return mx51_initialize_usb_hw(0, MXC_EHCI_ITC_NO_THRESHOLD); }
static int initialize_usbh2_port(struct platform_device *pdev) { iomux_v3_cfg_t usbh2stp = MX51_PAD_EIM_A26__USBH2_STP; iomux_v3_cfg_t usbh2gpio = MX51_PAD_EIM_A26__GPIO2_20; mxc_iomux_v3_setup_pad(usbh2gpio); gpio_request(EFIKASB_USBH2_STP, "usbh2_stp"); gpio_direction_output(EFIKASB_USBH2_STP, 0); msleep(1); gpio_set_value(EFIKASB_USBH2_STP, 1); msleep(1); gpio_free(EFIKASB_USBH2_STP); mxc_iomux_v3_setup_pad(usbh2stp); mdelay(10); return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_ITC_NO_THRESHOLD); }
static int initialize_usbh1_port(struct platform_device *pdev) { u32 v; void __iomem *usb_base; void __iomem *usbother_base; usb_base = ioremap(MX51_USB_OTG_BASE_ADDR, SZ_4K); if (!usb_base) return -ENOMEM; usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET; /* */ v = __raw_readl(usbother_base + MX51_USB_CTRL_1_OFFSET); __raw_writel(v | MX51_USB_CTRL_UH1_EXT_CLK_EN, usbother_base + MX51_USB_CTRL_1_OFFSET); iounmap(usb_base); mdelay(10); return mx51_initialize_usb_hw(1, MXC_EHCI_POWER_PINS_ENABLED | MXC_EHCI_ITC_NO_THRESHOLD); }
/* This function is board specific as the bit mask for the plldiv will also * be different for other Freescale SoCs, thus a common bitmask is not * possible and cannot get place in /plat-mxc/ehci.c. */ static int initialize_otg_port(struct platform_device *pdev) { u32 v; void __iomem *usb_base; void __iomem *usbother_base; usb_base = ioremap(MX51_OTG_BASE_ADDR, SZ_4K); if (!usb_base) return -ENOMEM; usbother_base = (void __iomem *)(usb_base + MX5_USBOTHER_REGS_OFFSET); /* Set the PHY clock to 19.2MHz */ v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); v &= ~MX5_USB_UTMI_PHYCTRL1_PLLDIV_MASK; v |= MX51_USB_PLL_DIV_19_2_MHZ; __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC2_OFFSET); iounmap(usb_base); mdelay(10); return mx51_initialize_usb_hw(pdev->id, MXC_EHCI_INTERNAL_PHY); }