static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
struct i2c_msg *msg, uint32_t flags)
{
struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
uint32_t addr_data = msg->addr << 1;
uint32_t data = 0;
int i, shifts_left, ret;
/* Mute IRQs coming from this block. */
writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
if (msg->flags & I2C_M_RD) {
addr_data |= I2C_SMBUS_READ;
/* SELECT command. */
mxs_i2c_pio_trigger_cmd(i2c, MXS_CMD_I2C_SELECT);
ret = mxs_i2c_pio_wait_dmareq(i2c);
if (ret)
return ret;
writel(addr_data, i2c->regs + MXS_I2C_DATA);
writel(MXS_I2C_DEBUG0_DMAREQ, i2c->regs + MXS_I2C_DEBUG0_CLR);
ret = mxs_i2c_pio_wait_cplt(i2c, 0);
if (ret)
return ret;
if (mxs_i2c_pio_check_error_state(i2c))
goto cleanup;
/* READ command. */
mxs_i2c_pio_trigger_cmd(i2c,
MXS_CMD_I2C_READ | flags |
MXS_I2C_CTRL0_XFER_COUNT(msg->len));
for (i = 0; i < msg->len; i++) {
if ((i & 3) == 0) {
ret = mxs_i2c_pio_wait_dmareq(i2c);
if (ret)
return ret;
data = readl(i2c->regs + MXS_I2C_DATA);
writel(MXS_I2C_DEBUG0_DMAREQ,
i2c->regs + MXS_I2C_DEBUG0_CLR);
}
msg->buf[i] = data & 0xff;
data >>= 8;
}
} else {
static int mxs_i2c_pio_setup_xfer(struct i2c_adapter *adap,
struct i2c_msg *msg, uint32_t flags)
{
struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
uint32_t addr_data = msg->addr << 1;
uint32_t data = 0;
int i, ret, xlen = 0, xmit = 0;
uint32_t start;
/* Mute IRQs coming from this block. */
writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_CLR);
/*
* MX23 idea:
* - Enable CTRL0::PIO_MODE (1 << 24)
* - Enable CTRL1::ACK_MODE (1 << 27)
*
* WARNING! The MX23 is broken in some way, even if it claims
* to support PIO, when we try to transfer any amount of data
* that is not aligned to 4 bytes, the DMA engine will have
* bits in DEBUG1::DMA_BYTES_ENABLES still set even after the
* transfer. This in turn will mess up the next transfer as
* the block it emit one byte write onto the bus terminated
* with a NAK+STOP. A possible workaround is to reset the IP
* block after every PIO transmission, which might just work.
*
* NOTE: The CTRL0::PIO_MODE description is important, since
* it outlines how the PIO mode is really supposed to work.
*/
if (msg->flags & I2C_M_RD) {
/*
* PIO READ transfer:
*
* This transfer MUST be limited to 4 bytes maximum. It is not
* possible to transfer more than four bytes via PIO, since we
* can not in any way make sure we can read the data from the
* DATA register fast enough. Besides, the RX FIFO is only four
* bytes deep, thus we can only really read up to four bytes at
* time. Finally, there is no bit indicating us that new data
* arrived at the FIFO and can thus be fetched from the DATA
* register.
*/
BUG_ON(msg->len > 4);
addr_data |= I2C_SMBUS_READ;
/* SELECT command. */
mxs_i2c_pio_trigger_write_cmd(i2c, MXS_CMD_I2C_SELECT,
addr_data);
ret = mxs_i2c_pio_wait_xfer_end(i2c);
if (ret) {
dev_err(i2c->dev,
"PIO: Failed to send SELECT command!\n");
goto cleanup;
}
/* READ command. */
mxs_i2c_pio_trigger_cmd(i2c,
MXS_CMD_I2C_READ | flags |
MXS_I2C_CTRL0_XFER_COUNT(msg->len));
ret = mxs_i2c_pio_wait_xfer_end(i2c);
if (ret) {
dev_err(i2c->dev,
"PIO: Failed to send SELECT command!\n");
goto cleanup;
}
data = readl(i2c->regs + MXS_I2C_DATA(i2c));
for (i = 0; i < msg->len; i++) {
msg->buf[i] = data & 0xff;
data >>= 8;
}
} else {
