static void beagle_common_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, int cpu_model) { struct beagle_s *s = (struct beagle_s *) qemu_mallocz(sizeof(*s)); DriveInfo *dmtd = drive_get(IF_MTD, 0, 0); DriveInfo *dsd = drive_get(IF_SD, 0, 0); if (!dmtd && !dsd) { hw_error("%s: SD or NAND image required", __FUNCTION__); } #if MAX_SERIAL_PORTS < 1 #error MAX_SERIAL_PORTS must be at least 1! #endif s->cpu = omap3_mpu_init(cpu_model, 1, ram_size, NULL, NULL, serial_hds[0], NULL); s->nand = nand_init(NAND_MFR_MICRON, 0xba, dmtd ? dmtd->bdrv : NULL); nand_setpins(s->nand, 0, 0, 0, 1, 0); /* no write-protect */ omap_gpmc_attach(s->cpu->gpmc, BEAGLE_NAND_CS, s->nand, 0, 2); if (dsd) { omap3_mmc_attach(s->cpu->omap3_mmc[0], dsd->bdrv, 0, 0); } s->twl4030 = twl4030_init(omap_i2c_bus(s->cpu->i2c, 0), s->cpu->irq[0][OMAP_INT_3XXX_SYS_NIRQ], NULL, NULL); int i; for (i = 0; i < nb_nics; i++) { if (!nd_table[i].model || !strcmp(nd_table[i].model, "smc91c111")) { break; } } if (cpu_model == omap3430) { qemu_set_irq(qdev_get_gpio_in(s->cpu->gpio, BEAGLE_GPIO_ID1),1); qemu_set_irq(qdev_get_gpio_in(s->cpu->gpio, BEAGLE_GPIO_ID3),1); } if (i < nb_nics) { s->smc = qdev_create(NULL, "smc91c111"); qdev_set_nic_properties(s->smc, &nd_table[i]); qdev_init_nofail(s->smc); sysbus_connect_irq(sysbus_from_qdev(s->smc), 0, qdev_get_gpio_in(s->cpu->gpio, 54)); } else { hw_error("%s: no NIC for smc91c111\n", __FUNCTION__); } omap_gpmc_attach(s->cpu->gpmc, BEAGLE_SMC_CS, s->smc, 0, 0); /* Wire up an I2C slave which returns EDID monitor information; * newer Linux kernels won't turn on the display unless they * detect a monitor over DDC. */ s->ddc = i2c_create_slave(omap_i2c_bus(s->cpu->i2c, 2), "i2c-ddc", 0x50); omap_lcd_panel_attach(s->cpu->dss); }
void at91_spl_board_init(void) { /* * For on the sam9m10g45ek board, the chip wm9711 stay in the test * mode, so it need do some action to exit mode. */ at91_set_gpio_output(AT91_PIN_PD7, 0); at91_set_gpio_output(AT91_PIN_PD8, 0); at91_set_pio_pullup(AT91_PIO_PORTD, 7, 1); at91_set_pio_pullup(AT91_PIO_PORTD, 8, 1); at91_set_pio_pullup(AT91_PIO_PORTA, 12, 1); at91_set_pio_pullup(AT91_PIO_PORTA, 13, 1); at91_set_pio_pullup(AT91_PIO_PORTA, 15, 1); corvus_nand_hw_init(); /* Configure recovery button PINs */ at91_set_gpio_input(AT91_PIN_PB7, 1); /* check if button is pressed */ if (at91_get_gpio_value(AT91_PIN_PB7) == 0) { u32 boot_device; debug("Recovery button pressed\n"); boot_device = spl_boot_device(); switch (boot_device) { #ifdef CONFIG_SPL_NAND_SUPPORT case BOOT_DEVICE_NAND: nand_init(); spl_nand_erase_one(0, 0); break; #endif } } }
void arm_boot(void) { int *ddr_p = (void *)0x57000000; WTCON = 0; __asm__ __volatile__( "mrs r0, cpsr\n" "bic r0, r0, #0xc0\n" "msr cpsr, r0\n" : : :"r0" ); clock_init(); ddr_init(); nand_init(); led_init(); nand_read(ddr_p, 0, 0x40000); __asm__ __volatile__( "mov sp, #0x58000000\n" "mov lr, pc\n" "ldr pc, =main\n" "there:\n" "b there\n" ); }
void main(void){ uart0_init(); led_init(); nand_init(); irq_init(); int i = 0; for(i = 0;i < 10;i++){ uart0_puts("\nShell #"); uart0_gets(buf,MAX_LEN); const cmd_t *ptr; ptr = find_cmd(buf); if(ptr != 0){ ptr->call_back(); }else{ uart0_puts("\nNot find Cmd"); } /*if(!my_strcmp(buf,"ledon")){ uart0_puts(buf); led_on(); continue; }else if(!my_strcmp(buf,"ledoff")){ uart0_puts(buf); led_off(); continue; }else{ uart0_puts("\nNot command!!!"); continue; }*/ } }
/* go init the NAND */ static int initr_nand(void) { puts("NAND: "); nand_init(); printf("%lu MiB\n", nand_size() / 1024); return 0; }
int32_t init_nand(struct nand_driver_data *nand) { int32_t retval; retval = nand_init(nand); if (retval) { //print_dbg("ERROR: failed to init NAND flash\r\n"); return retval; } //block_status = malloc(nand->info.num_blocks); //if (!block_status) { ////print_dbg("ERROR: could not allocate badblock table\r\n"); //return -1; //} //nand->bad_table.block_status = block_status; //buffer = malloc(nand->info.page_size + nand->info.oob->size); //if (!buffer) { ////print_dbg("ERROR: could not allocate buffer\r\n"); //return -1; //} return 1; }
void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) { int i; platform_device_register(&edma_device); platform_device_register(&tnetv107x_wdt_device); platform_device_register(&tsc_device); if (info->serial_config) davinci_serial_init(info->serial_config); for (i = 0; i < 2; i++) if (info->mmc_config[i]) { mmc_devices[i].dev.platform_data = info->mmc_config[i]; platform_device_register(&mmc_devices[i]); } for (i = 0; i < 4; i++) if (info->nand_config[i]) nand_init(i, info->nand_config[i]); if (info->keypad_config) { keypad_device.dev.platform_data = info->keypad_config; platform_device_register(&keypad_device); } }
static int __init init_nand_libmodule(void) { printk("hello:%s,%d\n", __func__, __LINE__); printk("hello:%s,%d\n", __func__, __LINE__); nand_init(); return 0; }
int board_init(void) { gd->bd->bi_arch_number=MACH_TYPE_MESON6_SKT; gd->bd->bi_boot_params=BOOT_PARAMS_OFFSET; #if CONFIG_JERRY_NAND_TEST //temp test nand_init(); #endif #ifdef CONFIG_AML_I2C board_i2c_init(); #endif /*CONFIG_AML_I2C*/ #ifdef CONFIG_IR_REMOTE board_ir_init(); #endif #ifdef CONFIG_USB_DWC_OTG_HCD board_usb_init(&g_usb_config_m6_skt_b,BOARD_USB_MODE_HOST); board_usb_init(&g_usb_config_m6_skt_h,BOARD_USB_MODE_CHARGER); #endif /*CONFIG_USB_DWC_OTG_HCD*/ key_init(); wifi_power_init(); run_command("magic_checkstatus", 0); return 0; }
int nprobe(struct platform_device *pdev) { struct nand_info *nand; int ret = 0; struct resource *io_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if(!io_res) return -EBUSY; nand = kzalloc(sizeof(*nand), GFP_KERNEL); if(!nand) return -ENOMEM; nand->virt = ioremap(io_res->start, io_res->end - io_res->start + 1); if(!nand->virt){ ret = -ENOMEM; goto ioremap_error; } nand->part = pdev->dev.platform_data; nand->chip.IO_ADDR_R = nand->virt + NFDATA; nand->chip.IO_ADDR_W = nand->virt + NFDATA; nand->chip.dev_ready = nand_dev_ready; nand->chip.cmd_ctrl = nand_cmd_ctrl; nand->chip.ecc.mode = NAND_ECC_SOFT; //nand->options = NAND_SKIP_BBTSCAN, nand->mtd.priv = &nand->chip; nand->mtd.owner = THIS_MODULE; //设置nand子系统中的默认的操作nand的方法 ret = nand_scan(&nand->mtd, nand->part->num_chips); if(ret) goto nand_scan_error; //注册mtd设备,添加分区 ret = add_mtd_partitions(&nand->mtd, nand->part->partition, nand->part->num_partitions); if(ret) goto add_part_error; platform_set_drvdata(pdev, nand); nand->clk = clk_get(NULL, "nand"); clk_enable(nand->clk); nand_init(nand); return 0; add_part_error: nand_scan_error: iounmap(nand->virt); ioremap_error: kfree(nand); return ret; }
void music_play() { printf("music_play\r\n"); nand_init(); short *pData = (short *)0x33000000; short *pData_end = pData + 882046/4; int send_cnt = 0; int i = 0; printf("read start\r\n"); nand_read((unsigned char *)pData, 0x60000, 0x200000); printf("the head of wav : 0x%x\r\n", *pData); pData += 0x2e;//real data offset while(1) { while (IISCON & IS_FIFO_READY); IISFIFO = *pData; if (pData == pData_end) { return 0; } pData++; } }
void board_init_r(gd_t *id, ulong dummy) { nand_init(); puts("Nand boot...\n"); nand_boot(); }
static void overo_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { struct overo_s *s = (struct overo_s *) g_malloc0(sizeof(*s)); DriveInfo *dmtd = drive_get(IF_MTD, 0, 0); DriveInfo *dsd = drive_get(IF_SD, 0, 0); if (ram_size > 1024 * 1024 * 1024) { fprintf(stderr, "overo: maximum permitted RAM size 1024MB\n"); exit(1); } if (!dmtd && !dsd) { hw_error("%s: SD or NAND image required", __FUNCTION__); } s->cpu = omap3_mpu_init(omap3430, ram_size, NULL, NULL, serial_hds[0], NULL); s->nand = nand_init(dmtd ? dmtd->bdrv : NULL, NAND_MFR_MICRON, 0xba); nand_setpins(s->nand, 0, 0, 0, 1, 0); /* no write-protect */ omap_gpmc_attach_nand(s->cpu->gpmc, OVERO_NAND_CS, s->nand); if (dsd) { omap3_mmc_attach(s->cpu->omap3_mmc[0], dsd->bdrv, 0, 0); } /* FAB revs >= 2516: 4030 interrupt is GPIO 0 (earlier ones were 112) */ s->twl4030 = twl4030_init(omap_i2c_bus(s->cpu->i2c, 0), qdev_get_gpio_in(s->cpu->gpio, 0), NULL, NULL); /* Wire up an I2C slave which returns EDID monitor information; * newer Linux kernels won't turn on the display unless they * detect a monitor over DDC. */ s->ddc = i2c_create_slave(omap_i2c_bus(s->cpu->i2c, 2), "i2c-ddc", 0x50); omap_lcd_panel_attach(s->cpu->dss); /* Strictly this should be a LAN9221 */ if (nd_table[0].vlan) { /* The ethernet chip hangs off the GPMC */ NICInfo *nd = &nd_table[0]; qemu_check_nic_model(nd, "lan9118"); s->eth = qdev_create(NULL, "lan9118"); qdev_set_nic_properties(s->eth, nd); qdev_init_nofail(s->eth); omap_gpmc_attach(s->cpu->gpmc, OVERO_NET_CS, sysbus_mmio_get_region(sysbus_from_qdev(s->eth), 0)); sysbus_connect_irq(sysbus_from_qdev(s->eth), 0, qdev_get_gpio_in(s->cpu->gpio, 176)); } }
int board_init(void) { gd->bd->bi_arch_number=MACH_TYPE_MESON6_REF; gd->bd->bi_boot_params=BOOT_PARAMS_OFFSET; #if CONFIG_JERRY_NAND_TEST //temp test nand_init(); #endif return 0; }
int copy2ddr(unsigned int nand_start, unsigned int ddr_start, unsigned int len) { int ret; /* 初始化nand flash controller */ nand_init(); /* 读nand flash */ ret = nand_read(nand_start, ddr_start, len); return ret; }
void memories_initialization(void) { #ifdef CONF_BOARD_SMC_PSRAM psram_init(); #endif #ifdef CONF_BOARD_SRAM ext_sram_init(); #endif #ifdef CONF_BOARD_NAND nand_init(); #endif }
int spl_nand_load_image(void) { nand_init(); nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, (void *)CONFIG_SYS_NAND_U_BOOT_DST); spl_set_header_raw_uboot(); nand_deselect(); return 0; }
int spl_nand_load_image(struct spl_image_info *spl_image, struct spl_boot_device *bootdev) { nand_init(); nand_spl_load_image(CONFIG_SYS_NAND_U_BOOT_OFFS, CONFIG_SYS_NAND_U_BOOT_SIZE, (void *)CONFIG_SYS_NAND_U_BOOT_DST); spl_set_header_raw_uboot(spl_image); nand_deselect(); return 0; }
int main() { nand_init(); nand_erase(0x600000, 0x100000); char *str = "jiangshen 123456789 haha"; nand_write((unsigned int)str, 0x600000, 2048); nand_read((unsigned int)0x41000000, 0x600000, 2048); return 0; }
int board_init(void) { gd->bd->bi_arch_number=MACH_TYPE_MESON6_REF; gd->bd->bi_boot_params=BOOT_PARAMS_OFFSET; #if CONFIG_JERRY_NAND_TEST //temp test nand_init(); #endif // set cpu freq to 600MHZ // aml_set_reg32_bits(0xb5,P_HHI_SYS_CPU_CLK_CNTL); writel(0xb5,P_HHI_SYS_CPU_CLK_CNTL); writel(0x180,P_PREG_CTLREG0_ADDR); writel(0x80000232,P_HHI_SYS_PLL_CNTL); return 0; }
int board_init(void) { #ifdef CONFIG_UART_A_FUNCTION_ADD unsigned a_uart = (159375000/(115200*4) -1) | UART_STP_BIT | UART_PRTY_BIT | UART_CHAR_LEN | UART_CNTL_MASK_TX_EN | UART_CNTL_MASK_RX_EN | UART_CNTL_MASK_RST_TX | UART_CNTL_MASK_RST_RX | UART_CNTL_MASK_CLR_ERR ; serial_init_uart_a(a_uart); #endif #if KSZ8091 CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO1_EN_N, 1 << 31); CLEAR_CBUS_REG_MASK(PREG_PAD_GPIO1_O, 1 << 31); #endif gd->bd->bi_arch_number=MACH_TYPE_MESON6_SKT; gd->bd->bi_boot_params=BOOT_PARAMS_OFFSET; #if CONFIG_JERRY_NAND_TEST //temp test nand_init(); #endif // LED clrbits_le32(P_AO_GPIO_O_EN_N, (1 << 15)); clrbits_le32(P_AO_GPIO_O_EN_N, (1 << 31)); #ifdef CONFIG_AML_I2C board_i2c_init(); #endif /*CONFIG_AML_I2C*/ #ifdef CONFIG_IR_REMOTE board_ir_init(); #endif #ifdef CONFIG_USB_DWC_OTG_HCD board_usb_init(&g_usb_config_m6_skt_b,BOARD_USB_MODE_HOST); board_usb_init(&g_usb_config_m6_skt_h,BOARD_USB_MODE_CHARGER); #endif /*CONFIG_USB_DWC_OTG_HCD*/ #ifdef CONFIG_NET_WIFI wifi_power_init(); #endif key_init(); return 0; }
int flash_init(void) { int ret = ERROR; nand_init_clear(); ret = nand_init(); if(ret) { cprintf("ERROR: nand init failed, ret = 0x%x\n", ret); goto ERRO; } return ret; ERRO: return ret; }
static void beagle_common_init(ram_addr_t ram_size, const char *boot_device, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, int cpu_model) { MemoryRegion *sysmem = get_system_memory(); struct beagle_s *s = (struct beagle_s *) g_malloc0(sizeof(*s)); DriveInfo *dmtd = drive_get(IF_MTD, 0, 0); DriveInfo *dsd = drive_get(IF_SD, 0, 0); if (!dmtd && !dsd) { hw_error("%s: SD or NAND image required", __FUNCTION__); } #if MAX_SERIAL_PORTS < 1 #error MAX_SERIAL_PORTS must be at least 1! #endif s->cpu = omap3_mpu_init(sysmem, cpu_model, ram_size, NULL, NULL, serial_hds[0], NULL); s->nand = nand_init(dmtd ? dmtd->bdrv : NULL, NAND_MFR_MICRON, 0xba); nand_setpins(s->nand, 0, 0, 0, 1, 0); /* no write-protect */ omap_gpmc_attach_nand(s->cpu->gpmc, BEAGLE_NAND_CS, s->nand); if (dsd) { omap3_mmc_attach(s->cpu->omap3_mmc[0], dsd->bdrv, 0, 0); } s->twl4030 = twl4030_init(omap_i2c_bus(s->cpu->i2c[0]), qdev_get_gpio_in(s->cpu->ih[0], OMAP_INT_3XXX_SYS_NIRQ), NULL, NULL); if (cpu_model == omap3430) { qemu_set_irq(qdev_get_gpio_in(s->cpu->gpio, BEAGLE_GPIO_ID1),1); qemu_set_irq(qdev_get_gpio_in(s->cpu->gpio, BEAGLE_GPIO_ID3),1); } /* Wire up an I2C slave which returns EDID monitor information; * newer Linux kernels won't turn on the display unless they * detect a monitor over DDC. */ s->ddc = i2c_create_slave(omap_i2c_bus(s->cpu->i2c[2]), "i2c-ddc", 0x50); omap_lcd_panel_attach(s->cpu->dss); }
int main() { copy_vec(); irq_init(); button_init(); uart0_init(); timer_init(); // timer4_init(); lcd_init(); lcd_clean(0xffff); adc_ts_init(); ts_init(); // tslib_calibrate(); // lcd_clean(0xffff); nand_init(); #if 1 nand_read_id(); while(1); #endif printf("\r\n\n"); printf("===============================================\r\n"); printf(" NAND FLASH PROGRAMMING \r\n"); unsigned int size = 512 * 1024; // 512KB nand_read_id(); printf("erase entire flash, waiting ... \r\n"); int i; for(i = 0; i < 2048; i++) nand_erase_block(i); printf("start program ... \r\n"); nand_write_bytes(0x0, (unsigned char *)0x31000000, size); printf("program end ... \r\n"); printf("===============================================\r\n"); while(1); return 0; }
void __init tnetv107x_devices_init(struct tnetv107x_device_info *info) { int i, error; struct clk *tsc_clk; /* * The reset defaults for tnetv107x tsc clock divider is set too high. * This forces the clock down to a range that allows the ADC to * complete sample conversion in time. */ tsc_clk = clk_get(NULL, "sys_tsc_clk"); if (tsc_clk) { error = clk_set_rate(tsc_clk, 5000000); WARN_ON(error < 0); clk_put(tsc_clk); } platform_device_register(&edma_device); platform_device_register(&tnetv107x_wdt_device); platform_device_register(&tsc_device); if (info->serial_config) davinci_serial_init(info->serial_config); for (i = 0; i < 2; i++) if (info->mmc_config[i]) { mmc_devices[i].dev.platform_data = info->mmc_config[i]; platform_device_register(&mmc_devices[i]); } for (i = 0; i < 4; i++) if (info->nand_config[i]) nand_init(i, info->nand_config[i]); if (info->keypad_config) { keypad_device.dev.platform_data = info->keypad_config; platform_device_register(&keypad_device); } if (info->ssp_config) { ssp_device.dev.platform_data = info->ssp_config; platform_device_register(&ssp_device); } }
int board_init(void) { #ifdef CONFIG_M201_COSTDOWN /* pull up Linux rx/tx */ writel(readl(P_AO_RTI_PULL_UP_REG) | (3 << 0 | 3 << 16), P_AO_RTI_PULL_UP_REG); #endif borad_power_init(); gd->bd->bi_arch_number=MACH_TYPE_MESON6_SKT; gd->bd->bi_boot_params=BOOT_PARAMS_OFFSET; #if CONFIG_JERRY_NAND_TEST //temp test nand_init(); #endif #ifdef CONFIG_AML_I2C board_i2c_init(); #endif /*CONFIG_AML_I2C*/ #ifdef CONFIG_IR_REMOTE board_ir_init(); #endif #ifdef CONFIG_USB_DWC_OTG_HCD board_usb_init(&g_usb_config_m6_skt_b,BOARD_USB_MODE_HOST); board_usb_init(&g_usb_config_m6_skt_h,BOARD_USB_MODE_CHARGER); #endif /*CONFIG_USB_DWC_OTG_HCD*/ #ifdef CONFIG_M201_COSTDOWN /* 32k clock init */ printf("init 32k clock\n"); aml_set_reg32_mask(P_PERIPHS_PIN_MUX_9,0x1<<19);//set mode GPIOX_10-->CLK_OUT3 WRITE_CBUS_REG(PWM_PWM_E, 0x16d016d); WRITE_CBUS_REG(PWM_MISC_REG_EF, 0x8001); /* init led out put */ //red off gpio_amlogic_requst(NULL, GPIOAO_2); gpio_amlogic_direction_output(NULL, GPIOAO_2, 1); //green on gpio_amlogic_requst(NULL, GPIOAO_13); gpio_amlogic_direction_output(NULL, GPIOAO_13, 0); #endif return 0; }
int board_init(void) { gd->bd->bi_arch_number=MACH_TYPE_MESON6_SKT; gd->bd->bi_boot_params=BOOT_PARAMS_OFFSET; #ifdef CONFIG_UBOOT_BUILD_VERSION_INFO print_build_version_info(); #endif #if CONFIG_JERRY_NAND_TEST //temp test nand_init(); #endif #ifdef CONFIG_AML_I2C board_i2c_init(); #endif /*CONFIG_AML_I2C*/ #ifdef CONFIG_IR_REMOTE board_ir_init(); #endif #ifdef CONFIG_USB_XHCI_AMLOGIC board_usb_init(&g_usb_config_g9TV_skt,BOARD_USB_MODE_HOST); #endif /*CONFIG_USB_XHCI_AMLOGIC*/ #if defined(CONFIG_VLSI_EMULATOR) run_command("video dev open 1080p", 0); #endif #ifdef CONFIG_PWM_E_OUT_32K printf("init pwm_e out 32k clock.\n"); writel(readl(P_PERIPHS_PIN_MUX_9) | (0x1 << 19), P_PERIPHS_PIN_MUX_9); //set mode GPIOX_10-->CLK_OUT3 writel(0x16d016d, P_PWM_PWM_E); writel((readl(P_PWM_MISC_REG_EF) & ~(0xFF << 8)) | 0x8001, P_PWM_MISC_REG_EF); #endif //default power on 24M writel(readl(P_PERIPHS_PIN_MUX_10)&~(1 << 11),P_PERIPHS_PIN_MUX_10); writel(readl(P_AO_GPIO_O_EN_N)&~(1 << 18),P_AO_GPIO_O_EN_N); writel(readl(P_AO_GPIO_O_EN_N)&~(1 << 2),P_AO_GPIO_O_EN_N); return 0; }
TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq) { TC6393xbState *s; DriveInfo *nand; static const MemoryRegionOps tc6393xb_ops = { .read = tc6393xb_readb, .write = tc6393xb_writeb, .endianness = DEVICE_NATIVE_ENDIAN, .impl = { .min_access_size = 1, .max_access_size = 1, }, }; s = (TC6393xbState *) g_malloc0(sizeof(TC6393xbState)); s->irq = irq; s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS); s->l3v = *qemu_allocate_irqs(tc6393xb_l3v, s, 1); s->blanked = 1; s->sub_irqs = qemu_allocate_irqs(tc6393xb_sub_irq, s, TC6393XB_NR_IRQS); nand = drive_get(IF_MTD, 0, 0); s->flash = nand_init(nand ? nand->bdrv : NULL, NAND_MFR_TOSHIBA, 0x76); memory_region_init_io(&s->iomem, &tc6393xb_ops, s, "tc6393xb", 0x10000); memory_region_add_subregion(sysmem, base, &s->iomem); memory_region_init_ram(&s->vram, "tc6393xb.vram", 0x100000); vmstate_register_ram_global(&s->vram); s->vram_ptr = memory_region_get_ram_ptr(&s->vram); memory_region_add_subregion(sysmem, base + 0x100000, &s->vram); s->scr_width = 480; s->scr_height = 640; s->con = graphic_console_init(tc6393xb_update_display, NULL, /* invalidate */ NULL, /* screen_dump */ NULL, /* text_update */ s); return s; }
static void __init omap_safir_init(void) { omap3_mux_init(board_mux, OMAP_PACKAGE_CBP); omap_mux_uart(); print_board_rev(); omap_serial_init(); nand_init(); mmc_init(); i2c_init(); ak4117_init(); spi_init(); bt_init(); usb_init(); ipod_init(); safir_audio_init(); safir_init_smsc911x(); platform_add_devices(board_devices, ARRAY_SIZE(board_devices)); }
//============================================================================ static int nand_sub_test(nand_info_t *nand, int idx) { if (!nand) { nand_init(); if (!nand) { post_log("<%d>%s:%d: NAND[device:%d]: no NAND device available.\n", SYSTEST_INFO_L2, __FUNCTION__, __LINE__, idx); return -1; } } if (nand->name) { //struct nand_chip *chip = nand->priv; /*#ifdef CONFIG_MTD_DEVICE sprintf(systest_info_line, "NAND: Device %d: %s, %s sector size %u KiB \n", idx, nand->name, nand->info, nand->erasesize >> 10); systest_log(systest_info_line, SYSTEST_INFO_L2); #else */ post_log("<%d>NAND: Device %d: %s, sector size %u KiB \n", SYSTEST_INFO_L2, idx, nand->name, nand->erasesize >> 10) ; //#endif }