static int __devinit mdss_dsi_panel_probe(struct platform_device *pdev) { int rc = 0; static struct mdss_panel_common_pdata vendor_pdata; static const char *panel_name; #ifdef CONFIG_LGE_SUPPORT_LCD_MAKER_ID struct class *panel; struct device *panel_sysfs_dev; #endif pr_debug("%s:%d, debug info id=%d", __func__, __LINE__, pdev->id); if (!pdev->dev.of_node) return -ENODEV; #if defined(CONFIG_MACH_LGE) register_syscore_ops(&panel_syscore_ops); #endif panel_name = of_get_property(pdev->dev.of_node, "label", NULL); if (!panel_name) pr_info("%s:%d, panel name not specified\n", __func__, __LINE__); else pr_info("%s: Panel Name = %s\n", __func__, panel_name); rc = mdss_panel_parse_dt(pdev, &vendor_pdata); if (rc) return rc; vendor_pdata.on = mdss_dsi_panel_on; vendor_pdata.off = mdss_dsi_panel_off; vendor_pdata.bl_fnc = mdss_dsi_panel_bl_ctrl; rc = dsi_panel_device_register(pdev, &vendor_pdata); if (rc) return rc; #ifdef CONFIG_LGE_SUPPORT_LCD_MAKER_ID panel = class_create(THIS_MODULE, "panel"); if (IS_ERR(panel)) pr_err("%s : Failed to create class(panel)!", __func__); panel_sysfs_dev = device_create(panel, NULL, 0, NULL, "panel_info"); if (IS_ERR(panel_sysfs_dev)) { pr_err("%s : Failed to create dev(panel_sysfs_dev)!", __func__); } else { if (device_create_file(panel_sysfs_dev, &dev_attr_panel_maker_id) < 0) pr_err("%s : Failed to create device file(%s)!", __func__, dev_attr_panel_maker_id.attr.name); } #endif #if defined(CONFIG_OLED_SUPPORT) && defined(CONFIG_LGE_OLED_IMG_TUNING) rc = device_create_file(&pdev->dev,&panel_tuning_device_attrs[0]); if(rc) pr_err("%s: device file(img_tune_mode) create fail!\n",__func__); rc = device_create_file(&pdev->dev,&panel_tuning_device_attrs[1]); if(rc) pr_err("%s: device file(bl_tune_mode) create fail!\n",__func__); rc = device_create_file(&pdev->dev,&panel_tuning_device_attrs[2]); if(rc) pr_err("%s: device file(mipi_dsi_read) create fail!\n",__func__); #endif #if defined(CONFIG_MACH_LGE) && !(defined(CONFIG_MACH_MSM8974_Z_KR) || defined(CONFIG_MACH_MSM8974_Z_US) || defined(CONFIG_MACH_MSM8974_Z_KDDI)) rc = device_create_file(&pdev->dev, &dev_attr_ief_on_off); #endif #ifdef CONFIG_LGE_SUPPORT_LCD_MAKER_ID pr_info("panel maker ID is %d\n", lge_get_panel_maker()); local_pdata = &vendor_pdata; if (!local_pdata) return -EINVAL; #endif rc = sysfs_create_group(&pdev->dev.kobj, &dsi_panel_attribute_group); if (rc) pr_err("%s: sysfs create failed: %d\n", panel_name, rc); return rc; }
static int __init xilinx_spi_of_probe(struct of_device *ofdev, const struct of_device_id *match) { struct spi_master *master; struct xilinx_spi *xspi; struct resource r_irq_struct; struct resource r_mem_struct; struct resource *r_irq = &r_irq_struct; struct resource *r_mem = &r_mem_struct; int rc = 0; const u32 *prop; int len; /* Get resources(memory, IRQ) associated with the device */ master = spi_alloc_master(&ofdev->dev, sizeof(struct xilinx_spi)); if (master == NULL) { return -ENOMEM; } dev_set_drvdata(&ofdev->dev, master); rc = of_address_to_resource(ofdev->node, 0, r_mem); if (rc) { dev_warn(&ofdev->dev, "invalid address\n"); goto put_master; } rc = of_irq_to_resource(ofdev->node, 0, r_irq); if (rc == NO_IRQ) { dev_warn(&ofdev->dev, "no IRQ found\n"); goto put_master; } xspi = spi_master_get_devdata(master); xspi->bitbang.master = spi_master_get(master); xspi->bitbang.chipselect = xilinx_spi_chipselect; xspi->bitbang.setup_transfer = xilinx_spi_setup_transfer; xspi->bitbang.txrx_bufs = xilinx_spi_txrx_bufs; xspi->bitbang.master->setup = xilinx_spi_setup; xspi->bitbang.flags |= SPI_SLAVE; init_completion(&xspi->done); xspi->rx_ptr = xspi->slave_rx_buf; xspi->irq = r_irq->start; if (!request_mem_region(r_mem->start, r_mem->end - r_mem->start + 1, XILINX_SPI_NAME)) { rc = -ENXIO; dev_warn(&ofdev->dev, "memory request failure\n"); goto put_master; } xspi->regs = ioremap(r_mem->start, r_mem->end - r_mem->start + 1); if (xspi->regs == NULL) { rc = -ENOMEM; dev_warn(&ofdev->dev, "ioremap failure\n"); goto release_mem; } xspi->irq = r_irq->start; /* dynamic bus assignment */ master->bus_num = -1; /* number of slave select bits is required */ prop = of_get_property(ofdev->node, "xlnx,num-ss-bits", &len); if (!prop || len < sizeof(*prop)) { dev_warn(&ofdev->dev, "no 'xlnx,num-ss-bits' property\n"); goto unmap_io; } master->num_chipselect = *prop; /* SPI controller initializations */ xspi_init_hw(xspi); /* Register for SPI Interrupt */ rc = request_irq(xspi->irq, xilinx_spi_irq, 0, XILINX_SPI_NAME, xspi); if (rc != 0) { dev_warn(&ofdev->dev, "irq request failure: %d\n", xspi->irq); goto unmap_io; } rc = spi_bitbang_start(&xspi->bitbang); if (rc != 0) { dev_err(&ofdev->dev, "spi_bitbang_start FAILED\n"); goto free_irq; } dev_info(&ofdev->dev, "at 0x%08X mapped to 0x%08X, irq=%d\n", (unsigned int)r_mem->start, (u32)xspi->regs, xspi->irq); /* Add any subnodes on the SPI bus */ of_register_spi_devices(master, ofdev->node); return rc; free_irq: free_irq(xspi->irq, xspi); unmap_io: iounmap(xspi->regs); release_mem: release_mem_region(r_mem->start, resource_size(r_mem)); put_master: spi_master_put(master); return rc; }
static int state_probe(struct device_d *dev) { struct device_node *np = dev->device_node; struct device_node *partition_node; struct state *state; const char *alias; const char *backend_type = NULL; int len, ret; const char *of_path; char *path; if (!np) return -EINVAL; alias = of_alias_get(np); if (!alias) alias = np->name; state = state_new_from_node(alias, np); if (IS_ERR(state)) return PTR_ERR(state); of_path = of_get_property(np, "backend", &len); if (!of_path) { ret = -ENODEV; goto out_release; } /* guess if of_path is a path, not a phandle */ if (of_path[0] == '/' && len > 1) { ret = of_find_path(np, "backend", &path, 0); } else { partition_node = of_parse_phandle(np, "backend", 0); if (!partition_node) return -EINVAL; of_path = partition_node->full_name; ret = of_find_path_by_node(partition_node, &path, 0); } if (ret == -ENODEV) ret = -EPROBE_DEFER; if (ret) goto out_release; ret = of_property_read_string(np, "backend-type", &backend_type); if (ret) { goto out_free; } else if (!strcmp(backend_type, "raw")) { ret = state_backend_raw_file(state, of_path, path, 0, 0); } else if (!strcmp(backend_type, "dtb")) { ret = state_backend_dtb_file(state, of_path, path); } else { dev_warn(dev, "invalid backend type: %s\n", backend_type); ret = -ENODEV; goto out_free; } if (ret) goto out_free; dev_info(dev, "backend: %s, path: %s, of_path: %s\n", backend_type, path, of_path); free(path); return 0; out_free: free(path); out_release: state_release(state); return ret; }
static int mdss_panel_parse_dt(struct platform_device *pdev, struct mdss_panel_common_pdata *panel_data) { struct device_node *np = pdev->dev.of_node; u32 res[6], tmp; u32 fbc_res[7]; int rc, i, len; const char *data; static const char *bl_ctrl_type, *pdest; bool fbc_enabled = false; rc = of_property_read_u32_array(np, "qcom,mdss-pan-res", res, 2); if (rc) { pr_err("%s:%d, panel resolution not specified\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.xres = (!rc ? res[0] : 640); panel_data->panel_info.yres = (!rc ? res[1] : 480); rc = of_property_read_u32_array(np, "qcom,mdss-pan-active-res", res, 2); if (rc == 0) { panel_data->panel_info.lcdc.xres_pad = panel_data->panel_info.xres - res[0]; panel_data->panel_info.lcdc.yres_pad = panel_data->panel_info.yres - res[1]; } rc = of_property_read_u32(np, "qcom,mdss-pan-bpp", &tmp); if (rc) { pr_err("%s:%d, panel bpp not specified\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.bpp = (!rc ? tmp : 24); pdest = of_get_property(pdev->dev.of_node, "qcom,mdss-pan-dest", NULL); if (strlen(pdest) != 9) { pr_err("%s: Unknown pdest specified\n", __func__); return -EINVAL; } if (!strncmp(pdest, "display_1", 9)) panel_data->panel_info.pdest = DISPLAY_1; else if (!strncmp(pdest, "display_2", 9)) panel_data->panel_info.pdest = DISPLAY_2; else { pr_debug("%s: pdest not specified. Set Default\n", __func__); panel_data->panel_info.pdest = DISPLAY_1; } rc = of_property_read_u32_array(np, "qcom,mdss-pan-porch-values", res, 6); panel_data->panel_info.lcdc.h_back_porch = (!rc ? res[0] : 6); panel_data->panel_info.lcdc.h_pulse_width = (!rc ? res[1] : 2); panel_data->panel_info.lcdc.h_front_porch = (!rc ? res[2] : 6); panel_data->panel_info.lcdc.v_back_porch = (!rc ? res[3] : 6); panel_data->panel_info.lcdc.v_pulse_width = (!rc ? res[4] : 2); panel_data->panel_info.lcdc.v_front_porch = (!rc ? res[5] : 6); rc = of_property_read_u32(np, "qcom,mdss-pan-underflow-clr", &tmp); panel_data->panel_info.lcdc.underflow_clr = (!rc ? tmp : 0xff); bl_ctrl_type = of_get_property(pdev->dev.of_node, "qcom,mdss-pan-bl-ctrl", NULL); if ((bl_ctrl_type) && (!strncmp(bl_ctrl_type, "bl_ctrl_wled", 12))) { led_trigger_register_simple("bkl-trigger", &bl_led_trigger); pr_debug("%s: SUCCESS-> WLED TRIGGER register\n", __func__); panel_data->panel_info.bklt_ctrl = BL_WLED; } else if (!strncmp(bl_ctrl_type, "bl_ctrl_pwm", 11)) { panel_data->panel_info.bklt_ctrl = BL_PWM; rc = of_property_read_u32(np, "qcom,pwm-period", &tmp); if (rc) { pr_err("%s:%d, Error, panel pwm_period\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.pwm_period = tmp; rc = of_property_read_u32(np, "qcom,pwm-lpg-channel", &tmp); if (rc) { pr_err("%s:%d, Error, dsi lpg channel\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.pwm_lpg_chan = tmp; tmp = of_get_named_gpio(np, "qcom,pwm-pmic-gpio", 0); panel_data->panel_info.pwm_pmic_gpio = tmp; } else if (!strncmp(bl_ctrl_type, "bl_ctrl_dcs", 11)) { panel_data->panel_info.bklt_ctrl = BL_DCS_CMD; } else { pr_debug("%s: Unknown backlight control\n", __func__); panel_data->panel_info.bklt_ctrl = UNKNOWN_CTRL; } rc = of_property_read_u32_array(np, "qcom,mdss-pan-bl-levels", res, 2); panel_data->panel_info.bl_min = (!rc ? res[0] : 0); panel_data->panel_info.bl_max = (!rc ? res[1] : 255); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-mode", &tmp); panel_data->panel_info.mipi.mode = (!rc ? tmp : DSI_VIDEO_MODE); rc = of_property_read_u32(np, "qcom,mdss-vsync-enable", &tmp); panel_data->panel_info.mipi.vsync_enable = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-hw-vsync-mode", &tmp); panel_data->panel_info.mipi.hw_vsync_mode = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-h-pulse-mode", &tmp); panel_data->panel_info.mipi.pulse_mode_hsa_he = (!rc ? tmp : false); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-h-power-stop", res, 3); panel_data->panel_info.mipi.hbp_power_stop = (!rc ? res[0] : false); panel_data->panel_info.mipi.hsa_power_stop = (!rc ? res[1] : false); panel_data->panel_info.mipi.hfp_power_stop = (!rc ? res[2] : false); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-bllp-power-stop", res, 2); panel_data->panel_info.mipi.bllp_power_stop = (!rc ? res[0] : false); panel_data->panel_info.mipi.eof_bllp_power_stop = (!rc ? res[1] : false); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-traffic-mode", &tmp); panel_data->panel_info.mipi.traffic_mode = (!rc ? tmp : DSI_NON_BURST_SYNCH_PULSE); rc = of_property_read_u32(np, "qcom,mdss-pan-insert-dcs-cmd", &tmp); panel_data->panel_info.mipi.insert_dcs_cmd = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-pan-wr-mem-continue", &tmp); panel_data->panel_info.mipi.wr_mem_continue = (!rc ? tmp : 0x3c); rc = of_property_read_u32(np, "qcom,mdss-pan-wr-mem-start", &tmp); panel_data->panel_info.mipi.wr_mem_start = (!rc ? tmp : 0x2c); rc = of_property_read_u32(np, "qcom,mdss-pan-te-sel", &tmp); panel_data->panel_info.mipi.te_sel = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dst-format", &tmp); panel_data->panel_info.mipi.dst_format = (!rc ? tmp : DSI_VIDEO_DST_FORMAT_RGB888); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-vc", &tmp); panel_data->panel_info.mipi.vc = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-rgb-swap", &tmp); panel_data->panel_info.mipi.rgb_swap = (!rc ? tmp : DSI_RGB_SWAP_RGB); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-data-lanes", res, 4); panel_data->panel_info.mipi.data_lane0 = (!rc ? res[0] : true); panel_data->panel_info.mipi.data_lane1 = (!rc ? res[1] : false); panel_data->panel_info.mipi.data_lane2 = (!rc ? res[2] : false); panel_data->panel_info.mipi.data_lane3 = (!rc ? res[3] : false); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dlane-swap", &tmp); panel_data->panel_info.mipi.dlane_swap = (!rc ? tmp : 0); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-t-clk", res, 2); panel_data->panel_info.mipi.t_clk_pre = (!rc ? res[0] : 0x24); panel_data->panel_info.mipi.t_clk_post = (!rc ? res[1] : 0x03); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-stream", &tmp); panel_data->panel_info.mipi.stream = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-mdp-tr", &tmp); panel_data->panel_info.mipi.mdp_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (panel_data->panel_info.mipi.mdp_trigger > 6) { pr_err("%s:%d, Invalid mdp trigger. Forcing to sw trigger", __func__, __LINE__); panel_data->panel_info.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dma-tr", &tmp); panel_data->panel_info.mipi.dma_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (panel_data->panel_info.mipi.dma_trigger > 6) { pr_err("%s:%d, Invalid dma trigger. Forcing to sw trigger", __func__, __LINE__); panel_data->panel_info.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-frame-rate", &tmp); panel_data->panel_info.mipi.frame_rate = (!rc ? tmp : 60); rc = of_property_read_u32(np, "qcom,mdss-pan-clk-rate", &tmp); panel_data->panel_info.clk_rate = (!rc ? tmp : 0); data = of_get_property(np, "qcom,panel-phy-regulatorSettings", &len); if ((!data) || (len != 7)) { pr_err("%s:%d, Unable to read Phy regulator settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.regulator[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-timingSettings", &len); if ((!data) || (len != 12)) { pr_err("%s:%d, Unable to read Phy timing settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.timing[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-strengthCtrl", &len); if ((!data) || (len != 2)) { pr_err("%s:%d, Unable to read Phy Strength ctrl settings", __func__, __LINE__); goto error; } phy_params.strength[0] = data[0]; phy_params.strength[1] = data[1]; data = of_get_property(np, "qcom,panel-phy-bistCtrl", &len); if ((!data) || (len != 6)) { pr_err("%s:%d, Unable to read Phy Bist Ctrl settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.bistCtrl[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-laneConfig", &len); if ((!data) || (len != 45)) { pr_err("%s:%d, Unable to read Phy lane configure settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.laneCfg[i] = data[i]; panel_data->panel_info.mipi.dsi_phy_db = &phy_params; fbc_enabled = of_property_read_bool(np, "qcom,fbc-enabled"); if (fbc_enabled) { pr_debug("%s:%d FBC panel enabled.\n", __func__, __LINE__); panel_data->panel_info.fbc.enabled = 1; rc = of_property_read_u32_array(np, "qcom,fbc-mode", fbc_res, 7); panel_data->panel_info.fbc.target_bpp = (!rc ? fbc_res[0] : panel_data->panel_info.bpp); panel_data->panel_info.fbc.comp_mode = (!rc ? fbc_res[1] : 0); panel_data->panel_info.fbc.qerr_enable = (!rc ? fbc_res[2] : 0); panel_data->panel_info.fbc.cd_bias = (!rc ? fbc_res[3] : 0); panel_data->panel_info.fbc.pat_enable = (!rc ? fbc_res[4] : 0); panel_data->panel_info.fbc.vlc_enable = (!rc ? fbc_res[5] : 0); panel_data->panel_info.fbc.bflc_enable = (!rc ? fbc_res[6] : 0); rc = of_property_read_u32_array(np, "qcom,fbc-budget-ctl", fbc_res, 3); panel_data->panel_info.fbc.line_x_budget = (!rc ? fbc_res[0] : 0); panel_data->panel_info.fbc.block_x_budget = (!rc ? fbc_res[1] : 0); panel_data->panel_info.fbc.block_budget = (!rc ? fbc_res[2] : 0); rc = of_property_read_u32_array(np, "qcom,fbc-lossy-mode", fbc_res, 4); panel_data->panel_info.fbc.lossless_mode_thd = (!rc ? fbc_res[0] : 0); panel_data->panel_info.fbc.lossy_mode_thd = (!rc ? fbc_res[1] : 0); panel_data->panel_info.fbc.lossy_rgb_thd = (!rc ? fbc_res[2] : 0); panel_data->panel_info.fbc.lossy_mode_idx = (!rc ? fbc_res[3] : 0); } else { pr_debug("%s:%d Panel does not support FBC.\n", __func__, __LINE__); panel_data->panel_info.fbc.enabled = 0; panel_data->panel_info.fbc.target_bpp = panel_data->panel_info.bpp; } mdss_dsi_parse_dcs_cmds(np, &panel_data->on_cmds, "qcom,panel-on-cmds", "qcom,on-cmds-dsi-state"); mdss_dsi_parse_dcs_cmds(np, &panel_data->off_cmds, "qcom,panel-off-cmds", "qcom,off-cmds-dsi-state"); return 0; error: return -EINVAL; }
static int32_t msm_flash_get_pmic_source_info( struct device_node *of_node, struct msm_flash_ctrl_t *fctrl) { int32_t rc = 0; uint32_t count = 0, i = 0; struct device_node *flash_src_node = NULL; struct device_node *torch_src_node = NULL; if (of_get_property(of_node, "qcom,flash-source", &count)) { count /= sizeof(uint32_t); CDBG("count %d\n", count); if (count > MAX_LED_TRIGGERS) { pr_err("invalid count\n"); return -EINVAL; } fctrl->flash_num_sources = count; CDBG("%s:%d flash_num_sources = %d", __func__, __LINE__, fctrl->flash_num_sources); for (i = 0; i < count; i++) { flash_src_node = of_parse_phandle(of_node, "qcom,flash-source", i); if (!flash_src_node) { pr_err("flash_src_node NULL\n"); continue; } rc = of_property_read_string(flash_src_node, "qcom,default-led-trigger", &fctrl->flash_trigger_name[i]); if (rc < 0) { rc = of_property_read_string(flash_src_node, "linux,default-trigger", &fctrl->flash_trigger_name[i]); if (rc < 0) { pr_err("default-trigger read failed\n"); of_node_put(flash_src_node); continue; } } CDBG("default trigger %s\n", fctrl->flash_trigger_name[i]); /* Read operational-current */ rc = of_property_read_u32(flash_src_node, "qcom,current", &fctrl->flash_op_current[i]); if (rc < 0) { pr_err("current: read failed\n"); of_node_put(flash_src_node); continue; } /* Read max-current */ rc = of_property_read_u32(flash_src_node, "qcom,max-current", &fctrl->flash_max_current[i]); if (rc < 0) { pr_err("current: read failed\n"); of_node_put(flash_src_node); continue; } of_node_put(flash_src_node); CDBG("max_current[%d] %d\n", i, fctrl->flash_op_current[i]); led_trigger_register_simple( fctrl->flash_trigger_name[i], &fctrl->flash_trigger[i]); } if (fctrl->flash_driver_type == FLASH_DRIVER_DEFAULT) fctrl->flash_driver_type = FLASH_DRIVER_PMIC; CDBG("%s:%d fctrl->flash_driver_type = %d", __func__, __LINE__, fctrl->flash_driver_type); } if (of_get_property(of_node, "qcom,torch-source", &count)) { count /= sizeof(uint32_t); CDBG("count %d\n", count); if (count > MAX_LED_TRIGGERS) { pr_err("invalid count\n"); return -EINVAL; } fctrl->torch_num_sources = count; CDBG("%s:%d torch_num_sources = %d", __func__, __LINE__, fctrl->torch_num_sources); for (i = 0; i < count; i++) { torch_src_node = of_parse_phandle(of_node, "qcom,torch-source", i); if (!torch_src_node) { pr_err("torch_src_node NULL\n"); continue; } rc = of_property_read_string(torch_src_node, "qcom,default-led-trigger", &fctrl->torch_trigger_name[i]); if (rc < 0) { rc = of_property_read_string(torch_src_node, "linux,default-trigger", &fctrl->torch_trigger_name[i]); if (rc < 0) { pr_err("default-trigger read failed\n"); of_node_put(torch_src_node); continue; } } CDBG("default trigger %s\n", fctrl->torch_trigger_name[i]); /* Read operational-current */ rc = of_property_read_u32(torch_src_node, "qcom,current", &fctrl->torch_op_current[i]); if (rc < 0) { pr_err("current: read failed\n"); of_node_put(torch_src_node); continue; } /* Read max-current */ rc = of_property_read_u32(torch_src_node, "qcom,max-current", &fctrl->torch_max_current[i]); if (rc < 0) { pr_err("current: read failed\n"); of_node_put(torch_src_node); continue; } of_node_put(torch_src_node); CDBG("max_current[%d] %d\n", i, fctrl->torch_op_current[i]); led_trigger_register_simple( fctrl->torch_trigger_name[i], &fctrl->torch_trigger[i]); } if (fctrl->flash_driver_type == FLASH_DRIVER_DEFAULT) fctrl->flash_driver_type = FLASH_DRIVER_PMIC; CDBG("%s:%d fctrl->flash_driver_type = %d", __func__, __LINE__, fctrl->flash_driver_type); } return 0; }
static void __init fill_ebus_child(struct device_node *dp, struct linux_ebus_child *dev, int non_standard_regs) { struct of_device *op; int *regs; int i, len; dev->prom_node = dp; printk(" (%s)", dp->name); regs = of_get_property(dp, "reg", &len); if (!regs) dev->num_addrs = 0; else dev->num_addrs = len / sizeof(regs[0]); if (non_standard_regs) { /* This is to handle reg properties which are not * in the parent relative format. One example are * children of the i2c device on CompactPCI systems. * * So, for such devices we just record the property * raw in the child resources. */ for (i = 0; i < dev->num_addrs; i++) dev->resource[i].start = regs[i]; } else { for (i = 0; i < dev->num_addrs; i++) { int rnum = regs[i]; if (rnum >= dev->parent->num_addrs) { prom_printf("UGH: property for %s was %d, need < %d\n", dp->name, len, dev->parent->num_addrs); prom_halt(); } dev->resource[i].start = dev->parent->resource[i].start; dev->resource[i].end = dev->parent->resource[i].end; dev->resource[i].flags = IORESOURCE_MEM; dev->resource[i].name = dp->name; } } op = of_find_device_by_node(dp); if (!op) { dev->num_irqs = 0; } else { dev->num_irqs = op->num_irqs; for (i = 0; i < dev->num_irqs; i++) dev->irqs[i] = op->irqs[i]; } if (!dev->num_irqs) { /* * Oh, well, some PROMs don't export interrupts * property to children of EBus devices... * * Be smart about PS/2 keyboard and mouse. */ if (!strcmp(dev->parent->prom_node->name, "8042")) { if (!strcmp(dev->prom_node->name, "kb_ps2")) { dev->num_irqs = 1; dev->irqs[0] = dev->parent->irqs[0]; } else { dev->num_irqs = 1; dev->irqs[0] = dev->parent->irqs[1]; } } } }
int msm_camera_get_dt_gpio_req_tbl(struct device_node *of_node, struct msm_camera_gpio_conf *gconf, uint16_t *gpio_array, uint16_t gpio_array_size) { int rc = 0, i = 0; uint32_t count = 0; uint32_t *val_array = NULL; if (!of_get_property(of_node, "qcom,gpio-req-tbl-num", &count)) return 0; count /= sizeof(uint32_t); if (!count) { pr_err("%s qcom,gpio-req-tbl-num 0\n", __func__); return 0; } val_array = kzalloc(sizeof(uint32_t) * count, GFP_KERNEL); if (!val_array) { pr_err("%s failed %d\n", __func__, __LINE__); return -ENOMEM; } gconf->cam_gpio_req_tbl = kzalloc(sizeof(struct gpio) * count, GFP_KERNEL); if (!gconf->cam_gpio_req_tbl) { pr_err("%s failed %d\n", __func__, __LINE__); rc = -ENOMEM; goto ERROR1; } gconf->cam_gpio_req_tbl_size = count; rc = of_property_read_u32_array(of_node, "qcom,gpio-req-tbl-num", val_array, count); if (rc < 0) { pr_err("%s failed %d\n", __func__, __LINE__); goto ERROR2; } for (i = 0; i < count; i++) { if (val_array[i] >= gpio_array_size) { pr_err("%s gpio req tbl index %d invalid\n", __func__, val_array[i]); rc = -EINVAL; goto ERROR2; } gconf->cam_gpio_req_tbl[i].gpio = gpio_array[val_array[i]]; CDBG("%s cam_gpio_req_tbl[%d].gpio = %d\n", __func__, i, gconf->cam_gpio_req_tbl[i].gpio); } rc = of_property_read_u32_array(of_node, "qcom,gpio-req-tbl-flags", val_array, count); if (rc < 0) { pr_err("%s failed %d\n", __func__, __LINE__); goto ERROR2; } for (i = 0; i < count; i++) { gconf->cam_gpio_req_tbl[i].flags = val_array[i]; CDBG("%s cam_gpio_req_tbl[%d].flags = %ld\n", __func__, i, gconf->cam_gpio_req_tbl[i].flags); } for (i = 0; i < count; i++) { rc = of_property_read_string_index(of_node, "qcom,gpio-req-tbl-label", i, &gconf->cam_gpio_req_tbl[i].label); CDBG("%s cam_gpio_req_tbl[%d].label = %s\n", __func__, i, gconf->cam_gpio_req_tbl[i].label); if (rc < 0) { pr_err("%s failed %d\n", __func__, __LINE__); goto ERROR2; } } kfree(val_array); return rc; ERROR2: kfree(gconf->cam_gpio_req_tbl); ERROR1: kfree(val_array); gconf->cam_gpio_req_tbl_size = 0; return rc; }
static int __devinit myri_sbus_probe(struct platform_device *op) { struct device_node *dp = op->dev.of_node; static unsigned version_printed; struct net_device *dev; struct myri_eth *mp; const void *prop; static int num; int i, len; DET(("myri_ether_init(%p,%d):\n", op, num)); dev = alloc_etherdev(sizeof(struct myri_eth)); if (!dev) return -ENOMEM; if (version_printed++ == 0) printk(version); SET_NETDEV_DEV(dev, &op->dev); mp = netdev_priv(dev); spin_lock_init(&mp->irq_lock); mp->myri_op = op; /* Clean out skb arrays. */ for (i = 0; i < (RX_RING_SIZE + 1); i++) mp->rx_skbs[i] = NULL; for (i = 0; i < TX_RING_SIZE; i++) mp->tx_skbs[i] = NULL; /* First check for EEPROM information. */ prop = of_get_property(dp, "myrinet-eeprom-info", &len); if (prop) memcpy(&mp->eeprom, prop, sizeof(struct myri_eeprom)); if (!prop) { /* No eeprom property, must cook up the values ourselves. */ DET(("No EEPROM: ")); mp->eeprom.bus_type = BUS_TYPE_SBUS; mp->eeprom.cpuvers = of_getintprop_default(dp, "cpu_version", 0); mp->eeprom.cval = of_getintprop_default(dp, "clock_value", 0); mp->eeprom.ramsz = of_getintprop_default(dp, "sram_size", 0); if (!mp->eeprom.cpuvers) mp->eeprom.cpuvers = CPUVERS_2_3; if (mp->eeprom.cpuvers < CPUVERS_3_0) mp->eeprom.cval = 0; if (!mp->eeprom.ramsz) mp->eeprom.ramsz = (128 * 1024); prop = of_get_property(dp, "myrinet-board-id", &len); if (prop) memcpy(&mp->eeprom.id[0], prop, 6); else set_boardid_from_idprom(mp, num); prop = of_get_property(dp, "fpga_version", &len); if (prop) memcpy(&mp->eeprom.fvers[0], prop, 32); else memset(&mp->eeprom.fvers[0], 0, 32); if (mp->eeprom.cpuvers == CPUVERS_4_1) { if (mp->eeprom.ramsz == (128 * 1024)) mp->eeprom.ramsz = (256 * 1024); if ((mp->eeprom.cval == 0x40414041) || (mp->eeprom.cval == 0x90449044)) mp->eeprom.cval = 0x50e450e4; } } #ifdef DEBUG_DETECT dump_eeprom(mp); #endif for (i = 0; i < 6; i++) dev->dev_addr[i] = mp->eeprom.id[i]; determine_reg_space_size(mp); /* Map in the MyriCOM register/localram set. */ if (mp->eeprom.cpuvers < CPUVERS_4_0) { /* XXX Makes no sense, if control reg is non-existant this * XXX driver cannot function at all... maybe pre-4.0 is * XXX only a valid version for PCI cards? Ask feldy... */ DET(("Mapping regs for cpuvers < CPUVERS_4_0\n")); mp->regs = of_ioremap(&op->resource[0], 0, mp->reg_size, "MyriCOM Regs"); if (!mp->regs) { printk("MyriCOM: Cannot map MyriCOM registers.\n"); goto err; } mp->lanai = mp->regs + (256 * 1024); mp->lregs = mp->lanai + (0x10000 * 2); } else { DET(("Mapping regs for cpuvers >= CPUVERS_4_0\n")); mp->cregs = of_ioremap(&op->resource[0], 0, PAGE_SIZE, "MyriCOM Control Regs"); mp->lregs = of_ioremap(&op->resource[0], (256 * 1024), PAGE_SIZE, "MyriCOM LANAI Regs"); mp->lanai = of_ioremap(&op->resource[0], (512 * 1024), mp->eeprom.ramsz, "MyriCOM SRAM"); } DET(("Registers mapped: cregs[%p] lregs[%p] lanai[%p]\n", mp->cregs, mp->lregs, mp->lanai)); if (mp->eeprom.cpuvers >= CPUVERS_4_0) mp->shmem_base = 0xf000; else mp->shmem_base = 0x8000; DET(("Shared memory base is %04x, ", mp->shmem_base)); mp->shmem = (struct myri_shmem __iomem *) (mp->lanai + (mp->shmem_base * 2)); DET(("shmem mapped at %p\n", mp->shmem)); mp->rqack = &mp->shmem->channel.recvqa; mp->rq = &mp->shmem->channel.recvq; mp->sq = &mp->shmem->channel.sendq; /* Reset the board. */ DET(("Resetting LANAI\n")); myri_reset_off(mp->lregs, mp->cregs); myri_reset_on(mp->cregs); /* Turn IRQ's off. */ myri_disable_irq(mp->lregs, mp->cregs); /* Reset once more. */ myri_reset_on(mp->cregs); /* Get the supported DVMA burst sizes from our SBUS. */ mp->myri_bursts = of_getintprop_default(dp->parent, "burst-sizes", 0x00); if (!sbus_can_burst64()) mp->myri_bursts &= ~(DMA_BURST64); DET(("MYRI bursts %02x\n", mp->myri_bursts)); /* Encode SBUS interrupt level in second control register. */ i = of_getintprop_default(dp, "interrupts", 0); if (i == 0) i = 4; DET(("prom_getint(interrupts)==%d, irqlvl set to %04x\n", i, (1 << i))); sbus_writel((1 << i), mp->cregs + MYRICTRL_IRQLVL); mp->dev = dev; dev->watchdog_timeo = 5*HZ; dev->irq = op->archdata.irqs[0]; dev->netdev_ops = &myri_ops; /* Register interrupt handler now. */ DET(("Requesting MYRIcom IRQ line.\n")); if (request_irq(dev->irq, myri_interrupt, IRQF_SHARED, "MyriCOM Ethernet", (void *) dev)) { printk("MyriCOM: Cannot register interrupt handler.\n"); goto err; } dev->mtu = MYRINET_MTU; dev->header_ops = &myri_header_ops; dev->hard_header_len = (ETH_HLEN + MYRI_PAD_LEN); /* Load code onto the LANai. */ DET(("Loading LANAI firmware\n")); if (myri_load_lanai(mp)) { printk(KERN_ERR "MyriCOM: Cannot Load LANAI firmware.\n"); goto err_free_irq; } if (register_netdev(dev)) { printk("MyriCOM: Cannot register device.\n"); goto err_free_irq; } dev_set_drvdata(&op->dev, mp); num++; printk("%s: MyriCOM MyriNET Ethernet %pM\n", dev->name, dev->dev_addr); return 0; err_free_irq: free_irq(dev->irq, dev); err: /* This will also free the co-allocated private data*/ free_netdev(dev); return -ENODEV; }
void rtas_progress(char *s, unsigned short hex) { struct device_node *root; int width; const int *p; char *os; static int display_character, set_indicator; static int display_width, display_lines, form_feed; static const int *row_width; static DEFINE_SPINLOCK(progress_lock); static int current_line; static int pending_newline = 0; /* did last write end with unprinted newline? */ if (!rtas.base) return; if (display_width == 0) { display_width = 0x10; if ((root = of_find_node_by_path("/rtas"))) { if ((p = of_get_property(root, "ibm,display-line-length", NULL))) display_width = *p; if ((p = of_get_property(root, "ibm,form-feed", NULL))) form_feed = *p; if ((p = of_get_property(root, "ibm,display-number-of-lines", NULL))) display_lines = *p; row_width = of_get_property(root, "ibm,display-truncation-length", NULL); of_node_put(root); } display_character = rtas_token("display-character"); set_indicator = rtas_token("set-indicator"); } if (display_character == RTAS_UNKNOWN_SERVICE) { /* use hex display if available */ if (set_indicator != RTAS_UNKNOWN_SERVICE) rtas_call(set_indicator, 3, 1, NULL, 6, 0, hex); return; } spin_lock(&progress_lock); /* * Last write ended with newline, but we didn't print it since * it would just clear the bottom line of output. Print it now * instead. * * If no newline is pending and form feed is supported, clear the * display with a form feed; otherwise, print a CR to start output * at the beginning of the line. */ if (pending_newline) { rtas_call(display_character, 1, 1, NULL, '\r'); rtas_call(display_character, 1, 1, NULL, '\n'); pending_newline = 0; } else { current_line = 0; if (form_feed) rtas_call(display_character, 1, 1, NULL, (char)form_feed); else rtas_call(display_character, 1, 1, NULL, '\r'); } if (row_width) width = row_width[current_line]; else width = display_width; os = s; while (*os) { if (*os == '\n' || *os == '\r') { /* If newline is the last character, save it * until next call to avoid bumping up the * display output. */ if (*os == '\n' && !os[1]) { pending_newline = 1; current_line++; if (current_line > display_lines-1) current_line = display_lines-1; spin_unlock(&progress_lock); return; } /* RTAS wants CR-LF, not just LF */ if (*os == '\n') { rtas_call(display_character, 1, 1, NULL, '\r'); rtas_call(display_character, 1, 1, NULL, '\n'); } else { /* CR might be used to re-draw a line, so we'll * leave it alone and not add LF. */ rtas_call(display_character, 1, 1, NULL, *os); } if (row_width) width = row_width[current_line]; else width = display_width; } else { width--; rtas_call(display_character, 1, 1, NULL, *os); } os++; /* if we overwrite the screen length */ if (width <= 0) while ((*os != 0) && (*os != '\n') && (*os != '\r')) os++; } spin_unlock(&progress_lock); }
int default_machine_kexec_prepare(struct kimage *image) { int i; unsigned long begin, end; /* limits of segment */ unsigned long low, high; /* limits of blocked memory range */ struct device_node *node; const unsigned long *basep; const unsigned int *sizep; if (!ppc_md.hpte_clear_all) return -ENOENT; /* * Since we use the kernel fault handlers and paging code to * handle the virtual mode, we must make sure no destination * overlaps kernel static data or bss. */ for (i = 0; i < image->nr_segments; i++) if (image->segment[i].mem < __pa(_end)) return -ETXTBSY; /* * For non-LPAR, we absolutely can not overwrite the mmu hash * table, since we are still using the bolted entries in it to * do the copy. Check that here. * * It is safe if the end is below the start of the blocked * region (end <= low), or if the beginning is after the * end of the blocked region (begin >= high). Use the * boolean identity !(a || b) === (!a && !b). */ if (htab_address) { low = __pa(htab_address); high = low + htab_size_bytes; for (i = 0; i < image->nr_segments; i++) { begin = image->segment[i].mem; end = begin + image->segment[i].memsz; if ((begin < high) && (end > low)) return -ETXTBSY; } } /* We also should not overwrite the tce tables */ for (node = of_find_node_by_type(NULL, "pci"); node != NULL; node = of_find_node_by_type(node, "pci")) { basep = of_get_property(node, "linux,tce-base", NULL); sizep = of_get_property(node, "linux,tce-size", NULL); if (basep == NULL || sizep == NULL) continue; low = *basep; high = low + (*sizep); for (i = 0; i < image->nr_segments; i++) { begin = image->segment[i].mem; end = begin + image->segment[i].memsz; if ((begin < high) && (end > low)) return -ETXTBSY; } } return 0; }
static int uec_mdio_probe(struct of_device *ofdev, const struct of_device_id *match) { struct device *device = &ofdev->dev; struct device_node *np = ofdev->node, *tempnp = NULL; struct device_node *child = NULL; struct ucc_mii_mng __iomem *regs; struct mii_bus *new_bus; struct resource res; int k, err = 0; new_bus = kzalloc(sizeof(struct mii_bus), GFP_KERNEL); if (NULL == new_bus) return -ENOMEM; new_bus->name = "UCC Ethernet Controller MII Bus"; new_bus->read = &uec_mdio_read; new_bus->write = &uec_mdio_write; new_bus->reset = &uec_mdio_reset; memset(&res, 0, sizeof(res)); err = of_address_to_resource(np, 0, &res); if (err) goto reg_map_fail; snprintf(new_bus->id, MII_BUS_ID_SIZE, "%x", res.start); new_bus->irq = kmalloc(32 * sizeof(int), GFP_KERNEL); if (NULL == new_bus->irq) { err = -ENOMEM; goto reg_map_fail; } for (k = 0; k < 32; k++) new_bus->irq[k] = PHY_POLL; while ((child = of_get_next_child(np, child)) != NULL) { int irq = irq_of_parse_and_map(child, 0); if (irq != NO_IRQ) { const u32 *id = of_get_property(child, "reg", NULL); new_bus->irq[*id] = irq; } } /* Set the base address */ regs = ioremap(res.start, sizeof(struct ucc_mii_mng)); if (NULL == regs) { err = -ENOMEM; goto ioremap_fail; } new_bus->priv = (void __force *)regs; new_bus->dev = device; dev_set_drvdata(device, new_bus); /* Read MII management master from device tree */ while ((tempnp = of_find_compatible_node(tempnp, "network", "ucc_geth")) != NULL) { struct resource tempres; err = of_address_to_resource(tempnp, 0, &tempres); if (err) goto bus_register_fail; /* if our mdio regs fall within this UCC regs range */ if ((res.start >= tempres.start) && (res.end <= tempres.end)) { /* set this UCC to be the MII master */ const u32 *id; id = of_get_property(tempnp, "cell-index", NULL); if (!id) { id = of_get_property(tempnp, "device-id", NULL); if (!id) goto bus_register_fail; } ucc_set_qe_mux_mii_mng(*id - 1); /* assign the TBI an address which won't * conflict with the PHYs */ out_be32(®s->utbipar, UTBIPAR_INIT_TBIPA); break; } } err = mdiobus_register(new_bus); if (0 != err) { printk(KERN_ERR "%s: Cannot register as MDIO bus\n", new_bus->name); goto bus_register_fail; } return 0; bus_register_fail: iounmap(regs); ioremap_fail: kfree(new_bus->irq); reg_map_fail: kfree(new_bus); return err; }
static int mv_otg_probe(struct platform_device *pdev) { struct mv_usb_platform_data *pdata = pdev->dev.platform_data; struct mv_otg *mvotg; struct usb_otg *otg; struct resource *r; int retval = 0, i; struct device_node *np = pdev->dev.of_node; const __be32 *prop; unsigned int proplen; if (pdata == NULL) { dev_err(&pdev->dev, "failed to get platform data\n"); return -ENODEV; } mvotg = devm_kzalloc(&pdev->dev, sizeof(*mvotg), GFP_KERNEL); if (!mvotg) { dev_err(&pdev->dev, "failed to allocate memory!\n"); return -ENOMEM; } otg = devm_kzalloc(&pdev->dev, sizeof(*otg), GFP_KERNEL); if (!otg) return -ENOMEM; platform_set_drvdata(pdev, mvotg); mvotg->pdev = pdev; mvotg->pdata = pdata; mvotg->clk = devm_clk_get(&pdev->dev, NULL); if (IS_ERR(mvotg->clk)) return PTR_ERR(mvotg->clk); clk_prepare(mvotg->clk); mvotg->qwork = create_singlethread_workqueue("mv_otg_queue"); if (!mvotg->qwork) { dev_dbg(&pdev->dev, "cannot create workqueue for OTG\n"); return -ENOMEM; } INIT_DELAYED_WORK(&mvotg->work, mv_otg_work); /* OTG common part */ mvotg->pdev = pdev; mvotg->phy.dev = &pdev->dev; mvotg->phy.type = USB_PHY_TYPE_USB2; mvotg->phy.otg = otg; mvotg->phy.label = driver_name; mvotg->phy.state = OTG_STATE_UNDEFINED; otg->phy = &mvotg->phy; otg->set_host = mv_otg_set_host; otg->set_peripheral = mv_otg_set_peripheral; otg->set_vbus = mv_otg_set_vbus; mv_otg_phy_bind_device(mvotg); for (i = 0; i < OTG_TIMER_NUM; i++) init_timer(&mvotg->otg_ctrl.timer[i]); r = platform_get_resource(mvotg->pdev, IORESOURCE_MEM, 0); if (r == NULL) { dev_err(&pdev->dev, "no I/O memory resource defined\n"); retval = -ENODEV; goto err_destroy_workqueue; } mvotg->cap_regs = devm_ioremap(&pdev->dev, r->start, resource_size(r)); if (mvotg->cap_regs == NULL) { dev_err(&pdev->dev, "failed to map I/O memory\n"); retval = -EFAULT; goto err_destroy_workqueue; } mvotg->outer_phy = devm_usb_get_phy_dev(&pdev->dev, MV_USB2_PHY_INDEX); if (IS_ERR_OR_NULL(mvotg->outer_phy)) { retval = PTR_ERR(mvotg->outer_phy); if (retval != -EPROBE_DEFER) dev_err(&pdev->dev, "can not find outer phy\n"); goto err_destroy_workqueue; } /* we will acces controller register, so enable the udc controller */ retval = mv_otg_enable_internal(mvotg); if (retval) { dev_err(&pdev->dev, "mv otg enable error %d\n", retval); goto err_destroy_workqueue; } mvotg->op_regs = (struct mv_otg_regs __iomem *) ((unsigned long) mvotg->cap_regs + (readl(mvotg->cap_regs) & CAPLENGTH_MASK)); if (pdata->extern_attr & (MV_USB_HAS_VBUS_DETECTION | MV_USB_HAS_IDPIN_DETECTION)) { mvotg->notifier.notifier_call = mv_otg_notifier_callback; pxa_usb_register_notifier(mvotg->pdata->id, &mvotg->notifier); if (pdata->extern_attr & MV_USB_HAS_VBUS_DETECTION) { mvotg->clock_gating = 1; pxa_usb_extern_call(mvotg->pdata->id, vbus, init); } if (pdata->extern_attr & MV_USB_HAS_IDPIN_DETECTION) pxa_usb_extern_call(mvotg->pdata->id, idpin, init); } if (pdata->disable_otg_clock_gating) mvotg->clock_gating = 0; mv_otg_reset(mvotg); mv_otg_init_irq(mvotg); r = platform_get_resource(mvotg->pdev, IORESOURCE_IRQ, 0); if (r == NULL) { dev_err(&pdev->dev, "no IRQ resource defined\n"); retval = -ENODEV; goto err_disable_clk; } mvotg->irq = r->start; if (devm_request_irq(&pdev->dev, mvotg->irq, mv_otg_irq, IRQF_SHARED, driver_name, mvotg)) { dev_err(&pdev->dev, "Request irq %d for OTG failed\n", mvotg->irq); mvotg->irq = 0; retval = -ENODEV; goto err_disable_clk; } retval = usb_add_phy_dev(&mvotg->phy); if (retval < 0) { dev_err(&pdev->dev, "can't register transceiver, %d\n", retval); goto err_disable_clk; } prop = of_get_property(np, "lpm-qos", &proplen); if (!prop) { pr_err("lpm-qos config in DT for mv_otg is not defined\n"); goto err_disable_clk; } else mvotg->lpm_qos = be32_to_cpup(prop); mvotg->qos_idle.name = mvotg->pdev->name; pm_qos_add_request(&mvotg->qos_idle, PM_QOS_CPUIDLE_BLOCK, PM_QOS_CPUIDLE_BLOCK_DEFAULT_VALUE); retval = sysfs_create_group(&pdev->dev.kobj, &inputs_attr_group); if (retval < 0) { dev_dbg(&pdev->dev, "Can't register sysfs attr group: %d\n", retval); goto err_remove_otg_phy; } spin_lock_init(&mvotg->wq_lock); if (spin_trylock(&mvotg->wq_lock)) { mv_otg_run_state_machine(mvotg, 2 * HZ); spin_unlock(&mvotg->wq_lock); } dev_info(&pdev->dev, "successful probe OTG device %s clock gating.\n", mvotg->clock_gating ? "with" : "without"); device_init_wakeup(&pdev->dev, 1); return 0; err_remove_otg_phy: usb_remove_phy(&mvotg->phy); pm_qos_remove_request(&mvotg->qos_idle); err_disable_clk: mv_otg_disable_internal(mvotg); if (pdata->extern_attr & (MV_USB_HAS_VBUS_DETECTION | MV_USB_HAS_IDPIN_DETECTION)) pxa_usb_unregister_notifier(mvotg->pdata->id, &mvotg->notifier); err_destroy_workqueue: flush_workqueue(mvotg->qwork); destroy_workqueue(mvotg->qwork); return retval; }
/* * Translate OpenFirmware node properties into platform_data */ static int gpio_keys_get_devtree_pdata(struct device *dev, struct gpio_keys_platform_data *pdata) { struct device_node *node, *pp; int i; struct gpio_keys_button *buttons; u32 reg; node = dev->of_node; if (node == NULL) return -ENODEV; memset(pdata, 0, sizeof *pdata); pdata->rep = !!of_get_property(node, "autorepeat", NULL); /* First count the subnodes */ pdata->nbuttons = 0; pp = NULL; while ((pp = of_get_next_child(node, pp))) pdata->nbuttons++; if (pdata->nbuttons == 0) return -ENODEV; buttons = kzalloc(pdata->nbuttons * (sizeof *buttons), GFP_KERNEL); if (!buttons) return -ENOMEM; pp = NULL; i = 0; while ((pp = of_get_next_child(node, pp))) { enum of_gpio_flags flags; if (!of_find_property(pp, "gpios", NULL)) { pdata->nbuttons--; dev_warn(dev, "Found button without gpios\n"); continue; } buttons[i].gpio = of_get_gpio_flags(pp, 0, &flags); buttons[i].active_low = flags & OF_GPIO_ACTIVE_LOW; if (of_property_read_u32(pp, "linux,code", ®)) { dev_err(dev, "Button without keycode: 0x%x\n", buttons[i].gpio); goto out_fail; } buttons[i].code = reg; buttons[i].desc = of_get_property(pp, "label", NULL); if (of_property_read_u32(pp, "linux,input-type", ®) == 0) buttons[i].type = reg; else buttons[i].type = EV_KEY; buttons[i].wakeup = !!of_get_property(pp, "gpio-key,wakeup", NULL); if (of_property_read_u32(pp, "debounce-interval", ®) == 0) buttons[i].debounce_interval = reg; else buttons[i].debounce_interval = 5; i++; } pdata->buttons = buttons; return 0; out_fail: kfree(buttons); return -ENODEV; }
void socfpga_init_ocram_ecc(void) { struct device_node *np; const __be32 *prop; u32 ocr_edac_addr, iram_addr, len; void __iomem *mapped_ocr_edac_addr; size_t size; struct gen_pool *gp; if (of_machine_is_compatible("altr,socfpga-arria10")) { if (socfpga_init_arria10_ocram_ecc() == 0) pr_alert("SOCFPGA: Success Initializing OCRAM ECC for Arria10"); return; } np = of_find_compatible_node(NULL, NULL, "altr,ocram-edac"); if (!np) { pr_err("SOCFPGA: Unable to find altr,ocram-edac in dtb\n"); return; } prop = of_get_property(np, "reg", &size); ocr_edac_addr = be32_to_cpup(prop++); len = be32_to_cpup(prop); if (!prop || size < sizeof(*prop)) { pr_err("SOCFPGA: Unable to find OCRAM ECC mapping in dtb\n"); return; } gp = of_gen_pool_get(np, "iram", 0); if (!gp) { pr_err("SOCFPGA: OCRAM cannot find gen pool\n"); return; } np = of_find_compatible_node(NULL, NULL, "mmio-sram"); if (!np) { pr_err("SOCFPGA: Unable to find mmio-sram in dtb\n"); return; } /* Determine the OCRAM address and size */ prop = of_get_property(np, "reg", &size); iram_addr = be32_to_cpup(prop++); len = be32_to_cpup(prop); if (!prop || size < sizeof(*prop)) { pr_err("SOCFPGA: Unable to find OCRAM mapping in dtb\n"); return; } iram_addr = gen_pool_alloc(gp, len); if (iram_addr == 0) { pr_err("SOCFPGA: cannot alloc from gen pool\n"); return; } memset((void *)iram_addr, 0, len); mapped_ocr_edac_addr = ioremap(ocr_edac_addr, 4); gen_pool_free(gp, iram_addr, len); /* Clear any pending OCRAM ECC interrupts, then enable ECC */ writel(0x18, mapped_ocr_edac_addr); writel(0x19, mapped_ocr_edac_addr); iounmap(mapped_ocr_edac_addr); pr_alert("SOCFPGA: Success Initializing OCRAM"); return; }
static int sensor_imx240_power_setpin(struct device *dev) { struct exynos_platform_fimc_is_sensor *pdata; struct device_node *dnode; int gpio_comp_en = 0, gpio_comp_rst = 0; int gpio_none = 0; int gpio_reset = 0; int gpios_cam_en = -EINVAL; #ifdef CONFIG_OIS_USE int gpios_ois_en = 0; #endif BUG_ON(!dev); BUG_ON(!dev->platform_data); dnode = dev->of_node; pdata = dev->platform_data; gpio_comp_en = of_get_named_gpio(dnode, "gpios_comp_en", 0); if (!gpio_is_valid(gpio_comp_en)) { dev_err(dev, "failed to get main comp en gpio\n"); } else { gpio_request_one(gpio_comp_en, GPIOF_OUT_INIT_LOW, "CAM_GPIO_OUTPUT_LOW"); gpio_free(gpio_comp_en); } gpio_comp_rst = of_get_named_gpio(dnode, "gpios_comp_reset", 0); if (!gpio_is_valid(gpio_comp_rst)) { dev_err(dev, "failed to get main comp reset gpio\n"); } else { gpio_request_one(gpio_comp_rst, GPIOF_OUT_INIT_LOW, "CAM_GPIO_OUTPUT_LOW"); gpio_free(gpio_comp_rst); } gpio_reset = of_get_named_gpio(dnode, "gpio_reset", 0); if (!gpio_is_valid(gpio_reset)) { dev_err(dev, "failed to get PIN_RESET\n"); return -EINVAL; } else { gpio_request_one(gpio_reset, GPIOF_OUT_INIT_LOW, "CAM_GPIO_OUTPUT_LOW"); gpio_free(gpio_reset); } if (of_get_property(dnode, "gpios_cam_en", NULL)) { gpios_cam_en = of_get_named_gpio(dnode, "gpios_cam_en", 0); if (!gpio_is_valid(gpios_cam_en)) { dev_err(dev, "failed to get main cam en gpio\n"); } else { gpio_request_one(gpios_cam_en, GPIOF_OUT_INIT_LOW, "CAM_GPIO_OUTPUT_LOW"); gpio_free(gpios_cam_en); } } #ifdef CONFIG_OIS_USE gpios_ois_en = of_get_named_gpio(dnode, "gpios_ois_en", 0); pdata->pin_ois_en = gpios_ois_en; if (!gpio_is_valid(gpios_ois_en)) { dev_err(dev, "failed to get ois en gpio\n"); } else { gpio_request_one(gpios_ois_en, GPIOF_OUT_INIT_LOW, "CAM_GPIO_OUTPUT_LOW"); gpio_free(gpios_ois_en); } #endif if (gpio_is_valid(gpios_cam_en)) { SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 0, gpios_cam_en, 0, NULL, 0, PIN_OUTPUT_HIGH); } else { SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 0, gpio_none, 0, "CAM_SEN_A2.8V_AP", 0, PIN_REGULATOR_ON); } SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 1, gpio_none, 0, "CAM_SEN_CORE_1.2V_AP", 0, PIN_REGULATOR_ON); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 2, gpio_none, 0, "CAM_AF_2.8V_AP", 2000, PIN_REGULATOR_ON); #ifdef CONFIG_OIS_USE SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 3, gpios_ois_en, 0, NULL, 0, PIN_OUTPUT_HIGH); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 4, gpio_none, 0, "OIS_VM_2.8V", 0, PIN_REGULATOR_ON); #endif SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 5, gpio_none, 0, "CAM_IO_1.8V_AP", 0, PIN_REGULATOR_ON); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 6, gpio_none, 0, "VDDA_1.8V_COMP", 0, PIN_REGULATOR_ON); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 7, gpio_comp_en, 0, NULL, 150, PIN_OUTPUT_HIGH); if (pdata->companion_use_pmic) { SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 8, gpio_none, 0, "VDD_MIPI_1.0V_COMP", 0, PIN_REGULATOR_ON); } SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 9, gpio_comp_rst, 0, NULL, 0, PIN_OUTPUT_HIGH); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 10, gpio_none, 0, "ch", 0, PIN_FUNCTION); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 11, gpio_none, 0, "af", 0, PIN_FUNCTION); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 12, gpio_reset, 0, NULL, 0, PIN_OUTPUT_HIGH); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_ON, 13, gpio_none, 0, NULL, 0, PIN_END); /* BACK CAMERA - POWER OFF */ SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 0, gpio_none, 0, "CAM_AF_2.8V_AP", 2000, PIN_REGULATOR_OFF); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 1, gpio_none, 0, "off", 0, PIN_FUNCTION); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 2, gpio_reset, 0, NULL, 0, PIN_OUTPUT_LOW); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 3, gpio_comp_rst, 0, NULL, 0, PIN_OUTPUT_LOW); if (pdata->companion_use_pmic) { SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 4, gpio_none, 0, "VDD_MIPI_1.0V_COMP", 0, PIN_REGULATOR_OFF); } SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 5, gpio_comp_en, 0, NULL, 0, PIN_OUTPUT_LOW); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 6, gpio_none, 0, "VDDA_1.8V_COMP", 0, PIN_REGULATOR_OFF); if (gpio_is_valid(gpios_cam_en)) { SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 7, gpios_cam_en, 0, NULL, 0, PIN_OUTPUT_LOW); } else { SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 7, gpio_none, 0, "CAM_SEN_A2.8V_AP", 0, PIN_REGULATOR_OFF); } SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 8, gpio_none, 0, "CAM_SEN_CORE_1.2V_AP", 0, PIN_REGULATOR_OFF); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 9, gpio_none, 0, "CAM_IO_1.8V_AP", 0, PIN_REGULATOR_OFF); #ifdef CONFIG_OIS_USE SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 10, gpios_ois_en, 0, NULL, 0, PIN_OUTPUT_LOW); SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 11, gpio_none, 0, "OIS_VM_2.8V", 0, PIN_REGULATOR_OFF); #endif SET_PIN(pdata, SENSOR_SCENARIO_NORMAL, GPIO_SCENARIO_OFF, 12, gpio_none, 0, NULL, 0, PIN_END); #ifdef CONFIG_OIS_USE /* OIS_FACTORY - POWER ON */ SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, 0, gpio_none, 0, "CAM_AF_2.8V_AP", 2000, PIN_REGULATOR_ON); SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, 1, gpios_ois_en, 0, NULL, 0, PIN_OUTPUT_HIGH); SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, 2, gpio_none, 0, "OIS_VM_2.8V", 0, PIN_REGULATOR_ON); SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, 3, gpio_none, 0, "CAM_IO_1.8V_AP", 0, PIN_REGULATOR_ON); SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, 4, gpio_reset, 0, NULL, 0, PIN_OUTPUT_HIGH); SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_ON, 5, gpio_none, 0, NULL, 0, PIN_END); /* OIS_FACTORY - POWER OFF */ SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, 0, gpio_none, 0, "CAM_AF_2.8V_AP", 2000, PIN_REGULATOR_OFF); SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, 1, gpio_reset, 0, NULL, 0, PIN_OUTPUT_LOW); SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, 2, gpio_none, 0, "CAM_IO_1.8V_AP", 0, PIN_REGULATOR_OFF); SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, 3, gpios_ois_en, 0, NULL, 0, PIN_OUTPUT_LOW); SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, 4, gpio_none, 0, "OIS_VM_2.8V", 0, PIN_REGULATOR_OFF); SET_PIN(pdata, SENSOR_SCENARIO_OIS_FACTORY, GPIO_SCENARIO_OFF, 5, gpio_none, 0, NULL, 0, PIN_END); #endif return 0; }
static int probe_vdd_rstr(struct device_node *node, struct msm_thermal_data *data, struct platform_device *pdev) { int ret = 0; int i = 0; int arr_size; char *key = NULL; struct device_node *child_node = NULL; rails = NULL; key = "qcom,vdd-restriction-temp"; ret = of_property_read_u32(node, key, &data->vdd_rstr_temp_degC); if (ret) goto read_node_fail; key = "qcom,vdd-restriction-temp-hysteresis"; ret = of_property_read_u32(node, key, &data->vdd_rstr_temp_hyst_degC); if (ret) goto read_node_fail; for_each_child_of_node(node, child_node) { rails_cnt++; } if (rails_cnt == 0) goto read_node_fail; if (rails_cnt >= MAX_RAILS) { pr_err("%s: Too many rails.\n", __func__); return -EFAULT; } rails = kzalloc(sizeof(struct rail) * rails_cnt, GFP_KERNEL); if (!rails) { pr_err("%s: Fail to allocate memory for rails.\n", __func__); return -ENOMEM; } i = 0; for_each_child_of_node(node, child_node) { key = "qcom,vdd-rstr-reg"; ret = of_property_read_string(child_node, key, &rails[i].name); if (ret) goto read_node_fail; key = "qcom,levels"; if (!of_get_property(child_node, key, &arr_size)) goto read_node_fail; rails[i].num_levels = arr_size/sizeof(__be32); if (rails[i].num_levels > sizeof(rails[i].levels)/sizeof(uint32_t)) { pr_err("%s: Array size too large\n", __func__); return -EFAULT; } ret = of_property_read_u32_array(child_node, key, rails[i].levels, rails[i].num_levels); if (ret) goto read_node_fail; key = "qcom,freq-req"; rails[i].freq_req = of_property_read_bool(child_node, key); if (rails[i].freq_req) rails[i].min_level = MSM_CPUFREQ_NO_LIMIT; else { key = "qcom,min-level"; ret = of_property_read_u32(child_node, key, &rails[i].min_level); if (ret) goto read_node_fail; } rails[i].curr_level = -1; rails[i].reg = NULL; i++; }
static int msm_smd_probe(struct platform_device *pdev) { uint32_t edge; char *key; int ret; uint32_t irq_offset; uint32_t irq_bitmask; uint32_t irq_line; const char *pilstr; struct interrupt_config_item *private_irq; struct device_node *node; void *irq_out_base; resource_size_t irq_out_size; struct platform_device *parent_pdev; struct resource *r; struct interrupt_config *private_intr_config; uint32_t remote_pid; node = pdev->dev.of_node; if (!pdev->dev.parent) { pr_err("%s: missing link to parent device\n", __func__); return -ENODEV; } parent_pdev = to_platform_device(pdev->dev.parent); key = "irq-reg-base"; r = platform_get_resource_byname(parent_pdev, IORESOURCE_MEM, key); if (!r) goto missing_key; irq_out_size = resource_size(r); irq_out_base = ioremap_nocache(r->start, irq_out_size); if (!irq_out_base) { pr_err("%s: ioremap_nocache() of irq_out_base addr:%pr size:%pr\n", __func__, &r->start, &irq_out_size); return -ENOMEM; } SMD_DBG("%s: %s = %p", __func__, key, irq_out_base); key = "qcom,smd-edge"; ret = of_property_read_u32(node, key, &edge); if (ret) goto missing_key; SMD_DBG("%s: %s = %d", __func__, key, edge); key = "qcom,smd-irq-offset"; ret = of_property_read_u32(node, key, &irq_offset); if (ret) goto missing_key; SMD_DBG("%s: %s = %x", __func__, key, irq_offset); key = "qcom,smd-irq-bitmask"; ret = of_property_read_u32(node, key, &irq_bitmask); if (ret) goto missing_key; SMD_DBG("%s: %s = %x", __func__, key, irq_bitmask); key = "interrupts"; irq_line = irq_of_parse_and_map(node, 0); if (!irq_line) goto missing_key; SMD_DBG("%s: %s = %d", __func__, key, irq_line); key = "qcom,pil-string"; pilstr = of_get_property(node, key, NULL); if (pilstr) SMD_DBG("%s: %s = %s", __func__, key, pilstr); private_intr_config = smd_get_intr_config(edge); if (!private_intr_config) { pr_err("%s: invalid edge\n", __func__); return -ENODEV; } private_irq = &private_intr_config->smd; private_irq->out_bit_pos = irq_bitmask; private_irq->out_offset = irq_offset; private_irq->out_base = irq_out_base; private_irq->irq_id = irq_line; remote_pid = smd_edge_to_remote_pid(edge); interrupt_stats[remote_pid].smd_interrupt_id = irq_line; ret = request_irq(irq_line, private_irq->irq_handler, IRQF_TRIGGER_RISING| IRQF_NO_SUSPEND, "smd_dev", NULL); if (ret < 0) { pr_err("%s: request_irq() failed on %d\n", __func__, irq_line); return ret; } else { ret = enable_irq_wake(irq_line); if (ret < 0) pr_err("%s: enable_irq_wake() failed on %d\n", __func__, irq_line); } if (pilstr) smd_set_edge_subsys_name(edge, pilstr); smd_set_edge_initialized(edge); smd_post_init(0, remote_pid); return 0; missing_key: pr_err("%s: missing key: %s", __func__, key); return -ENODEV; }
static int of_isp1760_probe(struct platform_device *dev) { struct isp1760 *drvdata; struct device_node *dp = dev->dev.of_node; struct resource *res; struct resource memory; int virq; resource_size_t res_len; int ret; unsigned int devflags = 0; enum of_gpio_flags gpio_flags; u32 bus_width = 0; drvdata = kzalloc(sizeof(*drvdata), GFP_KERNEL); if (!drvdata) return -ENOMEM; ret = of_address_to_resource(dp, 0, &memory); if (ret) { ret = -ENXIO; goto free_data; } res_len = resource_size(&memory); res = request_mem_region(memory.start, res_len, dev_name(&dev->dev)); if (!res) { ret = -EBUSY; goto free_data; } virq = irq_of_parse_and_map(dp, 0); if (!virq) { ret = -ENODEV; goto release_reg; } if (of_device_is_compatible(dp, "nxp,usb-isp1761")) devflags |= ISP1760_FLAG_ISP1761; /* Some systems wire up only 16 of the 32 data lines */ of_property_read_u32(dp, "bus-width", &bus_width); if (bus_width == 16) devflags |= ISP1760_FLAG_BUS_WIDTH_16; if (of_get_property(dp, "port1-otg", NULL) != NULL) devflags |= ISP1760_FLAG_OTG_EN; if (of_get_property(dp, "analog-oc", NULL) != NULL) devflags |= ISP1760_FLAG_ANALOG_OC; if (of_get_property(dp, "dack-polarity", NULL) != NULL) devflags |= ISP1760_FLAG_DACK_POL_HIGH; if (of_get_property(dp, "dreq-polarity", NULL) != NULL) devflags |= ISP1760_FLAG_DREQ_POL_HIGH; drvdata->rst_gpio = of_get_gpio_flags(dp, 0, &gpio_flags); if (gpio_is_valid(drvdata->rst_gpio)) { ret = gpio_request(drvdata->rst_gpio, dev_name(&dev->dev)); if (!ret) { if (!(gpio_flags & OF_GPIO_ACTIVE_LOW)) { devflags |= ISP1760_FLAG_RESET_ACTIVE_HIGH; gpio_direction_output(drvdata->rst_gpio, 0); } else { gpio_direction_output(drvdata->rst_gpio, 1); } } else { drvdata->rst_gpio = ret; } } drvdata->hcd = isp1760_register(memory.start, res_len, virq, IRQF_SHARED, drvdata->rst_gpio, &dev->dev, dev_name(&dev->dev), devflags); if (IS_ERR(drvdata->hcd)) { ret = PTR_ERR(drvdata->hcd); goto free_gpio; } platform_set_drvdata(dev, drvdata); return ret; free_gpio: if (gpio_is_valid(drvdata->rst_gpio)) gpio_free(drvdata->rst_gpio); release_reg: release_mem_region(memory.start, res_len); free_data: kfree(drvdata); return ret; }
static void __init fill_ebus_device(struct device_node *dp, struct linux_ebus_device *dev) { struct linux_ebus_child *child; struct of_device *op; int i, len; dev->prom_node = dp; printk(" [%s", dp->name); op = of_find_device_by_node(dp); if (!op) { dev->num_addrs = 0; dev->num_irqs = 0; } else { (void) of_get_property(dp, "reg", &len); dev->num_addrs = len / sizeof(struct linux_prom_registers); for (i = 0; i < dev->num_addrs; i++) memcpy(&dev->resource[i], &op->resource[i], sizeof(struct resource)); dev->num_irqs = op->num_irqs; for (i = 0; i < dev->num_irqs; i++) dev->irqs[i] = op->irqs[i]; } dev->ofdev.node = dp; dev->ofdev.dev.parent = &dev->bus->ofdev.dev; dev->ofdev.dev.bus = &ebus_bus_type; strcpy(dev->ofdev.dev.bus_id, dp->path_component_name); /* Register with core */ if (of_device_register(&dev->ofdev) != 0) printk(KERN_DEBUG "ebus: device registration error for %s!\n", dev->ofdev.dev.bus_id); dp = dp->child; if (dp) { printk(" ->"); dev->children = ebus_alloc(sizeof(struct linux_ebus_child)); child = dev->children; child->next = NULL; child->parent = dev; child->bus = dev->bus; fill_ebus_child(dp, child, child_regs_nonstandard(dev)); while ((dp = dp->sibling) != NULL) { child->next = ebus_alloc(sizeof(struct linux_ebus_child)); child = child->next; child->next = NULL; child->parent = dev; child->bus = dev->bus; fill_ebus_child(dp, child, child_regs_nonstandard(dev)); } } printk("]"); }
static void of_get_regulation_constraints(struct device_node *np, struct regulator_init_data **init_data, const struct regulator_desc *desc) { struct regulation_constraints *constraints = &(*init_data)->constraints; struct regulator_state *suspend_state; struct device_node *suspend_np; unsigned int mode; int ret, i, len; u32 pval; constraints->name = of_get_property(np, "regulator-name", NULL); if (!of_property_read_u32(np, "regulator-min-microvolt", &pval)) constraints->min_uV = pval; if (!of_property_read_u32(np, "regulator-max-microvolt", &pval)) constraints->max_uV = pval; /* Voltage change possible? */ if (constraints->min_uV != constraints->max_uV) constraints->valid_ops_mask |= REGULATOR_CHANGE_VOLTAGE; /* Do we have a voltage range, if so try to apply it? */ if (constraints->min_uV && constraints->max_uV) constraints->apply_uV = true; if (!of_property_read_u32(np, "regulator-microvolt-offset", &pval)) constraints->uV_offset = pval; if (!of_property_read_u32(np, "regulator-min-microamp", &pval)) constraints->min_uA = pval; if (!of_property_read_u32(np, "regulator-max-microamp", &pval)) constraints->max_uA = pval; if (!of_property_read_u32(np, "regulator-input-current-limit-microamp", &pval)) constraints->ilim_uA = pval; /* Current change possible? */ if (constraints->min_uA != constraints->max_uA) constraints->valid_ops_mask |= REGULATOR_CHANGE_CURRENT; constraints->boot_on = of_property_read_bool(np, "regulator-boot-on"); constraints->always_on = of_property_read_bool(np, "regulator-always-on"); if (!constraints->always_on) /* status change should be possible. */ constraints->valid_ops_mask |= REGULATOR_CHANGE_STATUS; constraints->pull_down = of_property_read_bool(np, "regulator-pull-down"); if (of_property_read_bool(np, "regulator-allow-bypass")) constraints->valid_ops_mask |= REGULATOR_CHANGE_BYPASS; if (of_property_read_bool(np, "regulator-allow-set-load")) constraints->valid_ops_mask |= REGULATOR_CHANGE_DRMS; ret = of_property_read_u32(np, "regulator-ramp-delay", &pval); if (!ret) { if (pval) constraints->ramp_delay = pval; else constraints->ramp_disable = true; } ret = of_property_read_u32(np, "regulator-settling-time-us", &pval); if (!ret) constraints->settling_time = pval; ret = of_property_read_u32(np, "regulator-settling-time-up-us", &pval); if (!ret) constraints->settling_time_up = pval; if (constraints->settling_time_up && constraints->settling_time) { pr_warn("%s: ambiguous configuration for settling time, ignoring 'regulator-settling-time-up-us'\n", np->name); constraints->settling_time_up = 0; } ret = of_property_read_u32(np, "regulator-settling-time-down-us", &pval); if (!ret) constraints->settling_time_down = pval; if (constraints->settling_time_down && constraints->settling_time) { pr_warn("%s: ambiguous configuration for settling time, ignoring 'regulator-settling-time-down-us'\n", np->name); constraints->settling_time_down = 0; } ret = of_property_read_u32(np, "regulator-enable-ramp-delay", &pval); if (!ret) constraints->enable_time = pval; constraints->soft_start = of_property_read_bool(np, "regulator-soft-start"); ret = of_property_read_u32(np, "regulator-active-discharge", &pval); if (!ret) { constraints->active_discharge = (pval) ? REGULATOR_ACTIVE_DISCHARGE_ENABLE : REGULATOR_ACTIVE_DISCHARGE_DISABLE; } if (!of_property_read_u32(np, "regulator-initial-mode", &pval)) { if (desc && desc->of_map_mode) { mode = desc->of_map_mode(pval); if (mode == REGULATOR_MODE_INVALID) pr_err("%s: invalid mode %u\n", np->name, pval); else constraints->initial_mode = mode; } else { pr_warn("%s: mapping for mode %d not defined\n", np->name, pval); } } len = of_property_count_elems_of_size(np, "regulator-allowed-modes", sizeof(u32)); if (len > 0) { if (desc && desc->of_map_mode) { for (i = 0; i < len; i++) { ret = of_property_read_u32_index(np, "regulator-allowed-modes", i, &pval); if (ret) { pr_err("%s: couldn't read allowed modes index %d, ret=%d\n", np->name, i, ret); break; } mode = desc->of_map_mode(pval); if (mode == REGULATOR_MODE_INVALID) pr_err("%s: invalid regulator-allowed-modes element %u\n", np->name, pval); else constraints->valid_modes_mask |= mode; } if (constraints->valid_modes_mask) constraints->valid_ops_mask |= REGULATOR_CHANGE_MODE; } else { pr_warn("%s: mode mapping not defined\n", np->name); } } if (!of_property_read_u32(np, "regulator-system-load", &pval)) constraints->system_load = pval; if (!of_property_read_u32(np, "regulator-coupled-max-spread", &pval)) constraints->max_spread = pval; constraints->over_current_protection = of_property_read_bool(np, "regulator-over-current-protection"); for (i = 0; i < ARRAY_SIZE(regulator_states); i++) { switch (i) { case PM_SUSPEND_MEM: suspend_state = &constraints->state_mem; break; case PM_SUSPEND_MAX: suspend_state = &constraints->state_disk; break; case PM_SUSPEND_ON: case PM_SUSPEND_TO_IDLE: case PM_SUSPEND_STANDBY: default: continue; } suspend_np = of_get_child_by_name(np, regulator_states[i]); if (!suspend_np || !suspend_state) continue; if (!of_property_read_u32(suspend_np, "regulator-mode", &pval)) { if (desc && desc->of_map_mode) { mode = desc->of_map_mode(pval); if (mode == REGULATOR_MODE_INVALID) pr_err("%s: invalid mode %u\n", np->name, pval); else suspend_state->mode = mode; } else { pr_warn("%s: mapping for mode %d not defined\n", np->name, pval); } } if (of_property_read_bool(suspend_np, "regulator-on-in-suspend")) suspend_state->enabled = ENABLE_IN_SUSPEND; else if (of_property_read_bool(suspend_np, "regulator-off-in-suspend")) suspend_state->enabled = DISABLE_IN_SUSPEND; else suspend_state->enabled = DO_NOTHING_IN_SUSPEND; if (!of_property_read_u32(np, "regulator-suspend-min-microvolt", &pval)) suspend_state->min_uV = pval; if (!of_property_read_u32(np, "regulator-suspend-max-microvolt", &pval)) suspend_state->max_uV = pval; if (!of_property_read_u32(suspend_np, "regulator-suspend-microvolt", &pval)) suspend_state->uV = pval; else /* otherwise use min_uV as default suspend voltage */ suspend_state->uV = suspend_state->min_uV; if (of_property_read_bool(suspend_np, "regulator-changeable-in-suspend")) suspend_state->changeable = true; if (i == PM_SUSPEND_MEM) constraints->initial_state = PM_SUSPEND_MEM; of_node_put(suspend_np); suspend_state = NULL; suspend_np = NULL; } }
static int mdss_dsi_parse_dcs_cmds(struct device_node *np, struct dsi_panel_cmds *pcmds, char *cmd_key, char *link_key) { const char *data; int blen = 0, len; char *buf, *bp; struct dsi_ctrl_hdr *dchdr; int i, cnt; data = of_get_property(np, cmd_key, &blen); if (!data) { pr_err("%s: failed, key=%s\n", __func__, cmd_key); return -ENOMEM; } buf = kzalloc(sizeof(char) * blen, GFP_KERNEL); if (!buf) return -ENOMEM; memcpy(buf, data, blen); /* scan dcs commands */ bp = buf; len = blen; cnt = 0; while (len > sizeof(*dchdr)) { dchdr = (struct dsi_ctrl_hdr *)bp; dchdr->dlen = ntohs(dchdr->dlen); if (dchdr->dlen > len) { pr_err("%s: dtsi cmd=%x error, len=%d", __func__, dchdr->dtype, dchdr->dlen); return -ENOMEM; } bp += sizeof(*dchdr); len -= sizeof(*dchdr); bp += dchdr->dlen; len -= dchdr->dlen; cnt++; } if (len != 0) { pr_err("%s: dcs_cmd=%x len=%d error!", __func__, buf[0], blen); kfree(buf); return -ENOMEM; } pcmds->cmds = kzalloc(cnt * sizeof(struct dsi_cmd_desc), GFP_KERNEL); if (!pcmds->cmds) return -ENOMEM; pcmds->cmd_cnt = cnt; pcmds->buf = buf; pcmds->blen = blen; bp = buf; len = blen; for (i = 0; i < cnt; i++) { dchdr = (struct dsi_ctrl_hdr *)bp; len -= sizeof(*dchdr); bp += sizeof(*dchdr); pcmds->cmds[i].dchdr = *dchdr; pcmds->cmds[i].payload = bp; bp += dchdr->dlen; len -= dchdr->dlen; } pcmds->link_state = DSI_LP_MODE; /* default */ data = of_get_property(np, link_key, NULL); if (!strncmp(data, "DSI_HS_MODE", 11)) pcmds->link_state = DSI_HS_MODE; pr_debug("%s: dcs_cmd=%x len=%d, cmd_cnt=%d link_state=%d\n", __func__, pcmds->buf[0], pcmds->blen, pcmds->cmd_cnt, pcmds->link_state); return 0; }
static int imx_ldb_bind(struct device *dev, struct device *master, void *data) { struct drm_device *drm = data; struct device_node *np = dev->of_node; const struct of_device_id *of_id = of_match_device(imx_ldb_dt_ids, dev); struct device_node *child; const u8 *edidp; struct imx_ldb *imx_ldb; int datawidth; int mapping; int dual; int ret; int i; imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL); if (!imx_ldb) return -ENOMEM; imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr"); if (IS_ERR(imx_ldb->regmap)) { dev_err(dev, "failed to get parent regmap\n"); return PTR_ERR(imx_ldb->regmap); } imx_ldb->dev = dev; if (of_id) imx_ldb->lvds_mux = of_id->data; dual = of_property_read_bool(np, "fsl,dual-channel"); if (dual) imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN; /* * There are three different possible clock mux configurations: * i.MX53: ipu1_di0_sel, ipu1_di1_sel * i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel * i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel * Map them all to di0_sel...di3_sel. */ for (i = 0; i < 4; i++) { char clkname[16]; sprintf(clkname, "di%d_sel", i); imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname); if (IS_ERR(imx_ldb->clk_sel[i])) { ret = PTR_ERR(imx_ldb->clk_sel[i]); imx_ldb->clk_sel[i] = NULL; break; } } if (i == 0) return ret; for_each_child_of_node(np, child) { struct imx_ldb_channel *channel; struct device_node *panel_node; ret = of_property_read_u32(child, "reg", &i); if (ret || i < 0 || i > 1) return -EINVAL; if (dual && i > 0) { dev_warn(dev, "dual-channel mode, ignoring second output\n"); continue; } if (!of_device_is_available(child)) continue; channel = &imx_ldb->channel[i]; channel->ldb = imx_ldb; channel->chno = i; channel->child = child; edidp = of_get_property(child, "edid", &channel->edid_len); if (edidp) { channel->edid = kmemdup(edidp, channel->edid_len, GFP_KERNEL); } else { ret = of_get_drm_display_mode(child, &channel->mode, 0); if (!ret) channel->mode_valid = 1; } ret = of_property_read_u32(child, "fsl,data-width", &datawidth); if (ret) datawidth = 0; else if (datawidth != 18 && datawidth != 24) return -EINVAL; mapping = of_get_data_mapping(child); switch (mapping) { case LVDS_BIT_MAP_SPWG: if (datawidth == 24) { if (i == 0 || dual) imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24; if (i == 1 || dual) imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24; } break; case LVDS_BIT_MAP_JEIDA: if (datawidth == 18) { dev_err(dev, "JEIDA standard only supported in 24 bit\n"); return -EINVAL; } if (i == 0 || dual) imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 | LDB_BIT_MAP_CH0_JEIDA; if (i == 1 || dual) imx_ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 | LDB_BIT_MAP_CH1_JEIDA; break; default: dev_err(dev, "data mapping not specified or invalid\n"); return -EINVAL; } panel_node = of_parse_phandle(child, "fsl,panel", 0); if (panel_node) channel->panel = of_drm_find_panel(panel_node); ret = imx_ldb_register(drm, channel); if (ret) return ret; } dev_set_drvdata(dev, imx_ldb); return 0; }
static int32_t msm_led_trigger_probe(struct platform_device *pdev) { int32_t rc = 0, i = 0; struct device_node *of_node = pdev->dev.of_node; struct device_node *flash_src_node = NULL; CDBG("called\n"); if (!of_node) { pr_err("of_node NULL\n"); return -EINVAL; } fctrl.pdev = pdev; rc = of_property_read_u32(of_node, "cell-index", &pdev->id); if (rc < 0) { pr_err("failed\n"); return -EINVAL; } CDBG("pdev id %d\n", pdev->id); if (of_get_property(of_node, "qcom,flash-source", &fctrl.num_sources)) { fctrl.num_sources /= sizeof(uint32_t); CDBG("count %d\n", fctrl.num_sources); if (fctrl.num_sources > MAX_LED_TRIGGERS) { pr_err("failed\n"); return -EINVAL; } for (i = 0; i < fctrl.num_sources; i++) { flash_src_node = of_parse_phandle(of_node, "qcom,flash-source", i); if (!flash_src_node) { pr_err("flash_src_node NULL\n"); continue; } rc = of_property_read_string(flash_src_node, "linux,default-trigger", &fctrl.flash_trigger_name[i]); if (rc < 0) { pr_err("failed\n"); of_node_put(flash_src_node); continue; } CDBG("default trigger %s\n", fctrl.flash_trigger_name[i]); rc = of_property_read_u32(flash_src_node, "qcom,current", &fctrl.flash_op_current[i]); if (rc < 0) { pr_err("failed rc %d\n", rc); of_node_put(flash_src_node); continue; } of_node_put(flash_src_node); CDBG("max_current[%d] %d\n", i, fctrl.flash_op_current[i]); led_trigger_register_simple(fctrl.flash_trigger_name[i], &fctrl.flash_trigger[i]); } /* Torch source */ flash_src_node = of_parse_phandle(of_node, "qcom,torch-source", 0); if (flash_src_node) { rc = of_property_read_string(flash_src_node, "linux,default-trigger", &fctrl.torch_trigger_name); if (rc < 0) { pr_err("failed\n"); } else { CDBG("default trigger %s\n", fctrl.torch_trigger_name); rc = of_property_read_u32(flash_src_node, "qcom,current", &fctrl.torch_op_current); if (rc < 0) { pr_err("failed rc %d\n", rc); } else { CDBG("torch max_current %d\n", fctrl.torch_op_current); led_trigger_register_simple( fctrl.torch_trigger_name, &fctrl.torch_trigger); } } of_node_put(flash_src_node); } } rc = msm_led_flash_create_v4lsubdev(pdev, &fctrl); return rc; }
struct pci_dn * handle_eeh_events (struct eeh_event *event) { struct device_node *frozen_dn; struct pci_dn *frozen_pdn; struct pci_bus *frozen_bus; int rc = 0; enum pci_ers_result result = PCI_ERS_RESULT_NONE; const char *location, *pci_str, *drv_str; frozen_dn = find_device_pe(event->dn); if (!frozen_dn) { location = of_get_property(event->dn, "ibm,loc-code", NULL); location = location ? location : "unknown"; printk(KERN_ERR "EEH: Error: Cannot find partition endpoint " "for location=%s pci addr=%s\n", location, pci_name(event->dev)); return NULL; } frozen_bus = pcibios_find_pci_bus(frozen_dn); location = of_get_property(frozen_dn, "ibm,loc-code", NULL); location = location ? location : "unknown"; /* There are two different styles for coming up with the PE. * In the old style, it was the highest EEH-capable device * which was always an EADS pci bridge. In the new style, * there might not be any EADS bridges, and even when there are, * the firmware marks them as "EEH incapable". So another * two-step is needed to find the pci bus.. */ if (!frozen_bus) frozen_bus = pcibios_find_pci_bus (frozen_dn->parent); if (!frozen_bus) { printk(KERN_ERR "EEH: Cannot find PCI bus " "for location=%s dn=%s\n", location, frozen_dn->full_name); return NULL; } frozen_pdn = PCI_DN(frozen_dn); frozen_pdn->eeh_freeze_count++; if (frozen_pdn->pcidev) { pci_str = pci_name (frozen_pdn->pcidev); drv_str = pcid_name (frozen_pdn->pcidev); } else { pci_str = pci_name (event->dev); drv_str = pcid_name (event->dev); } if (frozen_pdn->eeh_freeze_count > EEH_MAX_ALLOWED_FREEZES) goto excess_failures; printk(KERN_WARNING "EEH: This PCI device has failed %d times in the last hour:\n", frozen_pdn->eeh_freeze_count); printk(KERN_WARNING "EEH: location=%s driver=%s pci addr=%s\n", location, drv_str, pci_str); /* Walk the various device drivers attached to this slot through * a reset sequence, giving each an opportunity to do what it needs * to accomplish the reset. Each child gets a report of the * status ... if any child can't handle the reset, then the entire * slot is dlpar removed and added. */ pci_walk_bus(frozen_bus, eeh_report_error, &result); /* Get the current PCI slot state. This can take a long time, * sometimes over 3 seconds for certain systems. */ rc = eeh_wait_for_slot_status (frozen_pdn, MAX_WAIT_FOR_RECOVERY*1000); if (rc < 0) { printk(KERN_WARNING "EEH: Permanent failure\n"); goto hard_fail; } /* Since rtas may enable MMIO when posting the error log, * don't post the error log until after all dev drivers * have been informed. */ eeh_slot_error_detail(frozen_pdn, EEH_LOG_TEMP_FAILURE); /* If all device drivers were EEH-unaware, then shut * down all of the device drivers, and hope they * go down willingly, without panicing the system. */ if (result == PCI_ERS_RESULT_NONE) { rc = eeh_reset_device(frozen_pdn, frozen_bus); if (rc) { printk(KERN_WARNING "EEH: Unable to reset, rc=%d\n", rc); goto hard_fail; } } /* If all devices reported they can proceed, then re-enable MMIO */ if (result == PCI_ERS_RESULT_CAN_RECOVER) { rc = rtas_pci_enable(frozen_pdn, EEH_THAW_MMIO); if (rc < 0) goto hard_fail; if (rc) { result = PCI_ERS_RESULT_NEED_RESET; } else { result = PCI_ERS_RESULT_NONE; pci_walk_bus(frozen_bus, eeh_report_mmio_enabled, &result); } } /* If all devices reported they can proceed, then re-enable DMA */ if (result == PCI_ERS_RESULT_CAN_RECOVER) { rc = rtas_pci_enable(frozen_pdn, EEH_THAW_DMA); if (rc < 0) goto hard_fail; if (rc) result = PCI_ERS_RESULT_NEED_RESET; else result = PCI_ERS_RESULT_RECOVERED; } /* If any device has a hard failure, then shut off everything. */ if (result == PCI_ERS_RESULT_DISCONNECT) { printk(KERN_WARNING "EEH: Device driver gave up\n"); goto hard_fail; } /* If any device called out for a reset, then reset the slot */ if (result == PCI_ERS_RESULT_NEED_RESET) { rc = eeh_reset_device(frozen_pdn, NULL); if (rc) { printk(KERN_WARNING "EEH: Cannot reset, rc=%d\n", rc); goto hard_fail; } result = PCI_ERS_RESULT_NONE; pci_walk_bus(frozen_bus, eeh_report_reset, &result); } /* All devices should claim they have recovered by now. */ if ((result != PCI_ERS_RESULT_RECOVERED) && (result != PCI_ERS_RESULT_NONE)) { printk(KERN_WARNING "EEH: Not recovered\n"); goto hard_fail; } /* Tell all device drivers that they can resume operations */ pci_walk_bus(frozen_bus, eeh_report_resume, NULL); return frozen_pdn; excess_failures: /* * About 90% of all real-life EEH failures in the field * are due to poorly seated PCI cards. Only 10% or so are * due to actual, failed cards. */ printk(KERN_ERR "EEH: PCI device at location=%s driver=%s pci addr=%s \n" "has failed %d times in the last hour " "and has been permanently disabled. \n" "Please try reseating this device or replacing it.\n", location, drv_str, pci_str, frozen_pdn->eeh_freeze_count); goto perm_error; hard_fail: printk(KERN_ERR "EEH: Unable to recover from failure of PCI device " "at location=%s driver=%s pci addr=%s \n" "Please try reseating this device or replacing it.\n", location, drv_str, pci_str); perm_error: eeh_slot_error_detail(frozen_pdn, EEH_LOG_PERM_FAILURE); /* Notify all devices that they're about to go down. */ pci_walk_bus(frozen_bus, eeh_report_failure, NULL); /* Shut down the device drivers for good. */ pcibios_remove_pci_devices(frozen_bus); return NULL; }
static int sprd_asoc_i2s_probe(struct platform_device *pdev) { struct snd_soc_card *card = &all_i2s_card; struct device_node *node = pdev->dev.of_node; card->dev = &pdev->dev; if (node) { int i; int dai_count; struct device_node *pcm_node; struct device_node *codec_node; if (snd_soc_of_parse_card_name(card, "sprd,model")) { pr_err("ERR:Card name is not provided\n"); return -ENODEV; } pcm_node = of_parse_phandle(node, "sprd,pcm", 0); if (!pcm_node) { pr_err("ERR:PCM node is not provided\n"); return -EINVAL; } codec_node = of_parse_phandle(node, "sprd,codec", 0); if (!codec_node) { pr_err("ERR:CODEC node is not provided\n"); of_node_put(pcm_node); return -EINVAL; } if (!of_get_property(node, "sprd,i2s", &dai_count)) return -ENOENT; dai_count /= sizeof(((struct property *) 0)->length); sp_asoc_pr_dbg("Register I2S from DTS count is %d\n", dai_count); card->dai_link = devm_kzalloc(&pdev->dev, dai_count * sizeof(struct snd_soc_dai_link), GFP_KERNEL); card->num_links = dai_count; for (i = 0; i < card->num_links; i++) { char uni_name[NAME_SIZE] = { 0 }; char uni_sname[NAME_SIZE] = { 0 }; struct device_node *dai_node; dai_node = of_parse_phandle(node, "sprd,i2s", i); if (dai_node) sp_asoc_pr_dbg("Register I2S dai node is %s\n", dai_node->full_name); else pr_err("ERR:I2S dai node is not provided\n"); card->dai_link[i] = all_i2s_dai[0]; snprintf(uni_name, NAME_SIZE, "%s.%d", all_i2s_dai[0].name, i); snprintf(uni_sname, NAME_SIZE, "%s.%d", all_i2s_dai[0].stream_name, i); card->dai_link[i].name = kstrdup(uni_name, GFP_KERNEL); card->dai_link[i].stream_name = kstrdup(uni_sname, GFP_KERNEL); card->dai_link[i].cpu_dai_name = NULL; card->dai_link[i].cpu_of_node = dai_node; card->dai_link[i].platform_name = NULL; card->dai_link[i].platform_of_node = pcm_node; card->dai_link[i].codec_name = NULL; card->dai_link[i].codec_of_node = codec_node; of_node_put(dai_node); } of_node_put(pcm_node); of_node_put(codec_node); } return snd_soc_register_card(card); }
/* * Enumerate the possible CPU set from the device tree and build the * cpu logical map array containing MPIDR values related to logical * cpus. Assumes that cpu_logical_map(0) has already been initialized. */ void __init of_smp_init_cpus(void) { struct device_node *dn = NULL; unsigned int i, cpu = 1; bool bootcpu_valid = false; while ((dn = of_find_node_by_type(dn, "cpu"))) { const u32 *cell; u64 hwid; /* * A cpu node with missing "reg" property is * considered invalid to build a cpu_logical_map * entry. */ cell = of_get_property(dn, "reg", NULL); if (!cell) { pr_err("%s: missing reg property\n", dn->full_name); goto next; } hwid = of_read_number(cell, of_n_addr_cells(dn)); /* * Non affinity bits must be set to 0 in the DT */ if (hwid & ~MPIDR_HWID_BITMASK) { pr_err("%s: invalid reg property\n", dn->full_name); goto next; } /* * Duplicate MPIDRs are a recipe for disaster. Scan * all initialized entries and check for * duplicates. If any is found just ignore the cpu. * cpu_logical_map was initialized to INVALID_HWID to * avoid matching valid MPIDR values. */ for (i = 1; (i < cpu) && (i < NR_CPUS); i++) { if (cpu_logical_map(i) == hwid) { pr_err("%s: duplicate cpu reg properties in the DT\n", dn->full_name); goto next; } } /* * The numbering scheme requires that the boot CPU * must be assigned logical id 0. Record it so that * the logical map built from DT is validated and can * be used. */ if (hwid == cpu_logical_map(0)) { if (bootcpu_valid) { pr_err("%s: duplicate boot cpu reg property in DT\n", dn->full_name); goto next; } bootcpu_valid = true; /* * cpu_logical_map has already been * initialized and the boot cpu doesn't need * the enable-method so continue without * incrementing cpu. */ continue; } if (cpu >= NR_CPUS) goto next; if (cpu_read_ops(dn, cpu) != 0) goto next; if (cpu_ops[cpu]->cpu_init(dn, cpu)) goto next; pr_debug("cpu logical map 0x%llx\n", hwid); cpu_logical_map(cpu) = hwid; next: cpu++; } /* sanity check */ if (cpu > NR_CPUS) pr_warning("no. of cores (%d) greater than configured maximum of %d - clipping\n", cpu, NR_CPUS); if (!bootcpu_valid) { pr_err("DT missing boot CPU MPIDR, not enabling secondaries\n"); return; } /* * All the cpus that made it to the cpu_logical_map have been * validated so set them as possible cpus. */ for (i = 0; i < NR_CPUS; i++) if (cpu_logical_map(i) != INVALID_HWID) set_cpu_possible(i, true); }
/* Function Description: Initialize i2c child device. * Return: None. */ static void envctrl_init_i2c_child(struct linux_ebus_child *edev_child, struct i2c_child_t *pchild) { int len, i, tbls_size = 0; struct device_node *dp = edev_child->prom_node; const void *pval; /* Get device address. */ pval = of_get_property(dp, "reg", &len); memcpy(&pchild->addr, pval, len); /* Get tables property. Read firmware temperature tables. */ pval = of_get_property(dp, "translation", &len); if (pval && len > 0) { memcpy(pchild->tblprop_array, pval, len); pchild->total_tbls = len / sizeof(struct pcf8584_tblprop); for (i = 0; i < pchild->total_tbls; i++) { if ((pchild->tblprop_array[i].size + pchild->tblprop_array[i].offset) > tbls_size) { tbls_size = pchild->tblprop_array[i].size + pchild->tblprop_array[i].offset; } } pchild->tables = kmalloc(tbls_size, GFP_KERNEL); if (pchild->tables == NULL){ printk("envctrl: Failed to allocate table.\n"); return; } pval = of_get_property(dp, "tables", &len); if (!pval || len <= 0) { printk("envctrl: Failed to get table.\n"); return; } memcpy(pchild->tables, pval, len); } /* SPARCengine ASM Reference Manual (ref. SMI doc 805-7581-04) * sections 2.5, 3.5, 4.5 state node 0x70 for CP1400/1500 is * "For Factory Use Only." * * We ignore the node on these platforms by assigning the * 'NULL' monitor type. */ if (ENVCTRL_CPCI_IGNORED_NODE == pchild->addr) { struct device_node *root_node; int len; root_node = of_find_node_by_path("/"); if (!strcmp(root_node->name, "SUNW,UltraSPARC-IIi-cEngine")) { for (len = 0; len < PCF8584_MAX_CHANNELS; ++len) { pchild->mon_type[len] = ENVCTRL_NOMON; } return; } } /* Get the monitor channels. */ pval = of_get_property(dp, "channels-in-use", &len); memcpy(pchild->chnl_array, pval, len); pchild->total_chnls = len / sizeof(struct pcf8584_channel); for (i = 0; i < pchild->total_chnls; i++) { switch (pchild->chnl_array[i].type) { case PCF8584_TEMP_TYPE: envctrl_init_adc(pchild, dp); break; case PCF8584_GLOBALADDR_TYPE: envctrl_init_globaladdr(pchild); i = pchild->total_chnls; break; case PCF8584_FANSTAT_TYPE: envctrl_init_fanstat(pchild); i = pchild->total_chnls; break; case PCF8584_VOLTAGE_TYPE: if (pchild->i2ctype == I2C_ADC) { envctrl_init_adc(pchild,dp); } else { envctrl_init_voltage_status(pchild); } i = pchild->total_chnls; break; default: break; }; } }
static int32_t msm_led_trigger_probe(struct platform_device *pdev) { int32_t rc = 0, i = 0; struct device_node *of_node = pdev->dev.of_node; struct device_node *flash_src_node = NULL; uint32_t count = 0; CDBG("called\n"); if (!of_node) { pr_err("of_node NULL\n"); return -EINVAL; } fctrl.pdev = pdev; rc = of_property_read_u32(of_node, "cell-index", &pdev->id); if (rc < 0) { pr_err("failed\n"); return -EINVAL; } CDBG("pdev id %d\n", pdev->id); rc = of_property_read_string(of_node, "flash-driver", &fctrl.flash_driver); pr_info("[%s] Flash driver is %s\n", __FUNCTION__, fctrl.flash_driver); if (rc < 0) { pr_err("%s failed %d\n", __FUNCTION__, __LINE__); return -EINVAL; } if (of_get_property(of_node, "qcom,flash-source", &count)) { count /= sizeof(uint32_t); CDBG("count %d\n", count); if (count > MAX_LED_TRIGGERS) { pr_err("failed\n"); return -EINVAL; } for (i = 0; i < count; i++) { flash_src_node = of_parse_phandle(of_node, "qcom,flash-source", i); if (!flash_src_node) { pr_err("flash_src_node NULL\n"); continue; } rc = of_property_read_string(flash_src_node, "linux,default-trigger", &fctrl.led_trigger_name[i]); if (rc < 0) { pr_err("failed\n"); of_node_put(flash_src_node); continue; } CDBG("default trigger %s\n", fctrl.led_trigger_name[i]); rc = of_property_read_u32(flash_src_node, "qcom,max-current", &fctrl.max_current[i]); if (rc < 0) { pr_err("failed rc %d\n", rc); of_node_put(flash_src_node); continue; } of_node_put(flash_src_node); CDBG("max_current[%d] %d\n", i, fctrl.max_current[i]); led_trigger_register_simple(fctrl.led_trigger_name[i], &fctrl.led_trigger[i]); } } rc = msm_led_flash_create_v4lsubdev(pdev, &fctrl); return rc; }
static int __devinit msm_spm_dev_probe(struct platform_device *pdev) { int ret = 0; int cpu = 0; int i = 0; struct device_node *node = pdev->dev.of_node; struct msm_spm_platform_data spm_data; char *key = NULL; uint32_t val = 0; struct msm_spm_seq_entry modes[MSM_SPM_MODE_NR]; size_t len = 0; struct msm_spm_device *dev = NULL; struct resource *res = NULL; uint32_t mode_count = 0; struct spm_of { char *key; uint32_t id; }; struct spm_of spm_of_data[] = { {"qcom,saw2-cfg", MSM_SPM_REG_SAW2_CFG}, {"qcom,saw2-avs-ctl", MSM_SPM_REG_SAW2_AVS_CTL}, {"qcom,saw2-avs-hysteresis", MSM_SPM_REG_SAW2_AVS_HYSTERESIS}, {"qcom,saw2-spm-ctl", MSM_SPM_REG_SAW2_SPM_CTL}, {"qcom,saw2-pmic-dly", MSM_SPM_REG_SAW2_PMIC_DLY}, {"qcom,saw2-avs-limit", MSM_SPM_REG_SAW2_AVS_LIMIT}, {"qcom,saw2-spm-dly", MSM_SPM_REG_SAW2_SPM_DLY}, {"qcom,saw2-pmic-data0", MSM_SPM_REG_SAW2_PMIC_DATA_0}, {"qcom,saw2-pmic-data1", MSM_SPM_REG_SAW2_PMIC_DATA_1}, {"qcom,saw2-pmic-data2", MSM_SPM_REG_SAW2_PMIC_DATA_2}, {"qcom,saw2-pmic-data3", MSM_SPM_REG_SAW2_PMIC_DATA_3}, {"qcom,saw2-pmic-data4", MSM_SPM_REG_SAW2_PMIC_DATA_4}, {"qcom,saw2-pmic-data5", MSM_SPM_REG_SAW2_PMIC_DATA_5}, {"qcom,saw2-pmic-data6", MSM_SPM_REG_SAW2_PMIC_DATA_6}, {"qcom,saw2-pmic-data7", MSM_SPM_REG_SAW2_PMIC_DATA_7}, }; struct mode_of { char *key; uint32_t id; uint32_t notify_rpm; }; struct mode_of of_cpu_modes[] = { {"qcom,saw2-spm-cmd-wfi", MSM_SPM_MODE_CLOCK_GATING, 0}, {"qcom,saw2-spm-cmd-ret", MSM_SPM_MODE_POWER_RETENTION, 0}, {"qcom,saw2-spm-cmd-spc", MSM_SPM_MODE_POWER_COLLAPSE, 0}, {"qcom,saw2-spm-cmd-pc", MSM_SPM_MODE_POWER_COLLAPSE, 1}, }; struct mode_of of_l2_modes[] = { {"qcom,saw2-spm-cmd-ret", MSM_SPM_L2_MODE_RETENTION, 1}, {"qcom,saw2-spm-cmd-gdhs", MSM_SPM_L2_MODE_GDHS, 1}, {"qcom,saw2-spm-cmd-pc", MSM_SPM_L2_MODE_POWER_COLLAPSE, 1}, }; struct mode_of *mode_of_data; int num_modes; memset(&spm_data, 0, sizeof(struct msm_spm_platform_data)); memset(&modes, 0, (MSM_SPM_MODE_NR - 2) * sizeof(struct msm_spm_seq_entry)); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) goto fail; spm_data.reg_base_addr = devm_ioremap(&pdev->dev, res->start, resource_size(res)); if (!spm_data.reg_base_addr) return -ENOMEM; key = "qcom,core-id"; ret = of_property_read_u32(node, key, &val); if (ret) goto fail; cpu = val; key = "qcom,saw2-ver-reg"; ret = of_property_read_u32(node, key, &val); if (ret) goto fail; spm_data.ver_reg = val; key = "qcom,vctl-timeout-us"; ret = of_property_read_u32(node, key, &val); if (!ret) spm_data.vctl_timeout_us = val; /* optional */ key = "qcom,vctl-port"; ret = of_property_read_u32(node, key, &val); if (!ret) spm_data.vctl_port = val; /* optional */ key = "qcom,phase-port"; ret = of_property_read_u32(node, key, &val); if (!ret) spm_data.phase_port = val; for (i = 0; i < ARRAY_SIZE(spm_of_data); i++) { ret = of_property_read_u32(node, spm_of_data[i].key, &val); if (ret) continue; spm_data.reg_init_values[spm_of_data[i].id] = val; } /* * Device with id 0..NR_CPUS are SPM for apps cores * Device with id 0xFFFF is for L2 SPM. */ if (cpu >= 0 && cpu < num_possible_cpus()) { mode_of_data = of_cpu_modes; num_modes = ARRAY_SIZE(of_cpu_modes); dev = &per_cpu(msm_cpu_spm_device, cpu); } else { mode_of_data = of_l2_modes; num_modes = ARRAY_SIZE(of_l2_modes); dev = &msm_spm_l2_device; } for (i = 0; i < num_modes; i++) { key = mode_of_data[i].key; modes[mode_count].cmd = (uint8_t *)of_get_property(node, key, &len); if (!modes[mode_count].cmd) continue; modes[mode_count].mode = mode_of_data[i].id; modes[mode_count].notify_rpm = mode_of_data[i].notify_rpm; mode_count++; } spm_data.modes = modes; spm_data.num_modes = mode_count; ret = msm_spm_dev_init(dev, &spm_data); if (ret < 0) pr_warn("%s():failed core-id:%u ret:%d\n", __func__, cpu, ret); return ret; fail: pr_err("%s: Failed reading node=%s, key=%s\n", __func__, node->full_name, key); return -EFAULT; }
/** * axienet_mdio_setup - MDIO setup function * @lp: Pointer to axienet local data structure. * @np: Pointer to device node * * returns: 0 on success, -ETIMEDOUT on a timeout, -ENOMEM when * mdiobus_alloc (to allocate memory for mii bus structure) fails. * * Sets up the MDIO interface by initializing the MDIO clock and enabling the * MDIO interface in hardware. Register the MDIO interface. **/ int axienet_mdio_setup(struct axienet_local *lp, struct device_node *np) { int ret; u32 clk_div, host_clock; u32 *property_p; struct mii_bus *bus; struct resource res; struct device_node *np1; /* clk_div can be calculated by deriving it from the equation: * fMDIO = fHOST / ((1 + clk_div) * 2) * * Where fMDIO <= 2500000, so we get: * fHOST / ((1 + clk_div) * 2) <= 2500000 * * Then we get: * 1 / ((1 + clk_div) * 2) <= (2500000 / fHOST) * * Then we get: * 1 / (1 + clk_div) <= ((2500000 * 2) / fHOST) * * Then we get: * 1 / (1 + clk_div) <= (5000000 / fHOST) * * So: * (1 + clk_div) >= (fHOST / 5000000) * * And finally: * clk_div >= (fHOST / 5000000) - 1 * * fHOST can be read from the flattened device tree as property * "clock-frequency" from the CPU */ np1 = of_find_node_by_name(NULL, "cpu"); if (!np1) { printk(KERN_WARNING "%s(): Could not find CPU device node.", __func__); printk(KERN_WARNING "Setting MDIO clock divisor to " "default %d\n", DEFAULT_CLOCK_DIVISOR); clk_div = DEFAULT_CLOCK_DIVISOR; goto issue; } property_p = (u32 *) of_get_property(np1, "clock-frequency", NULL); if (!property_p) { printk(KERN_WARNING "%s(): Could not find CPU property: " "clock-frequency.", __func__); printk(KERN_WARNING "Setting MDIO clock divisor to " "default %d\n", DEFAULT_CLOCK_DIVISOR); clk_div = DEFAULT_CLOCK_DIVISOR; goto issue; } host_clock = be32_to_cpup(property_p); clk_div = (host_clock / (MAX_MDIO_FREQ * 2)) - 1; /* If there is any remainder from the division of * fHOST / (MAX_MDIO_FREQ * 2), then we need to add * 1 to the clock divisor or we will surely be above 2.5 MHz */ if (host_clock % (MAX_MDIO_FREQ * 2)) clk_div++; printk(KERN_DEBUG "%s(): Setting MDIO clock divisor to %u based " "on %u Hz host clock.\n", __func__, clk_div, host_clock); of_node_put(np1); issue: axienet_iow(lp, XAE_MDIO_MC_OFFSET, (((u32) clk_div) | XAE_MDIO_MC_MDIOEN_MASK)); ret = axienet_mdio_wait_until_ready(lp); if (ret < 0) return ret; bus = mdiobus_alloc(); if (!bus) return -ENOMEM; np1 = of_get_parent(lp->phy_node); of_address_to_resource(np1, 0, &res); snprintf(bus->id, MII_BUS_ID_SIZE, "%.8llx", (unsigned long long) res.start); bus->priv = lp; bus->name = "Xilinx Axi Ethernet MDIO"; bus->read = axienet_mdio_read; bus->write = axienet_mdio_write; bus->parent = lp->dev; bus->irq = lp->mdio_irqs; /* preallocated IRQ table */ lp->mii_bus = bus; ret = of_mdiobus_register(bus, np1); if (ret) { mdiobus_free(bus); return ret; } return 0; }