static int vexpress_osc_probe(struct platform_device *pdev) { struct clk_init_data init; struct vexpress_osc *osc; struct clk *clk; u32 range[2]; osc = devm_kzalloc(&pdev->dev, sizeof(*osc), GFP_KERNEL); if (!osc) return -ENOMEM; osc->reg = devm_regmap_init_vexpress_config(&pdev->dev); if (IS_ERR(osc->reg)) return PTR_ERR(osc->reg); if (of_property_read_u32_array(pdev->dev.of_node, "freq-range", range, ARRAY_SIZE(range)) == 0) { osc->rate_min = range[0]; osc->rate_max = range[1]; } if (of_property_read_string(pdev->dev.of_node, "clock-output-names", &init.name) != 0) init.name = dev_name(&pdev->dev); init.ops = &vexpress_osc_ops; init.flags = 0; init.num_parents = 0; osc->hw.init = &init; clk = clk_register(NULL, &osc->hw); if (IS_ERR(clk)) return PTR_ERR(clk); of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get, clk); dev_dbg(&pdev->dev, "Registered clock '%s'\n", init.name); return 0; }
static int hisi_pmic_uv_mntn_initial(struct platform_device *pdev, PMIC_MNTN_DESC *pmic_mntn) { int ret; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; struct irq_desc *desc = NULL ; pmic_mntn->uv_irq = platform_get_irq_byname(pdev, "uv"); if (pmic_mntn->uv_irq < 0) { dev_err(dev, "[%s] platform_get_irq_byname uv failed.\n", __func__); return -ENODEV; } ret = devm_request_irq(dev, pmic_mntn->uv_irq, hisi_pmic_uv_irq_handler, IRQF_DISABLED|IRQF_NO_SUSPEND, "pmu-uv-irq", (void *)pmic_mntn); if (ret) { dev_err(dev, "[%s]devm_request_irq uv_irq failed.\n", __func__); return -ENODEV; } /* mask or unmask is up to battery capacity,do not know the battery capacity here */ desc = irq_to_desc(pmic_mntn->uv_irq); if (!desc) { dev_err(dev, "[%s]irq_to_desc failed\n", __func__); return -1; } if (NULL != desc->irq_data.chip->irq_mask) desc->irq_data.chip->irq_mask(&desc->irq_data); ret = of_property_read_u32_array(np, "hisilicon,battery-capacity-check", (u32 *)&(pmic_mntn->bat_cap_info), 2); if (ret) { dev_err(dev, "of_property_read_u32_array read fail\n"); return -ENODEV; } INIT_DELAYED_WORK(&pmic_mntn->uv_mntn_delayed_work, uv_mntn_work); schedule_delayed_work(&pmic_mntn->uv_mntn_delayed_work, round_jiffies_relative(msecs_to_jiffies(pmic_mntn->bat_cap_info.check_interval))); return 0; }
static int qpnp_regulator_match(struct qpnp_regulator *vreg) { const struct qpnp_regulator_mapping *mapping; struct device_node *node = vreg->spmi_dev->dev.of_node; int rc, i; u8 raw_type[2], type, subtype; u32 type_reg[2]; rc = of_property_read_u32_array(node, "qcom,force-type", type_reg, 2); if (!rc) { type = type_reg[0]; subtype = type_reg[1]; } else { rc = qpnp_vreg_read(vreg, QPNP_COMMON_REG_TYPE, raw_type, 2); if (rc) { vreg_err(vreg, "could not read type register, rc=%d\n", rc); return rc; } type = raw_type[0]; subtype = raw_type[1]; } rc = -ENODEV; for (i = 0; i < ARRAY_SIZE(supported_regulators); i++) { mapping = &supported_regulators[i]; if (mapping->type == type && mapping->subtype == subtype) { vreg->logical_type = mapping->logical_type; vreg->set_points = mapping->set_points; vreg->hpm_min_load = mapping->hpm_min_load; vreg->rdesc.ops = mapping->ops; vreg->rdesc.n_voltages = mapping->set_points->n_voltages; rc = 0; break; } } return rc; }
static int __devinit restart_parameters_probe(struct platform_device *pdev) { int of_ret = 0; u32 of_val[2]; if (!(pdev->dev.of_node)) { pr_err("%s: device tree not enabled\n", __func__); return -EFAULT; } of_ret = of_property_read_u32_array(pdev->dev.of_node, "qcom,memory-fixed", of_val, 2); if (of_ret) { pr_err("%s: device tree configuration error\n", __func__); return -EFAULT; } restart_parameters_base = ioremap(of_val[0], of_val[1]); restart_parameters_max = of_val[1]; return 0; }
static int msm_vidc_load_freq_table(struct msm_vidc_platform_resources *res) { int rc = 0; int num_elements = 0; struct platform_device *pdev = res->pdev; if (!of_find_property(pdev->dev.of_node, "qcom,load-freq-tbl", NULL)) { /* qcom,load-freq-tbl is an optional property. It likely won't * be present on cores that we can't clock scale on. */ dprintk(VIDC_DBG, "qcom,load-freq-tbl not found\n"); return 0; } num_elements = get_u32_array_num_elements(pdev, "qcom,load-freq-tbl"); num_elements /= sizeof(*res->load_freq_tbl) / sizeof(u32); if (num_elements == 0) { dprintk(VIDC_ERR, "no elements in frequency table\n"); return rc; } res->load_freq_tbl = devm_kzalloc(&pdev->dev, num_elements * sizeof(*res->load_freq_tbl), GFP_KERNEL); if (!res->load_freq_tbl) { dprintk(VIDC_ERR, "%s Failed to alloc load_freq_tbl\n", __func__); return -ENOMEM; } if (of_property_read_u32_array(pdev->dev.of_node, "qcom,load-freq-tbl", (u32 *)res->load_freq_tbl, num_elements * sizeof(*res->load_freq_tbl) / sizeof(u32))) { dprintk(VIDC_ERR, "Failed to read frequency table\n"); msm_vidc_free_freq_table(res); return -EINVAL; } res->load_freq_tbl_size = num_elements; return rc; }
int altel6045_get_dt_data(const hwextisp_intf_t *i, struct device_node *of_node) { int ret = 0; int index = 0; altek6045_private_data_t* pdata = NULL; altek6045_t* mini_isp = NULL; mini_isp = I2A(i); pdata = (altek6045_private_data_t *)mini_isp->pdata; ret = of_property_read_u32_array(of_node, "hisi,isp-pin", pdata->pin, ISP_MAX); if (ret < 0) { cam_err("%s failed line %d\n", __func__, __LINE__); return ret; } else { for (index = 0; index < ISP_MAX; index++) { cam_debug("%s pin[%d]=%d.\n", __func__, index, pdata->pin[index]); } } #if 0 ret = gpio_request(pdata->pin[ISP_DVDD], "isp-dcdc"); if (ret < 0) { cam_err("%s failed to request isp-dvdd pin.", __func__); return ret; } #endif ret = of_property_read_u32(of_node, "hisi,chip-type", &extisp_type); cam_info("%s hisi,chip-type %d, ret %d\n", __func__, extisp_type, ret); if (ret < 0) { cam_err("%s failed %d\n", __func__, __LINE__); } return ret; }
static int dsi_panel_parse_backlight(struct platform_device *pdev, struct dsi_panel_common_pdata *panel_data, char *bl_ctrl) { int rc; u32 res[6]; static const char *bl_ctrl_type; bl_ctrl_type = of_get_property(pdev->dev.of_node, "qcom,mdss-pan-bl-ctrl", NULL); if ((bl_ctrl_type) && (!strncmp(bl_ctrl_type, "bl_ctrl_wled", 12))) { led_trigger_register_simple("bkl-trigger", &bl_led_trigger); pr_debug("%s: SUCCESS-> WLED TRIGGER register\n", __func__); *bl_ctrl = BL_WLED; } rc = of_property_read_u32_array(pdev->dev.of_node, "qcom,mdss-pan-bl-levels", res, 2); panel_data->panel_info.bl_min = (!rc ? res[0] : 0); panel_data->panel_info.bl_max = (!rc ? res[1] : 255); return rc; }
int hdmi_parse_lanes_of(struct platform_device *pdev, struct device_node *ep, struct hdmi_phy_data *phy) { struct property *prop; int r, len; prop = of_find_property(ep, "lanes", &len); if (prop) { u32 lanes[8]; if (len / sizeof(u32) != ARRAY_SIZE(lanes)) { dev_err(&pdev->dev, "bad number of lanes\n"); return -EINVAL; } r = of_property_read_u32_array(ep, "lanes", lanes, ARRAY_SIZE(lanes)); if (r) { dev_err(&pdev->dev, "failed to read lane data\n"); return r; } r = hdmi_phy_parse_lanes(phy, lanes); if (r) { dev_err(&pdev->dev, "failed to parse lane data\n"); return r; } } else { static const u32 default_lanes[] = { 0, 1, 2, 3, 4, 5, 6, 7 }; r = hdmi_phy_parse_lanes(phy, default_lanes); if (WARN_ON(r)) { dev_err(&pdev->dev, "failed to parse lane data\n"); return r; } } return 0; }
static int arizona_of_get_core_pdata(struct arizona *arizona) { int ret, i; arizona->pdata.reset = of_get_named_gpio(arizona->dev->of_node, "reset", 0); if (arizona->pdata.reset < 0) arizona->pdata.reset = 0; arizona->pdata.ldoena = of_get_named_gpio(arizona->dev->of_node, "ldoena", 0); if (arizona->pdata.ldoena < 0) arizona->pdata.ldoena = 0; ret = of_property_read_u32_array(arizona->dev->of_node, "gpio-defaults", arizona->pdata.gpio_defaults, ARRAY_SIZE(arizona->pdata.gpio_defaults)); if (ret >= 0) { /* * All values are literal except out of range values * which are chip default, translate into platform * data which uses 0 as chip default and out of range * as zero. */ for (i = 0; i < ARRAY_SIZE(arizona->pdata.gpio_defaults); i++) { if (arizona->pdata.gpio_defaults[i] > 0xffff) arizona->pdata.gpio_defaults[i] = 0; if (arizona->pdata.gpio_defaults[i] == 0) arizona->pdata.gpio_defaults[i] = 0x10000; } } else { dev_err(arizona->dev, "Failed to parse GPIO defaults: %d\n", ret); } of_property_read_u32(arizona->dev->of_node, "irq-base", &arizona->pdata.irq_base); of_property_read_u32(arizona->dev->of_node, "gpio-base", &arizona->pdata.gpio_base); return 0; }
int mali_pdev_dts_init(struct platform_device* mali_gpu_device) { struct device_node *cfg_node = mali_gpu_device->dev.of_node; struct device_node *child; u32 prop_value; int err; mali_dvfs_threshold_table_t* tbl = NULL; u32 tbl_size; u32 tbl_size_in_byte; for_each_child_of_node(cfg_node, child) { err = of_property_read_u32(child, "shared_memory", &prop_value); if (err == 0) { MALI_DEBUG_PRINT(2, ("shared_memory configurate %d\n", prop_value)); mali_gpu_data.shared_mem_size = prop_value * 1024 * 1024; } err = of_property_read_u32(child, "dvfs_size", &prop_value); if (err != 0 || prop_value < 0 || prop_value > get_max_dvfs_tbl_size()) { MALI_DEBUG_PRINT(2, ("invalid recorde_number is.\n")); goto def_start; } tbl_size = sizeof(mali_dvfs_threshold_table_t) * prop_value; tbl_size_in_byte = tbl_size / sizeof(u32); tbl = kzalloc(tbl_size, GFP_KERNEL); if (!tbl) goto def_start; err = of_property_read_u32_array(child, "dvfs_table", (u32*)tbl, tbl_size_in_byte); if (err == 0) { memcpy(get_mali_dvfs_tbl_addr(), tbl, tbl_size); set_mali_dvfs_tbl_size(prop_value); kfree(tbl); } }
static struct tps65910_board *tps65910_parse_dt_for_gpio(struct device *dev, struct tps65910 *tps65910, int chip_ngpio) { struct tps65910_board *tps65910_board = tps65910->of_plat_data; unsigned int prop_array[TPS6591X_MAX_NUM_GPIO]; int ngpio = min(chip_ngpio, TPS6591X_MAX_NUM_GPIO); int ret; int idx; tps65910_board->gpio_base = -1; ret = of_property_read_u32_array(tps65910->dev->of_node, "ti,en-gpio-sleep", prop_array, ngpio); if (ret < 0) { dev_dbg(dev, "ti,en-gpio-sleep not specified\n"); return tps65910_board; } for (idx = 0; idx < ngpio; idx++) tps65910_board->en_gpio_sleep[idx] = (prop_array[idx] != 0); return tps65910_board; }
/* * Probe device tree for supported idle states */ static void __init pnv_probe_idle_states(void) { struct device_node *np; int dt_idle_states; u32 *flags = NULL; int i; np = of_find_node_by_path("/ibm,opal/power-mgt"); if (!np) { pr_warn("opal: PowerMgmt Node not found\n"); goto out; } dt_idle_states = of_property_count_u32_elems(np, "ibm,cpu-idle-state-flags"); if (dt_idle_states < 0) { pr_warn("cpuidle-powernv: no idle states found in the DT\n"); goto out; } flags = kcalloc(dt_idle_states, sizeof(*flags), GFP_KERNEL); if (of_property_read_u32_array(np, "ibm,cpu-idle-state-flags", flags, dt_idle_states)) { pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-flags in DT\n"); goto out; } if (cpu_has_feature(CPU_FTR_ARCH_300)) { if (pnv_power9_idle_init(np, flags, dt_idle_states)) goto out; } for (i = 0; i < dt_idle_states; i++) supported_cpuidle_states |= flags[i]; out: kfree(flags); }
static void highbank_set_em_messages(struct device *dev, struct ahci_host_priv *hpriv, struct ata_port_info *pi) { struct device_node *np = dev->of_node; struct ecx_plat_data *pdata = hpriv->plat_data; int i; int err; for (i = 0; i < SGPIO_PINS; i++) { err = of_get_named_gpio(np, "calxeda,sgpio-gpio", i); if (err < 0) return; pdata->sgpio_gpio[i] = err; err = gpio_request(pdata->sgpio_gpio[i], "CX SGPIO"); if (err) { pr_err("sata_highbank gpio_request %d failed: %d\n", i, err); return; } gpio_direction_output(pdata->sgpio_gpio[i], 1); } of_property_read_u32_array(np, "calxeda,led-order", pdata->port_to_sgpio, pdata->n_ports); if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks)) pdata->pre_clocks = 0; if (of_property_read_u32(np, "calxeda,post-clocks", &pdata->post_clocks)) pdata->post_clocks = 0; /* store em_loc */ hpriv->em_loc = 0; hpriv->em_buf_sz = 4; hpriv->em_msg_type = EM_MSG_TYPE_LED; pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY; }
static int regulator_init(struct device_node *fdt_node, const char *regul_name, const char *scope_name, struct dts_regulator *dts_regul) { unsigned int scope[2]; const char *regul = NULL; DBG_INFO(""); if (of_property_read_string(fdt_node, regul_name, ®ul)) { DBG_ERR("don't config %s", regul_name); goto fail; } DBG_INFO("%s", regul ? regul : "NULL"); if (of_property_read_u32_array(fdt_node, scope_name, scope, 2)) { DBG_ERR("fail to get %s", scope_name); goto fail; } DBG_INFO("min-%d, max-%d", scope[0], scope[1]); dts_regul->min = scope[0]; dts_regul->max = scope[1]; dts_regul->regul = regulator_get(NULL, regul); if (IS_ERR(dts_regul->regul)) { dts_regul->regul = NULL; DBG_ERR("get regulator failed"); goto fail; } regulator_set_voltage(dts_regul->regul, dts_regul->min, dts_regul->max); //regulator_enable(dts_regul->regul); //mdelay(5); return 0; fail: return -1; }
static int cypress_get_keycodes(struct device *dev, char *name, struct cypress_touchkey_platform_data *pdata) { struct property *prop; struct device_node *np = dev->of_node; int rc; prop = of_find_property(np, name, NULL); if (!prop) return -EINVAL; if (!prop->value) return -ENODATA; pdata->keycodes_size = prop->length / sizeof(u32); rc = of_property_read_u32_array(np, name, pdata->touchkey_keycode, pdata->keycodes_size); if (rc && (rc != -EINVAL)) { dev_info(dev, "%s: Unable to read %s\n", __func__, name); return rc; } return 0; }
static void j2_start_cpu(unsigned int cpu, unsigned long entry_point) { struct device_node *np; u32 regs[2]; void __iomem *release, *initpc; if (!cpu) return; np = of_get_cpu_node(cpu, NULL); if (!np) return; if (of_property_read_u32_array(np, "cpu-release-addr", regs, 2)) return; release = ioremap_nocache(regs[0], sizeof(u32)); initpc = ioremap_nocache(regs[1], sizeof(u32)); __raw_writel(entry_point, initpc); __raw_writel(1, release); iounmap(initpc); iounmap(release); pr_info("J2 SMP: requested start of cpu %u\n", cpu); }
void kpd_get_dts_info(struct device_node *node) { of_property_read_u32(node, "mediatek,kpd-key-debounce", &kpd_dts_data.kpd_key_debounce); of_property_read_u32(node, "mediatek,kpd-sw-pwrkey", &kpd_dts_data.kpd_sw_pwrkey); of_property_read_u32(node, "mediatek,kpd-hw-pwrkey", &kpd_dts_data.kpd_hw_pwrkey); of_property_read_u32(node, "mediatek,kpd-sw-rstkey", &kpd_dts_data.kpd_sw_rstkey); of_property_read_u32(node, "mediatek,kpd-hw-rstkey", &kpd_dts_data.kpd_hw_rstkey); of_property_read_u32(node, "mediatek,kpd-use-extend-type", &kpd_dts_data.kpd_use_extend_type); of_property_read_u32(node, "mediatek,kpd-pwrkey-eint-gpio", &kpd_dts_data.kpd_pwrkey_eint_gpio); of_property_read_u32(node, "mediatek,kpd-pwrkey-gpio-din", &kpd_dts_data.kpd_pwrkey_gpio_din); of_property_read_u32(node, "mediatek,kpd-hw-dl-key1", &kpd_dts_data.kpd_hw_dl_key1); of_property_read_u32(node, "mediatek,kpd-hw-dl-key2", &kpd_dts_data.kpd_hw_dl_key2); of_property_read_u32(node, "mediatek,kpd-hw-dl-key3", &kpd_dts_data.kpd_hw_dl_key3); of_property_read_u32(node, "mediatek,kpd-hw-recovery-key", &kpd_dts_data.kpd_hw_recovery_key); of_property_read_u32(node, "mediatek,kpd-hw-factory-key", &kpd_dts_data.kpd_hw_factory_key); of_property_read_u32(node, "mediatek,kpd-hw-map-num", &kpd_dts_data.kpd_hw_map_num); of_property_read_u32_array(node, "mediatek,kpd-hw-init-map", kpd_dts_data.kpd_hw_init_map, kpd_dts_data.kpd_hw_map_num); kpd_print("key-debounce = %d, sw-pwrkey = %d, hw-pwrkey = %d, hw-rstkey = %d, sw-rstkey = %d\n", kpd_dts_data.kpd_key_debounce, kpd_dts_data.kpd_sw_pwrkey, kpd_dts_data.kpd_hw_pwrkey, kpd_dts_data.kpd_hw_rstkey, kpd_dts_data.kpd_sw_rstkey); }
static int tangox_sata_phy_probe(struct platform_device *pdev) { struct device_node *node = pdev->dev.of_node; struct tangox_sata_phy *phy; struct resource *res; struct phy *genphy; struct phy_provider *phy_prov; phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL); if (!phy) return -ENOMEM; res = platform_get_resource(pdev, IORESOURCE_MEM, 0); if (!res) return -EINVAL; phy->base = devm_ioremap_resource(&pdev->dev, res); if (IS_ERR(phy->base)) return PTR_ERR(phy->base); phy->clk_sel = of_property_read_bool(node, "sigma,internal-clock"); of_property_read_u32(node, "clock-frequency", &phy->clk_ref); of_property_read_u32(node, "sigma,tx-erc", &phy->tx_erc); of_property_read_u32(node, "sigma,tx-ssc", &phy->tx_ssc); of_property_read_u32_array(node, "sigma,rx-ssc", phy->rx_ssc, 2); genphy = devm_phy_create(&pdev->dev, NULL, &tangox_sata_phy_ops); if (IS_ERR(genphy)) return PTR_ERR(genphy); phy_set_drvdata(genphy, phy); phy_prov = devm_of_phy_provider_register(&pdev->dev, of_phy_simple_xlate); return PTR_ERR_OR_ZERO(phy_prov); }
int get_hw_config_u32_array(const char *node_name, const char *prop_name, u32 *pvalue, size_t sz) { struct device_node *np; int ret; if(node_name == NULL || prop_name == NULL || pvalue == NULL) { hwlog_err("Invalid Argument, NULL passed\n"); return -EINVAL; } np = of_find_node_by_name(NULL, node_name); if (!np) { hwlog_err("can not get device node with node_name: %s\n", node_name); return -ENODEV; } if(0 == is_property_public(np, prop_name)) { hwlog_err("property to read is not public, permission denied\n"); ret = -EACCES; goto OUT; } ret = of_property_read_u32_array(np, prop_name, pvalue, sz); if (ret != 0) { hwlog_err("can not get prop values with prop_name: %s\n", prop_name); goto OUT; } OUT: of_node_put(np); return ret; }
static int gadc_thermal_read_linear_lookup_table(struct device *dev, struct gadc_thermal_info *gti) { struct device_node *np = dev->of_node; int ntable; int ret; ntable = of_property_count_elems_of_size(np, "temperature-lookup-table", sizeof(u32)); if (ntable <= 0) { dev_notice(dev, "no lookup table, assuming DAC channel returns milliCelcius\n"); return 0; } if (ntable % 2) { dev_err(dev, "Pair of temperature vs ADC read value missing\n"); return -EINVAL; } gti->lookup_table = devm_kcalloc(dev, ntable, sizeof(*gti->lookup_table), GFP_KERNEL); if (!gti->lookup_table) return -ENOMEM; ret = of_property_read_u32_array(np, "temperature-lookup-table", (u32 *)gti->lookup_table, ntable); if (ret < 0) { dev_err(dev, "Failed to read temperature lookup table: %d\n", ret); return ret; } gti->nlookup_table = ntable / 2; return 0; }
void get_cable_data_from_dt(void *of_node) { int i; u32 cable_value[3]; struct device_node *node_temp = (struct device_node *)of_node; const char *propname[MAX_CABLE_NUM] = { "lge,no-init-cable", "lge,cable-mhl-1k", "lge,cable-u-28p7k", "lge,cable-28p7k", "lge,cable-56k", "lge,cable-100k", "lge,cable-130k", "lge,cable-180k", "lge,cable-200k", "lge,cable-220k", "lge,cable-270k", "lge,cable-330k", "lge,cable-620k", "lge,cable-910k", "lge,cable-none" }; if (cable_type_defined) { pr_info("Cable type is already defined\n"); return; } for (i = 0; i < MAX_CABLE_NUM; i++) { of_property_read_u32_array(node_temp, propname[i], cable_value, 3); lge_acc_cable_type_data[i].threshhold = cable_value[0]; lge_acc_cable_type_data[i].type = i; lge_acc_cable_type_data[i].ta_ma = cable_value[1]; lge_acc_cable_type_data[i].usb_ma = cable_value[2]; } cable_type_defined = 1; }
static int __devinit productinfo_probe(struct platform_device *pdev) { int of_ret = 0; u32 of_val[2]; if (!(pdev->dev.of_node)) { pr_err("%s: device tree not enabled\n", __func__); return -EFAULT; } if (productinfo_fops.owner) { pr_err("%s: already claimed\n", __func__); return -EFAULT; } of_ret = of_property_read_u32_array(pdev->dev.of_node, "qcom,memory-fixed", of_val, 2); if (of_ret) { pr_err("%s: device tree configuration error\n", __func__); return -EFAULT; } productinfo_base = ioremap(of_val[0], of_val[1]); productinfo_max = of_val[1] - 1; productinfo_entry = create_proc_entry("productinfo", S_IFREG | S_IRUGO | S_IWUSR | S_IWGRP, NULL); if (!productinfo_entry) { pr_err("%s: could not create proc entry for productinfo\n", __func__); return -EFAULT; } productinfo_fops.owner = THIS_MODULE; productinfo_entry->proc_fops = &productinfo_fops; // productinfo_entry->size = strlen(productinfo_base); return 0; }
static void __init zynq_pll_clk_setup(struct device_node *np) { struct clk_init_data init; struct zynq_pll_clk *pll; const char *parent_name; struct clk *clk; u32 regs[2]; int ret; ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs)); if (WARN_ON(ret)) return; pll = kzalloc(sizeof(*pll), GFP_KERNEL); if (WARN_ON(!pll)) return; pll->pll_ctrl = slcr_base + regs[0]; pll->pll_cfg = slcr_base + regs[1]; of_property_read_string(np, "clock-output-names", &init.name); init.ops = &zynq_pll_clk_ops; parent_name = of_clk_get_parent_name(np, 0); init.parent_names = &parent_name; init.num_parents = 1; pll->hw.init = &init; clk = clk_register(NULL, &pll->hw); if (WARN_ON(IS_ERR(clk))) return; ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); if (WARN_ON(ret)) return; }
static void hkadc_fill_channel_map(void) { unsigned int l2p_table[HKADC_TEMP_BUTT]; struct device_node *root = NULL; struct hkadc_table_data *p_hkadc_table = acpu_hkadc_property; unsigned int phy_chan; int index = 0; int ret = 0; root = of_find_compatible_node(NULL, NULL, "hisilicon,hi6xxx-hkadc-driver"); if (!root) { printk(KERN_ERR "get hisilicon,hi6xxx-hkadc node err.\n"); return; } ret = of_property_read_u32_array(root, "hkadc-l2p-table", l2p_table, sizeof(l2p_table)/sizeof(unsigned int)); if(ret) { printk(KERN_ERR "get hi6xxx-hisilicon-hkadc_l2p_table err.\n"); return; } for(index = 0; index < sizeof(acpu_hkadc_property)/sizeof(struct hkadc_table_data); index++) { phy_chan = l2p_table[p_hkadc_table->logic_chan]; /*获取到有效的通道值,才赋给全局变量,不然使用默认的*/ if(HKADC_INVALID_CHAN_NUM != phy_chan) { p_hkadc_table->phy_chan = phy_chan; } p_hkadc_table++; } return; }
static int pwm_regulator_init_table(struct platform_device *pdev, struct pwm_regulator_data *drvdata) { struct device_node *np = pdev->dev.of_node; struct pwm_voltages *duty_cycle_table; unsigned int length = 0; int ret; of_find_property(np, "voltage-table", &length); if ((length < sizeof(*duty_cycle_table)) || (length % sizeof(*duty_cycle_table))) { dev_err(&pdev->dev, "voltage-table length(%d) is invalid\n", length); return -EINVAL; } duty_cycle_table = devm_kzalloc(&pdev->dev, length, GFP_KERNEL); if (!duty_cycle_table) return -ENOMEM; ret = of_property_read_u32_array(np, "voltage-table", (u32 *)duty_cycle_table, length / sizeof(u32)); if (ret) { dev_err(&pdev->dev, "Failed to read voltage-table\n"); return ret; } drvdata->duty_cycle_table = duty_cycle_table; pwm_regulator_desc.ops = &pwm_regulator_voltage_table_ops; pwm_regulator_desc.n_voltages = length / sizeof(*duty_cycle_table); return 0; }
/* * pnv_arch300_idle_init: Initializes the default idle state, first * deep idle state and deepest idle state on * ISA 3.0 CPUs. * * @np: /ibm,opal/power-mgt device node * @flags: cpu-idle-state-flags array * @dt_idle_states: Number of idle state entries * Returns 0 on success */ static int __init pnv_power9_idle_init(struct device_node *np, u32 *flags, int dt_idle_states) { u64 *psscr_val = NULL; u64 *psscr_mask = NULL; u32 *residency_ns = NULL; u64 max_residency_ns = 0; int rc = 0, i; psscr_val = kcalloc(dt_idle_states, sizeof(*psscr_val), GFP_KERNEL); psscr_mask = kcalloc(dt_idle_states, sizeof(*psscr_mask), GFP_KERNEL); residency_ns = kcalloc(dt_idle_states, sizeof(*residency_ns), GFP_KERNEL); if (!psscr_val || !psscr_mask || !residency_ns) { rc = -1; goto out; } if (of_property_read_u64_array(np, "ibm,cpu-idle-state-psscr", psscr_val, dt_idle_states)) { pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr in DT\n"); rc = -1; goto out; } if (of_property_read_u64_array(np, "ibm,cpu-idle-state-psscr-mask", psscr_mask, dt_idle_states)) { pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-psscr-mask in DT\n"); rc = -1; goto out; } if (of_property_read_u32_array(np, "ibm,cpu-idle-state-residency-ns", residency_ns, dt_idle_states)) { pr_warn("cpuidle-powernv: missing ibm,cpu-idle-state-residency-ns in DT\n"); rc = -1; goto out; } /* * Set pnv_first_deep_stop_state, pnv_deepest_stop_psscr_{val,mask}, * and the pnv_default_stop_{val,mask}. * * pnv_first_deep_stop_state should be set to the first stop * level to cause hypervisor state loss. * * pnv_deepest_stop_{val,mask} should be set to values corresponding to * the deepest stop state. * * pnv_default_stop_{val,mask} should be set to values corresponding to * the shallowest (OPAL_PM_STOP_INST_FAST) loss-less stop state. */ pnv_first_deep_stop_state = MAX_STOP_STATE; for (i = 0; i < dt_idle_states; i++) { int err; u64 psscr_rl = psscr_val[i] & PSSCR_RL_MASK; if ((flags[i] & OPAL_PM_LOSE_FULL_CONTEXT) && (pnv_first_deep_stop_state > psscr_rl)) pnv_first_deep_stop_state = psscr_rl; err = validate_psscr_val_mask(&psscr_val[i], &psscr_mask[i], flags[i]); if (err) { report_invalid_psscr_val(psscr_val[i], err); continue; } if (max_residency_ns < residency_ns[i]) { max_residency_ns = residency_ns[i]; pnv_deepest_stop_psscr_val = psscr_val[i]; pnv_deepest_stop_psscr_mask = psscr_mask[i]; pnv_deepest_stop_flag = flags[i]; deepest_stop_found = true; } if (!default_stop_found && (flags[i] & OPAL_PM_STOP_INST_FAST)) { pnv_default_stop_val = psscr_val[i]; pnv_default_stop_mask = psscr_mask[i]; default_stop_found = true; } } if (unlikely(!default_stop_found)) { pr_warn("cpuidle-powernv: No suitable default stop state found. Disabling platform idle.\n"); } else { ppc_md.power_save = power9_idle; pr_info("cpuidle-powernv: Default stop: psscr = 0x%016llx,mask=0x%016llx\n", pnv_default_stop_val, pnv_default_stop_mask); } if (unlikely(!deepest_stop_found)) { pr_warn("cpuidle-powernv: No suitable stop state for CPU-Hotplug. Offlined CPUs will busy wait"); } else { pr_info("cpuidle-powernv: Deepest stop: psscr = 0x%016llx,mask=0x%016llx\n", pnv_deepest_stop_psscr_val, pnv_deepest_stop_psscr_mask); } pr_info("cpuidle-powernv: Requested Level (RL) value of first deep stop = 0x%llx\n", pnv_first_deep_stop_state); out: kfree(psscr_val); kfree(psscr_mask); kfree(residency_ns); return rc; }
static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg) { struct msm_otg_platform_data *pdata; struct extcon_dev *ext_id, *ext_vbus; struct device_node *node = pdev->dev.of_node; struct property *prop; int len, ret, words; u32 val, tmp[3]; pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) return -ENOMEM; motg->pdata = pdata; pdata->phy_type = (enum msm_usb_phy_type)of_device_get_match_data(&pdev->dev); if (!pdata->phy_type) return 1; motg->link_rst = devm_reset_control_get(&pdev->dev, "link"); if (IS_ERR(motg->link_rst)) return PTR_ERR(motg->link_rst); motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy"); if (IS_ERR(motg->phy_rst)) motg->phy_rst = NULL; pdata->mode = usb_get_dr_mode(&pdev->dev); if (pdata->mode == USB_DR_MODE_UNKNOWN) pdata->mode = USB_DR_MODE_OTG; pdata->otg_control = OTG_PHY_CONTROL; if (!of_property_read_u32(node, "qcom,otg-control", &val)) if (val == OTG_PMIC_CONTROL) pdata->otg_control = val; if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2) motg->phy_number = val; motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL; motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN; motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX; if (of_get_property(node, "qcom,vdd-levels", &len) && len == sizeof(tmp)) { of_property_read_u32_array(node, "qcom,vdd-levels", tmp, len / sizeof(*tmp)); motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE]; motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN]; motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX]; } motg->manual_pullup = of_property_read_bool(node, "qcom,manual-pullup"); motg->switch_gpio = devm_gpiod_get_optional(&pdev->dev, "switch", GPIOD_OUT_LOW); if (IS_ERR(motg->switch_gpio)) return PTR_ERR(motg->switch_gpio); ext_id = ERR_PTR(-ENODEV); ext_vbus = ERR_PTR(-ENODEV); if (of_property_read_bool(node, "extcon")) { /* Each one of them is not mandatory */ ext_vbus = extcon_get_edev_by_phandle(&pdev->dev, 0); if (IS_ERR(ext_vbus) && PTR_ERR(ext_vbus) != -ENODEV) return PTR_ERR(ext_vbus); ext_id = extcon_get_edev_by_phandle(&pdev->dev, 1); if (IS_ERR(ext_id) && PTR_ERR(ext_id) != -ENODEV) return PTR_ERR(ext_id); } if (!IS_ERR(ext_vbus)) { motg->vbus.extcon = ext_vbus; motg->vbus.nb.notifier_call = msm_otg_vbus_notifier; ret = extcon_register_notifier(ext_vbus, EXTCON_USB, &motg->vbus.nb); if (ret < 0) { dev_err(&pdev->dev, "register VBUS notifier failed\n"); return ret; } ret = extcon_get_cable_state_(ext_vbus, EXTCON_USB); if (ret) set_bit(B_SESS_VLD, &motg->inputs); else clear_bit(B_SESS_VLD, &motg->inputs); } if (!IS_ERR(ext_id)) { motg->id.extcon = ext_id; motg->id.nb.notifier_call = msm_otg_id_notifier; ret = extcon_register_notifier(ext_id, EXTCON_USB_HOST, &motg->id.nb); if (ret < 0) { dev_err(&pdev->dev, "register ID notifier failed\n"); extcon_unregister_notifier(motg->vbus.extcon, EXTCON_USB, &motg->vbus.nb); return ret; } ret = extcon_get_cable_state_(ext_id, EXTCON_USB_HOST); if (ret) clear_bit(ID, &motg->inputs); else set_bit(ID, &motg->inputs); } prop = of_find_property(node, "qcom,phy-init-sequence", &len); if (!prop || !len) return 0; words = len / sizeof(u32); if (words >= ULPI_EXT_VENDOR_SPECIFIC) { dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words); return 0; } pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); if (!pdata->phy_init_seq) return 0; ret = of_property_read_u32_array(node, "qcom,phy-init-sequence", pdata->phy_init_seq, words); if (!ret) pdata->phy_init_sz = words; return 0; }
static int msm_otg_read_dt(struct platform_device *pdev, struct msm_otg *motg) { struct msm_otg_platform_data *pdata; const struct of_device_id *id; struct device_node *node = pdev->dev.of_node; struct property *prop; int len, ret, words; u32 val, tmp[3]; pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); if (!pdata) return -ENOMEM; motg->pdata = pdata; id = of_match_device(msm_otg_dt_match, &pdev->dev); pdata->phy_type = (enum msm_usb_phy_type) id->data; motg->link_rst = devm_reset_control_get(&pdev->dev, "link"); if (IS_ERR(motg->link_rst)) return PTR_ERR(motg->link_rst); motg->phy_rst = devm_reset_control_get(&pdev->dev, "phy"); if (IS_ERR(motg->phy_rst)) motg->phy_rst = NULL; pdata->mode = of_usb_get_dr_mode(node); if (pdata->mode == USB_DR_MODE_UNKNOWN) pdata->mode = USB_DR_MODE_OTG; pdata->otg_control = OTG_PHY_CONTROL; if (!of_property_read_u32(node, "qcom,otg-control", &val)) if (val == OTG_PMIC_CONTROL) pdata->otg_control = val; if (!of_property_read_u32(node, "qcom,phy-num", &val) && val < 2) motg->phy_number = val; motg->vdd_levels[VDD_LEVEL_NONE] = USB_PHY_SUSP_DIG_VOL; motg->vdd_levels[VDD_LEVEL_MIN] = USB_PHY_VDD_DIG_VOL_MIN; motg->vdd_levels[VDD_LEVEL_MAX] = USB_PHY_VDD_DIG_VOL_MAX; if (of_get_property(node, "qcom,vdd-levels", &len) && len == sizeof(tmp)) { of_property_read_u32_array(node, "qcom,vdd-levels", tmp, len / sizeof(*tmp)); motg->vdd_levels[VDD_LEVEL_NONE] = tmp[VDD_LEVEL_NONE]; motg->vdd_levels[VDD_LEVEL_MIN] = tmp[VDD_LEVEL_MIN]; motg->vdd_levels[VDD_LEVEL_MAX] = tmp[VDD_LEVEL_MAX]; } prop = of_find_property(node, "qcom,phy-init-sequence", &len); if (!prop || !len) return 0; words = len / sizeof(u32); if (words >= ULPI_EXT_VENDOR_SPECIFIC) { dev_warn(&pdev->dev, "Too big PHY init sequence %d\n", words); return 0; } pdata->phy_init_seq = devm_kzalloc(&pdev->dev, len, GFP_KERNEL); if (!pdata->phy_init_seq) { dev_warn(&pdev->dev, "No space for PHY init sequence\n"); return 0; } ret = of_property_read_u32_array(node, "qcom,phy-init-sequence", pdata->phy_init_seq, words); if (!ret) pdata->phy_init_sz = words; return 0; }
static int mdss_panel_parse_dt(struct platform_device *pdev, struct mdss_panel_common_pdata *panel_data) { struct device_node *np = pdev->dev.of_node; u32 res[6], tmp; u32 fbc_res[7]; int rc, i, len; const char *data; static const char *bl_ctrl_type, *pdest; bool fbc_enabled = false; rc = of_property_read_u32_array(np, "qcom,mdss-pan-res", res, 2); if (rc) { pr_err("%s:%d, panel resolution not specified\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.xres = (!rc ? res[0] : 640); panel_data->panel_info.yres = (!rc ? res[1] : 480); rc = of_property_read_u32(np, "qcom,mdss-pan-id", &tmp); if (!rc) mdss_panel_id = tmp; pr_info("%s: Panel ID = %d\n", __func__, mdss_panel_id); mdss_panel_flip_ud = of_property_read_bool(np, "qcom,mdss-pan-flip-ud"); if (mdss_panel_flip_ud) pr_info("%s: Panel FLIP UD\n", __func__); rc = of_property_read_u32_array(np, "qcom,mdss-pan-active-res", res, 2); if (rc == 0) { panel_data->panel_info.lcdc.xres_pad = panel_data->panel_info.xres - res[0]; panel_data->panel_info.lcdc.yres_pad = panel_data->panel_info.yres - res[1]; } rc = of_property_read_u32(np, "qcom,mdss-pan-bpp", &tmp); if (rc) { pr_err("%s:%d, panel bpp not specified\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.bpp = (!rc ? tmp : 24); rc = of_property_read_u32(np, "qcom,mdss-pan-width", &tmp); if (rc) pr_warn("%s:%d, panel width not specified\n", __func__, __LINE__); panel_data->panel_info.width = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-height", &tmp); if (rc) pr_warn("%s:%d, panel height not specified\n", __func__, __LINE__); panel_data->panel_info.height = (!rc ? tmp : 0); pdest = of_get_property(pdev->dev.of_node, "qcom,mdss-pan-dest", NULL); if (strlen(pdest) != 9) { pr_err("%s: Unknown pdest specified\n", __func__); return -EINVAL; } if (!strncmp(pdest, "display_1", 9)) panel_data->panel_info.pdest = DISPLAY_1; else if (!strncmp(pdest, "display_2", 9)) panel_data->panel_info.pdest = DISPLAY_2; else { pr_debug("%s: pdest not specified. Set Default\n", __func__); panel_data->panel_info.pdest = DISPLAY_1; } rc = of_property_read_u32_array(np, "qcom,mdss-pan-porch-values", res, 6); panel_data->panel_info.lcdc.h_back_porch = (!rc ? res[0] : 6); panel_data->panel_info.lcdc.h_pulse_width = (!rc ? res[1] : 2); panel_data->panel_info.lcdc.h_front_porch = (!rc ? res[2] : 6); panel_data->panel_info.lcdc.v_back_porch = (!rc ? res[3] : 6); panel_data->panel_info.lcdc.v_pulse_width = (!rc ? res[4] : 2); panel_data->panel_info.lcdc.v_front_porch = (!rc ? res[5] : 6); rc = of_property_read_u32(np, "qcom,mdss-pan-underflow-clr", &tmp); panel_data->panel_info.lcdc.underflow_clr = (!rc ? tmp : 0xff); bl_ctrl_type = of_get_property(pdev->dev.of_node, "qcom,mdss-pan-bl-ctrl", NULL); if ((bl_ctrl_type) && (!strncmp(bl_ctrl_type, "bl_ctrl_wled", 12))) { led_trigger_register_simple("bkl-trigger", &bl_led_trigger); pr_debug("%s: SUCCESS-> WLED TRIGGER register\n", __func__); panel_data->panel_info.bklt_ctrl = BL_WLED; } else if (!strncmp(bl_ctrl_type, "bl_ctrl_pwm", 11)) { panel_data->panel_info.bklt_ctrl = BL_PWM; rc = of_property_read_u32(np, "qcom,pwm-period", &tmp); if (rc) { pr_err("%s:%d, Error, panel pwm_period\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.pwm_period = tmp; rc = of_property_read_u32(np, "qcom,pwm-lpg-channel", &tmp); if (rc) { pr_err("%s:%d, Error, dsi lpg channel\n", __func__, __LINE__); return -EINVAL; } panel_data->panel_info.pwm_lpg_chan = tmp; tmp = of_get_named_gpio(np, "qcom,pwm-pmic-gpio", 0); panel_data->panel_info.pwm_pmic_gpio = tmp; } else if (!strncmp(bl_ctrl_type, "bl_ctrl_dcs", 11)) { panel_data->panel_info.bklt_ctrl = BL_DCS_CMD; } else { pr_debug("%s: Unknown backlight control\n", __func__); panel_data->panel_info.bklt_ctrl = UNKNOWN_CTRL; } rc = of_property_read_u32_array(np, "qcom,mdss-pan-bl-levels", res, 2); panel_data->panel_info.bl_min = (!rc ? res[0] : 0); panel_data->panel_info.bl_max = (!rc ? res[1] : 255); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-mode", &tmp); panel_data->panel_info.mipi.mode = (!rc ? tmp : DSI_VIDEO_MODE); rc = of_property_read_u32(np, "qcom,mdss-vsync-enable", &tmp); panel_data->panel_info.mipi.vsync_enable = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-hw-vsync-mode", &tmp); panel_data->panel_info.mipi.hw_vsync_mode = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-h-pulse-mode", &tmp); panel_data->panel_info.mipi.pulse_mode_hsa_he = (!rc ? tmp : false); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-h-power-stop", res, 3); panel_data->panel_info.mipi.hbp_power_stop = (!rc ? res[0] : false); panel_data->panel_info.mipi.hsa_power_stop = (!rc ? res[1] : false); panel_data->panel_info.mipi.hfp_power_stop = (!rc ? res[2] : false); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-bllp-power-stop", res, 2); panel_data->panel_info.mipi.bllp_power_stop = (!rc ? res[0] : false); panel_data->panel_info.mipi.eof_bllp_power_stop = (!rc ? res[1] : false); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-traffic-mode", &tmp); panel_data->panel_info.mipi.traffic_mode = (!rc ? tmp : DSI_NON_BURST_SYNCH_PULSE); rc = of_property_read_u32(np, "qcom,mdss-pan-insert-dcs-cmd", &tmp); panel_data->panel_info.mipi.insert_dcs_cmd = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-pan-wr-mem-continue", &tmp); panel_data->panel_info.mipi.wr_mem_continue = (!rc ? tmp : 0x3c); rc = of_property_read_u32(np, "qcom,mdss-pan-wr-mem-start", &tmp); panel_data->panel_info.mipi.wr_mem_start = (!rc ? tmp : 0x2c); rc = of_property_read_u32(np, "qcom,mdss-pan-te-sel", &tmp); panel_data->panel_info.mipi.te_sel = (!rc ? tmp : 1); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dst-format", &tmp); panel_data->panel_info.mipi.dst_format = (!rc ? tmp : DSI_VIDEO_DST_FORMAT_RGB888); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-vc", &tmp); panel_data->panel_info.mipi.vc = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-rgb-swap", &tmp); panel_data->panel_info.mipi.rgb_swap = (!rc ? tmp : DSI_RGB_SWAP_RGB); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-data-lanes", res, 4); panel_data->panel_info.mipi.data_lane0 = (!rc ? res[0] : true); panel_data->panel_info.mipi.data_lane1 = (!rc ? res[1] : false); panel_data->panel_info.mipi.data_lane2 = (!rc ? res[2] : false); panel_data->panel_info.mipi.data_lane3 = (!rc ? res[3] : false); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dlane-swap", &tmp); panel_data->panel_info.mipi.dlane_swap = (!rc ? tmp : 0); rc = of_property_read_u32_array(np, "qcom,mdss-pan-dsi-t-clk", res, 2); panel_data->panel_info.mipi.t_clk_pre = (!rc ? res[0] : 0x24); panel_data->panel_info.mipi.t_clk_post = (!rc ? res[1] : 0x03); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-stream", &tmp); panel_data->panel_info.mipi.stream = (!rc ? tmp : 0); rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-mdp-tr", &tmp); panel_data->panel_info.mipi.mdp_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (panel_data->panel_info.mipi.mdp_trigger > 6) { pr_err("%s:%d, Invalid mdp trigger. Forcing to sw trigger", __func__, __LINE__); panel_data->panel_info.mipi.mdp_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-dma-tr", &tmp); panel_data->panel_info.mipi.dma_trigger = (!rc ? tmp : DSI_CMD_TRIGGER_SW); if (panel_data->panel_info.mipi.dma_trigger > 6) { pr_err("%s:%d, Invalid dma trigger. Forcing to sw trigger", __func__, __LINE__); panel_data->panel_info.mipi.dma_trigger = DSI_CMD_TRIGGER_SW; } rc = of_property_read_u32(np, "qcom,mdss-pan-dsi-frame-rate", &tmp); panel_data->panel_info.mipi.frame_rate = (!rc ? tmp : 60); rc = of_property_read_u32(np, "qcom,mdss-pan-clk-rate", &tmp); panel_data->panel_info.clk_rate = (!rc ? tmp : 0); data = of_get_property(np, "qcom,panel-phy-regulatorSettings", &len); if ((!data) || (len != 7)) { pr_err("%s:%d, Unable to read Phy regulator settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.regulator[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-timingSettings", &len); if ((!data) || (len != 12)) { pr_err("%s:%d, Unable to read Phy timing settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.timing[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-strengthCtrl", &len); if ((!data) || (len != 2)) { pr_err("%s:%d, Unable to read Phy Strength ctrl settings", __func__, __LINE__); goto error; } phy_params.strength[0] = data[0]; phy_params.strength[1] = data[1]; data = of_get_property(np, "qcom,panel-phy-bistCtrl", &len); if ((!data) || (len != 6)) { pr_err("%s:%d, Unable to read Phy Bist Ctrl settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.bistCtrl[i] = data[i]; data = of_get_property(np, "qcom,panel-phy-laneConfig", &len); if ((!data) || (len != 45)) { pr_err("%s:%d, Unable to read Phy lane configure settings", __func__, __LINE__); goto error; } for (i = 0; i < len; i++) phy_params.laneCfg[i] = data[i]; panel_data->panel_info.mipi.dsi_phy_db = &phy_params; fbc_enabled = of_property_read_bool(np, "qcom,fbc-enabled"); if (fbc_enabled) { pr_debug("%s:%d FBC panel enabled.\n", __func__, __LINE__); panel_data->panel_info.fbc.enabled = 1; rc = of_property_read_u32_array(np, "qcom,fbc-mode", fbc_res, 7); panel_data->panel_info.fbc.target_bpp = (!rc ? fbc_res[0] : panel_data->panel_info.bpp); panel_data->panel_info.fbc.comp_mode = (!rc ? fbc_res[1] : 0); panel_data->panel_info.fbc.qerr_enable = (!rc ? fbc_res[2] : 0); panel_data->panel_info.fbc.cd_bias = (!rc ? fbc_res[3] : 0); panel_data->panel_info.fbc.pat_enable = (!rc ? fbc_res[4] : 0); panel_data->panel_info.fbc.vlc_enable = (!rc ? fbc_res[5] : 0); panel_data->panel_info.fbc.bflc_enable = (!rc ? fbc_res[6] : 0); rc = of_property_read_u32_array(np, "qcom,fbc-budget-ctl", fbc_res, 3); panel_data->panel_info.fbc.line_x_budget = (!rc ? fbc_res[0] : 0); panel_data->panel_info.fbc.block_x_budget = (!rc ? fbc_res[1] : 0); panel_data->panel_info.fbc.block_budget = (!rc ? fbc_res[2] : 0); rc = of_property_read_u32_array(np, "qcom,fbc-lossy-mode", fbc_res, 4); panel_data->panel_info.fbc.lossless_mode_thd = (!rc ? fbc_res[0] : 0); panel_data->panel_info.fbc.lossy_mode_thd = (!rc ? fbc_res[1] : 0); panel_data->panel_info.fbc.lossy_rgb_thd = (!rc ? fbc_res[2] : 0); panel_data->panel_info.fbc.lossy_mode_idx = (!rc ? fbc_res[3] : 0); } else { pr_debug("%s:%d Panel does not support FBC.\n", __func__, __LINE__); panel_data->panel_info.fbc.enabled = 0; panel_data->panel_info.fbc.target_bpp = panel_data->panel_info.bpp; } mdss_dsi_parse_dcs_cmds(np, &panel_data->on_cmds, "qcom,panel-on-cmds", "qcom,on-cmds-dsi-state"); mdss_dsi_parse_dcs_cmds(np, &panel_data->off_cmds, "qcom,panel-off-cmds", "qcom,off-cmds-dsi-state"); return 0; error: return -EINVAL; }
static struct tegra_emc_pdata *tegra_emc_dt_parse_pdata( struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; struct device_node *tnp, *iter; struct tegra_emc_pdata *pdata; int ret, i, num_tables; if (!np) return NULL; if (of_find_property(np, "nvidia,use-ram-code", NULL)) { tnp = tegra_emc_ramcode_devnode(np); if (!tnp) dev_warn(&pdev->dev, "can't find emc table for ram-code 0x%02x\n", tegra_bct_strapping); } else tnp = of_node_get(np); if (!tnp) return NULL; num_tables = 0; for_each_child_of_node(tnp, iter) if (of_device_is_compatible(iter, "nvidia,tegra20-emc-table")) num_tables++; if (!num_tables) { pdata = NULL; goto out; } pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); pdata->tables = devm_kzalloc(&pdev->dev, sizeof(*pdata->tables) * num_tables, GFP_KERNEL); i = 0; for_each_child_of_node(tnp, iter) { u32 prop; ret = of_property_read_u32(iter, "clock-frequency", &prop); if (ret) { dev_err(&pdev->dev, "no clock-frequency in %s\n", iter->full_name); continue; } pdata->tables[i].rate = prop; ret = of_property_read_u32_array(iter, "nvidia,emc-registers", pdata->tables[i].regs, TEGRA_EMC_NUM_REGS); if (ret) { dev_err(&pdev->dev, "malformed emc-registers property in %s\n", iter->full_name); continue; } i++; }